AN634 P O W E R S U PP L Y C O N S I D E R A T I O N S C M O S I S O L A T I O N P R O D U C TS FOR S IL IC ON L A B S 1. Introduction This application note helps users understand the operation of Silicon Labs' CMOS isolator products when subjected to various power supply operating conditions. A calculator utility is also presented that allows the user to quickly and easily determine digital isolator power consumption. The CMOS digital isolator channel block diagram of Figure 1 consists of two die separated by a capacitive differential isolation barrier and powered by individual (or otherwise mutually isolated) power supplies. For the purposes of safety isolation, VDD1 and VDD2 must be isolated from each other; that is, VDD1 must be referenced only to GND1, and VDD2 must be referenced only to GND2. This ensures that IDD1 circulates only within Side 1, and IDD2 circulates only within Side 2, and no current flows between Side 1 and Side 2 under any conditions. CMOS Isolator Channel IDD1 VDD1 VDD1 SIDE 2 DIE SIDE 1 DIE VREG OSC OSC Isolation Barrier VREG IDD2 VDD2 01101001 Tx INPUT 01101001 01101001 Rx 01101001 01101001 VDD2 OUTPUT 01101001 GND1 GND2 Figure 1. CMOS Digital Isolator Block Diagram A simple on/off keying scheme is used to transmit data across the isolator channel. A logic high level on the channel input enables the transmitter (TX) to generate a high-frequency signal (carrier) that propagates through the capacitive isolation barrier to the receiver (RX). The receiver then asserts logic high on the channel output when sufficient in-band carrier energy is detected. Conversely, a logic low level at the channel input pin disables the transmitter, discontinuing the carrier and causing the receiver to drive the channel output low. This deceptively simple architecture offers significant benefits compared to other isolation schemes, including: Significantly higher device integration (up to six channels per package) Greater operating stability over supply voltage, temperature, and device age Significantly lower power consumption Tighter timing characteristics for more consistent end-system performance Significantly higher speed data transmission CMOS process technology for high reliability (60+ year isolation barrier lifetime) High 35 kV/µs (Si86xx) and 25 kV/µs (Si84xx) common mode transient immunity (CMTI) High RF and magnetic field immunity Low EMI (meets FCC Class B Part 15) Highly competitive price per channel Rev. 0.1 9/11 Copyright © 2011 by Silicon Laboratories AN634 AN634 2. Ground References +5V Isolation Barrier VDD1 Supply 1 5V Side 1 0V +5V VDD2 Side 2 GND1 Supply 2 5V +5V GND2 Isolator Ground 0V System Ground 0V Figure 2. Isolator Power Configuration Digital isolators are often used in high common-mode voltage environments for safety and/or level shifting. It is very important to be mindful of the ground references during system design and testing to ensure proper system operation, as illustrated in Figures 2 and 3. Figure 2 shows a typical isolator configuration in which each side of the isolator is powered by a dedicated power supply. In this case, GND1 and GND2 are the only ground references for VDD1 and VDD2, respectively. VDD1 is +5 V with respect to GND1; VDD2 is +5 V with respect to GND2, and no current flows between the two sides. +5V Supply 1 5V VDD1 Side 1 Isolation Barrier VDD2 (+5V + VCM) Supply 2 5V Side 2 +5V 5V Circuits 5V Circuits 805V 0V GND2 GND1 VCM VCM Isolator Ground 800V 0V System Ground Figure 3. Isolator Circuit with Side 2 800 Vdc Common Mode Voltage An 800 Vdc common mode voltage (VCM) referenced Side 2 system ground is added in Figure 3. While the ground reference relationships of VDD1 and GND 1 are unchanged, Side 2 now has two different ground reference points because of the presence of VCM. The voltage at VDD2 with respect to GND2 (isolator ground) is +5 V, but the voltage at VDD2 with respect to the Side 2 system ground is 805 Vdc due to VCM. Therefore, any external 5 V circuits in parallel with Supply 2 must be referenced to GND2, and not the Side 2 system ground. Again, close attention to ground reference points is critical when designing with or testing any galvanically-isolated circuit. 2 Rev. 0.1 AN634 3. Channel Behavior During Power Supply State Changes 3.1. Channel Operation During Power-Up and Power Down Figure 4 shows isolator channel behavior during normal operation. Isolator side A and side B have under-voltage lockout detectors (UVLO) that inhibit isolator operation any time VDD is below the UVLO– threshold and enable isolator operation when VDD is at or above the UVLO+ threshold, ensuring smooth, glitch-free startup and shutdown behavior. Either side of the isolator may enter or exit UVLO independently. Referring to Figure 4, isolator startup begins at time tSTART after VDD is at or above UVLO+. Should VDD on a given side momentarily fail, the associated UVLO will unpower that side at time tSD after VDD falls to or below UVLO–, and restore power tSTART after VDD is at or above UVLO+. (For more information on startup timing parameters, please see the Si86xx and/or Si84xx digital isolator data sheets.) UVLO+ UVLO‐ VDD1 UVLO+ UVLO‐ VDD2 INPUT tSTART tSD tSTART tSTART tPHL tPLH OUTPUT Figure 4. Channel Behavior During Startup and Shutdown 3.2. VDD Bypass Capacitors The VDD1 and VDD2 supply inputs must each be bypassed with a parallel combination of 1 µF and 0.1 µF capacitors. These capacitors must be mounted as close to the VDD pins as possible and referenced to the shortest possible ground path, and the bypass capacitors must be low inductance types (e.g. X5R, X7R). 3.3. Channel Operation During Power Loss Figure 5 shows digital isolator operation during all possible combinations of powered and unpowered states. (In this document, a “powered” state is defined as VDD(min) < VDD < VDD(max), and an “unpowered” state is defined as 0 V.) Referring to Figure 5A, the isolator operates normally (i.e., data out = data in) when both isolator sides are powered, the enable input (EN) is pulled high (or not connected), and data is applied to the input pin. (Note: it is recommended the EN input be connected to VDD when the digital isolator is operated in electrically noisy environments.) Rev. 0.1 3 AN634 Input Side Supply Powered Output Side Supply Unpowered Powered Powered Unpowered Unpowered Input Data Enable Input Default Output State (see text) Output Data Both Sides Powered (5A) Hi‐Z Default Output State (see text) Input Side Unpowered (5B) Hi‐Z (see text) Output Side Unpowered (5C) Both Sides Unpowered (5D) Figure 5. Digital Isolator Behavior During Power Cycling Figure 5B shows isolator behavior when the input side is unpowered and the output side is powered, which causes the isolator output to retreat to its default state (1 or 0, depending on the isolator part number). Note that a logic low on EN causes the data output go to a high impedance state as long as the output side remains powered. Normal isolator operation resumes in less than 1 µs after the input side is again powered. Referring to Figure 5C, the loss of the output-side supply causes the driver to assume a high-impedance state until output-side power is restored. During this time, external impedances and/or parasitics may cause the isolator output to float a random voltage level (i.e., “undetermined state”). Again, powering the output side causes the isolator to return to normal operation within 1 µs. This is also true when both sides of the isolator are unpowered (Figure 5D). While the isolator input side is unpowered, input data voltage swing may power the input-side die through the on-chip ESD diode. This is not a recommended isolator operating mode, and performance is not guaranteed. The contents of this paragraph are summarized in Table 1. 4 Rev. 0.1 AN634 3.4. Eliminating Undetermined Output States Loss of output-side power can cause the output to be externally pulled to an undetermined state. As shown in Figure 6, output-side power failure disables the output buffer, creating a high-impedance output condition where externally-coupled noise and/or leakage current from local dc sources can create arbitrary output voltage levels. This issue can be corrected by adding a load resistor from the output pin to ground or a local VDD source to ensure a known output state in the event of an output-side power failure. Table 1. CMOS Isolator Logic Operation Enable VDDI VDDO Input1,2,3,4,5 State1,6,7 State1,6,7 H H or NC Powered Powered H L H or NC Powered Powered L X9 L Powered Powered Hi-Z10 X9 H or NC Unpowered Powered L11 H11 X9 L Unpowered Powered Hi-Z10 X9 X9 Powered VI Input1,2 Comments VO Output1,2,8 Enabled, normal operation. Disabled. Upon transition of VDDI from unpowered to powered, Vo returns to the same state as VI in lass than 1 µs. Disabled. Unpowered Undetermined Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 µs if EN is in either the high or NC state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1 µs if EN is L. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the 4. isolator is operating in noisy environments. 5. Enable function: the VO output pin is in the high-impedance state when the EN pin is low. 6. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 7. Powered state is defined as V 8. Depending on the part number, the Si86xx digital isolators can default to the high or low state when output-side power is lost. Please see the Si86xx data sheet for ordering information. 9. DD(min) < VDD < VDD(max) V. 10. Unpowered state is defined as VDD = 0 V. 11. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. Rev. 0.1 5 AN634 4. Calculating Isolator Power Consumption Calculating isolator supply current and power dissipation can be cumbersome since results are impacted by the values of input and output supply voltage, output load, signal duty cycle, internal bias currents, data rate, and so on. The digital isolator power calculator (Figure 6) precisely calculates isolator power dissipation, and can be found at www.silabs.com/support/Pages/isolator-power-calculator.aspx. Using the power calculator is simple; the user can specify an isolator ordering part number or have the power calculator locate the best isolator match based on the user's channel configuration, isolation rating, supply voltages, and output default state (Figure 6, Boxes 1 and 2). The user then enters values for the data rate, duty cycle, and output load capacitance for each isolator channel (Figure 6, Box 3). Clicking on the “Get Results” button causes the calculated voltage, current and power to be displayed in the “View Results” field on the right side of the calculator. 5. Related Documents Si84xx and Si86xx data sheets Labs white paper: CMOS Digital Isolators_WP.pdf; Title: “CMOS Digital Isolators Supersede Optocouplers in Industrial Applications” Silicon Labs application note “AN583:"Safety Considerations and Layout Requirements for Digital Isolators” Silicon Labs application note: “AN520: CMOS Advanced Galvanic Isolators for Medical Electronics” Silicon Labs application note “AN553: Decoupling Recommendations for Si84xx Digital Isolators” Silicon Labs application note “AN611: Using the ISOvolt Reference Design” Silicon 6 Rev. 0.1 AN634 Figure 6. Silicon Labs Isolator Power Consumption Calculator Rev. 0.1 7 AN634 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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