Si8440/1/2 Q U A D -C H A N N E L D I G I TA L I S O L A T O R Features Pin Assignments High-speed operation: DC – 150 Mbps Low propagation delay: <10 ns Wide Operating Supply Voltage: 2.375–5.5 V Low power: I1 + I2 < 12 mA/channel at 100 Mbps Precise timing: 2 ns pulse width distortion 1 ns channel-channel matching 2 ns pulse width skew 2500 VRMS isolation Transient Immunity: >25 kV/µs Tri-state outputs with ENABLE control DC correct No start-up initialization required <10 µs Startup Time High temperature operation: 125 °C at 100 Mbps 100 °C at 150 Mbps Wide body SOIC-16 package Wide Body SOIC VDD1 GND1 A1 A2 A3 A4 EN1 GND1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD2 GND2 B1 B2 B3 B4 EN2 GND2 Top View Applications Isolated switch mode supplies Isolated ADC, DAC Motor control Power factor correction systems Safety Regulatory Approvals UL recognition:2500 VRMS for 1 Minute per UL1577 CSA component acceptance notice #5A * All Pending VDE certification conformity DIN EN 60747-5-2 (VDE0884 Part 2):2003-01 DIN EN60950(VDE0805): 2001-12;EN60950:2000 VIORM = 560 VPEAK Description Silicon Lab's family of digital isolators are CMOS devices that employ an RF coupler to transmit digital information across an isolation barrier. Very high speed operation at low power levels is achieved. These parts are available in a 16-pin wide body SOIC package. Three speed grade options (1, 10, 100 Mbps) are available and achieve typical propagation delay of less than 10 ns. Block Diagram Si8440 Si8441 Si8442 A1 B1 A1 B1 A1 B1 A2 B2 A2 B2 A2 B2 A3 B3 A3 B3 A3 B3 A4 B4 A4 B4 A4 B4 NC EN2 EN1 EN2 EN1 Rev. 0.3 4/06 EN2 Copyright © 2006 by Silicon Laboratories Si8440/1/2 Si8440/1/2 2 Rev. 0.3 Si8440/1/2 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1. Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2. Input and Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3. Enable Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.4. RF Immunity and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . . . 17 4.5. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Rev. 0.3 3 Si8440/1/2 1. Electrical Specifications Table 1. Electrical Characteristics (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 C°) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL Enable Input High Current IENH VENx = VIH — 4 — µA Enable Input Low Current IENL VENx = VIL — 20 — µA DC Supply Current (All inputs 0 V or at Supply) Si8440-A,-B,-C, VDD1 All inputs 0 DC — 7.5 — mA Si8440-A,-B,-C, VDD2 All inputs 0 DC — 7 — mA Si8440-A,-B,-C, VDD1 All inputs 1 DC — 15 — mA Si8440-A,-B,-C, VDD2 All inputs 1 DC — 6.5 — mA Si8441-A,-B,-C, VDD1 All inputs 0 DC — 8.7 — mA Si8441-A,-B,-C, VDD2 All inputs 0 DC — 11 — mA Si8441-A,-B,-C, VDD1 All inputs 1 DC — 14 — mA Si8441-A,-B,-C, VDD2 All inputs 1 DC — 12.5 — mA Si8442-A,-B,-C, VDD1 All inputs 0 DC — 10 — mA Si8442-A,-B,-C, VDD2 All inputs 0 DC — 10 — mA Si8442-A,-B,-C, VDD1 All inputs 1 DC — 13 — mA Si8442-A,-B,-C, VDD2 All inputs 1 DC — 13 — mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8440-B,-C, VDD1 — 11 — mA Si8440-B,-C, VDD2 — 9 — mA Si8441-B,-C, VDD1 — 12 — mA Si8441-B,-C, VDD2 — 13.5 — mA Si8442-B,-C, VDD1 — 12.5 — mA Si8442-B,-C, VDD2 — 12.5 — mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8440-C, VDD1 — 12 — mA Si8440-C, VDD2 — 27 — mA Si8441-C, VDD1 — 16 — mA Si8441-C, VDD2 — 27 — mA Si8442-C, VDD1 — 21 — mA Si8442-C, VDD2 — 21 — mA 4 Rev. 0.3 Si8440/1/2 Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 C°) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 100 Mbps Minimum Pulse Width — 5 — ns tPHL, tPLH — 7.5 — ns PWD — 1 — ns tPSK — 6 — ns tPSKCD/OD — 0.5 — ns Timing Characteristics Propagation Delay1 Pulse Width Distortion |tPLH - tPHL|1 Propagation Delay Skew2 Channel-Channel Skew 3 Output Rise Time C1 = 15 pF — 2 — ns Output Fall Time C1 = 15 pF — 2 — ns Common Mode Transient Immunity at Logic Low Output4 CML 25 30 — kV/µs Common Mode Transient Immunity at Logic High Output4 CMH 25 30 — kV/µs Enable to Data Valid ten1 — 5 — ns Enable to Data Tri-State ten2 — 5 — ns Start-up Time5 tSU — 3 — µs Notes: 1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 5. Start-up time is the time period from the application of power to valid data at the output. INPUT (V IX) ENABLE 50% tPLH tPHL OUTPUTS OUTPUT (V OX) ten1 50% ten2 Figure 1. ENABLE Timing Diagram Figure 2. Propagation Delay Timing Rev. 0.3 5 Si8440/1/2 Table 2. Electrical Characteristics (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 C°) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL Enable Input High Current IENH VENx = VIH — 4 — µA Enable Input Low Current IENL VENx = VIL — 20 — µA DC Supply Current (All inputs 0 V or at supply) Si8440-A,-B,-C, VDD1 All inputs 0 DC — 7.3 — mA Si8440-A,-B,-C, VDD2 All inputs 0 DC — 6.5 — mA Si8440-A,-B,-C, VDD1 All inputs 1 DC — 14.3 — mA Si8440-A,-B,-C, VDD2 All inputs 1 DC — 6 — mA Si8441-A,-B,-C, VDD1 All inputs 0 DC — 8.3 — mA Si8441-A,-B,-C, VDD2 All inputs 0 DC — 10.8 — mA Si8441-A,-B,-C, VDD1 All inputs 1 DC — 13.3 — mA Si8441-A,-B,-C, VDD2 All inputs 1 DC — 11.8 — mA Si8442-A,-B,-C, VDD1 All inputs 0 DC — 9 — mA Si8442-A,-B,-C, VDD2 All inputs 0 DC — 9 — mA Si8442-A,-B,-C, VDD1 All inputs 1 DC — 12 — mA Si8442-A,-B,-C, VDD2 All inputs 1 DC — 12 — mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8440-B,-C, VDD1 — 11 — mA Si8440-B,-C, VDD2 — 8 — mA Si8441-B,-C, VDD1 — 11.4 — mA Si8441-B,-C, VDD2 — 14.5 — mA Si8442-B,-C, VDD1 — 11.5 — mA Si8442-B,-C, VDD2 — 11.5 — mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8440-C, VDD1 — 11.4 — mA Si8440-C, VDD2 — 18 — mA Si8441-C, VDD1 — 12.5 — mA Si8441-C, VDD2 — 21 — mA Si8442-C, VDD1 — 17.5 — mA Si8442-C, VDD2 — 17.5 — mA 6 Rev. 0.3 Si8440/1/2 Table 2. Electrical Characteristics (Continued) (VDD1 = 3.3 V, VDD2 = 3.3 V, TA = –40 to 125 C°) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 100 Mbps Minimum Pulse Width — 5 — ns tPHL,tPLH — 7.5 — ns PWD — 1 — ns tPSK — 8 — ns tPSKCD/OD — 1 — ns Timing Characteristics Propagation Delay1 Pulse Width Distortion |tPLH - tPHL|1 Propagation Delay Skew2 Channel-Channel Skew 3 Output Rise Time C1 = 15 pF — 2 — ns Output Fall Time C1 = 15 pF — 2 — ns Common Mode Transient Immunity at Logic Low Output4 CML 25 30 — kV/µs Common Mode Transient Immunity at Logic High Output4 CMH 25 30 — kV/µs Enable to Data Valid ten1 — 5 — ns Enable to Data Tri-State ten2 — 5 — ns Start-up Time5 tSU — 3 — µs Notes: 1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 5. Start-up time is the time period from the application of power to valid data at the output. Rev. 0.3 7 Si8440/1/2 Table 3. Electrical Characteristics (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 C°) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V — — ±10 µA Input Leakage Current IL Enable Input High Current IENH VENx = VIH — 4 — µA Enable Input Low Current IENL VENx = VIL — 20 — µA DC Supply Current (All inputs 0 V or at supply) Si8440-A,-B,-C, VDD1 All inputs 0 DC — 6.8 — mA Si8440-A,-B,-C, VDD2 All inputs 0 DC — 6.3 — mA Si8440-A,-B,-C, VDD1 All inputs 1 DC — 12.5 — mA Si8440-A,-B,-C, VDD2 All inputs 1 DC — 5.8 — mA Si8441-A,-B,-C, VDD1 All inputs 0 DC — 7.8 — mA Si8441-A,-B,-C, VDD2 All inputs 0 DC — 9.8 — mA Si8441-A,-B,-C, VDD1 All inputs 1 DC — 12.5 — mA Si8441-A,-B,-C, VDD2 All inputs 1 DC — 11 — mA Si8442-A,-B,-C, VDD1 All inputs 0 DC — 8.8 — mA Si8442-A,-B,-C, VDD2 All inputs 0 DC — 8.5 — mA Si8442-A,-B,-C, VDD1 All inputs 1 DC — 11.5 — mA Si8442-A,-B,-C, VDD2 All inputs 1 DC — 11.5 — mA 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8440-B,-C, VDD1 — 10.2 — mA Si8440-B,-C, VDD2 — 7 — mA Si8441-B,-C, VDD1 — 10.5 — mA Si8441-B,-C, VDD2 — 11.5 — mA Si8442-B,-C, VDD1 — 11 — mA Si8442-B,-C, VDD2 — 11 — mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8440-C, VDD1 — 10.8 — mA Si8440-C, VDD2 — 14.5 — mA Si8441-C, VDD1 — 12.5 — mA Si8441-C, VDD2 — 17 — mA Si8442-C, VDD1 — 15 — mA Si8442-C, VDD2 — 15 — mA 8 Rev. 0.3 Si8440/1/2 Table 3. Electrical Characteristics (Continued) (VDD1 = 2.5 V, VDD2 = 2.5 V, TA = –40 to 100 C°) Parameter Symbol Test Condition Min Typ Max Unit Maximum Data Rate 0 — 100 Mbps Minimum Pulse Width — 5 — ns tPHL,tPLH — 12 — ns PWD — 1.5 — ns tPSK — 10 — ns tPSKCD/OD — 1 — ns Timing Characteristics Propagation Delay1 Pulse Width Distortion |tPLH - tPHL|1 Propagation Delay Skew2 Channel-Channel Skew 3 Output Rise Time C1 = 15 pF — 2 — ns Output Fall Time C1 = 15 pF — 2 — ns Common Mode Transient Immunity at Logic Low Output4 CML 25 30 — kV/µs Common Mode Transient Immunity at Logic High Output4 CMH 25 30 — kV/µs Enable to Data Valid ten1 — 5 — ns Enable to Data Tri-State ten2 — 5 — ns Start-up Time5 tSU — 3 — µs Notes: 1. tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 2. tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 3. Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 4. CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 5. Start-up time is the time period from the application of power to valid data at the output. Rev. 0.3 9 Si8440/1/2 Table 4. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit TA 100 Mbps, 15 pF, 5 V –40 25 125 ºC 150 Mbps, 15 pF, 5 V 0 25 100 ºC VDD1 2.375 — 5.5 V VDD2 2.375 — 5.5 V Ambient Operating Temperature* Supply Voltage *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 5. Absolute Maximum Ratings Parameter Symbol Min Typ Max Unit TSTG –65 — 150 ºC TA –40 — 125 ºC VDD1, VDD2 –0.5 — 6 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel LO — — 10 mA Lead Solder Temperature (10s) — — 260 ºC Maximum Isolation Voltage — — 4000 VDC Storage Temperature Ambient Temperature Under Bias Supply Voltage Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Package Characteristics Parameter Symbol Resistance (Input-Output)1 Capacitance (Input-Output)1 Input Capacitance2 Test Condition RIO CIO f = 1 MHz CI IC Junction-to-Case Thermal Resistance, Side 1 θJCI IC Junction-to-Case Thermal Resistance, Side 2 θJCO Thermocouple located at center of package underside Min Typ Max Unit — 1012 — Ω — 1.4 — pF — 4.0 — pF — 33 — ºC/W — 28 — ºC/W Notes: 1. Device considered a 2-terminal device; Pins 1– 8 shorted together and pins 9–16 shorted together. 2. Input capacitance is from any input data pin to ground. 10 Rev. 0.3 Si8440/1/2 Table 7. Regulatory Information The Si84xx have been approved by the organizations listed below. UL1 VDE2 CSA Recognized under 1577 component Approved under CSA Component recognition program1 Acceptance Notice #5A Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003012 Basic insulation, 2500 V RMS isolation voltage Reinforced insulation per CSA Basic insulation, 560 V peak 60950-1-03 and IEC 60950-1, 400 V Complies with DIN EN 60747-5-2 RMS maximum working voltage (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000 Reinforced insulation, 560 V peak File E257455 File 2500035643 File 5006301-4880-0001 Notes: 1. In accordance with UL1577, each Si84xx is proof tested by applying an insulation test voltage > 3000 V RMS for 1 second (current leakage detection limit = 5 µA). 2. In accordance with DIN EN 60747-5-2, each Si84xx is proof tested by applying an insulation test voltage > 1050 V peak for 1 second (partial discharge detection limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval. Table 8. Insulation and Safety-related Specifications Parameter Symbol Rated Dielectric Insulation Voltage Test Condition Value Unit 1 minute duration 2500 VRMS Minimum External Air Gap (Clearance) L(IO1) Measured from input terminals to output terminals, shortest distance through air 7.7 min mm Minimum External Tracking (Creepage) L(IO2) Measured from input terminals to output terminals, shortest distance path along body 8.1 mm Insulation distance through insulation 0.017 min mm DIN IEC 112/VDE 0303 Part 1 >175 V Material Group (DIN VDE 0110, 1/89, Table 1) IIIa Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Basic Isolation Group CTI Rev. 0.3 11 Si8440/1/2 Table 9. DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics1,2 Description Symbol Installation Classification per DIN VDE 0110 For Rated Mains Voltages < 150 VRMS For Rated Mains Voltages < 300 VRMS For Rated Mains Voltages < 400 VRMS Characteristic Unit I-IV I-III I-II Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage VIORM 560 VPEAK VPR 1050 VPEAK Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1 (VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC) After Input and/or Safety Test Subgroup 2/3 (VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC) VPR 896 VPEAK 672 VPEAK Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) VTR 4000 VPEAK Safety-Limiting Values (Maximum value allowed in the event of a failure; also see the thermal derating curve, Figure 3) Case Temperature Side 1 Current Side 2 Current TS IS1 IS2 150 265 335 ºC mA mA Insulation Resistance at TS, VIO = 500 V RS >109 Ω Input to Output Test Voltage, Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) Notes: 1. This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. 2. The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage. 350 Safety-Limiting Current (mA) 300 250 SIDE #2 200 150 SIDE #1 100 50 0 0 50 100 Case Temperature (ºC) 150 200 Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 12 Rev. 0.3 Si8440/1/2 2. Typical Performance Characteristics 15 20 18 5V Current (mA) Current (mA) 13 11 3.3V 9 2.5V 7 5V 16 3.3V 14 12 5 2.5V 10 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 Data Rate (Mbps) 40 50 60 70 80 Figure 4. Si8440 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation 100 Figure 6. Si8441 Typical VDD1 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation 30 30 5V 5V 25 25 Current (mA) Current (mA) 90 Data Rate (Mbps) 3.3V 20 15 2.5V 10 3.3V 20 15 2.5V 10 5 5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 Data Rate (Mbps) 40 50 60 70 80 90 100 Data Rate (Mbps) Figure 5. Si8440 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Figure 7. Si8441 Typical VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) 30 Current (mA) 25 5V 20 3.3V 15 2.5V 10 5 0 10 20 30 40 50 60 70 80 90 100 Data Rate (Mbps) Figure 8. Si8442 Typical VDD1 or VDD2 Supply Current vs. Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load) Rev. 0.3 13 Si8440/1/2 10 Delay (ns) 9 8 Falling Edge 7 6 Rising Edge 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 9. Propagation Delay vs. Temperature 5 V Operation 10 Delay (ns) 9 Rising Edge 8 Falling Edge 7 6 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 10. Propagation Delay vs. Temperature 3.3 V Operation 15 Delay (ns) 13 Rising Edge 11 Falling Edge 9 7 5 -40 -20 0 20 40 60 80 100 120 Temperature (Degrees C) Figure 11. Propagation Delay vs. Temperature 2.5 V Operation 14 Rev. 0.3 Si8440/1/2 3. Application Information 3.1. Theory of Operation The operation of an Si8440 channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si8440 channel is shown in Figure 12. A channel consists of an RF transmitter and receiver separated by a transformer. Referring to the transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying and applies the resulting waveform to the primary of the transformer. The receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. 3.2. Eye Diagram Figure 13 illustrates an eye-diagram taken on an Si8440-IS. The test used an Anritsu (MP1763C) Pulse Pattern Generator for the data source. The output of the generator's clock and data from an Si8440-IS were captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that very low pulse width distortion and very little jitter were exhibited. TRANSMITTER RF OSCILLATOR A RECEIVER MODULATOR DEMODULATOR B Figure 12. Simplified Channel Diagram Figure 13. Eye Diagram Rev. 0.3 15 Si8440/1/2 4. Layout Recommendations 4.1. Supply Bypass Dielectric isolation is a set of specifications produced by the safety regulatory agencies from around the world that describes the physical construction of electrical equipment that derives power from a high-voltage power system such as 100–240 VAC systems or industrial power systems. The dielectric test (or HIPOT test) given in the safety specifications places a very high voltage between the input power pins of a product and the user circuits and the user touchable surfaces of the product. For the IEC relating to products deriving their power from the 220–240 V power grids, the test voltage is 2500 VAC (or 3750 VDC—the peak equivalent voltage). There are two specifications: terms described in the safety The Si8440 requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. 4.2. Input and Output Characteristics The Si8440 inputs and outputs are standard CMOS drivers/receivers. 4.3. Enable Inputs The receiver output drivers are enabled when the Enable input is high and the drivers remain in a highimpedance state when Enable is low. The Enable input can be used for multiplexing or as a clock sync input. Supply currents remain at their nominal values when Enable is low. The Enable inputs must be tied to a logic level. Creepage—the distance along the insulating surface an arc may travel. Clearance—the distance through the shortest path through air that an arc may travel. Figure 14 illustrates the accepted method of providing the proper creepage distance along the surface. For a 220–240 V application, this distance is 8 mm and the wide body SOIC package must be used. There must be no copper traces within this 8 mm exclusion area, and the surface should have a conformal coating such as solder resist. The digital isolator chip must straddle this exclusion area. Figure 14. Creepage Distance 16 Rev. 0.3 Si8440/1/2 4.4. RF Immunity and Common Mode Transient Immunity The Si8440 family has very high common mode transient immunity while transmitting data. This is typically measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements show no failures up to 30 kV/µs. During a high surge event the output may glitch low for up to 20–30 ns, but the output corrects immediately after the surge event. The Si844x family passes the industrial requirements of CISPR24 for RF immunity of 3 V/m using an unshielded evaluation board. As shown in Figure 15, the isolated ground planes form a parasitic dipole antenna, while Figure 16 shows the RMS common mode voltage versus frequency above which the Si844x becomes susceptible to data corruption. To avoid compromising data, care must be taken to keep RF common-mode voltage below the envelope specified in Figure 16. The PCB should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded. GND1 Isolator GND2 Dipole Antenna Figure 15. Dipole Antenna RMS Voltage (V) 5 4 3 2 1 0 500 1000 1500 2000 Frequency (MHz) Figure 16. RMS Common Mode Voltage vs. Frequency Rev. 0.3 17 Si8440/1/2 4.5. RF Radiated Emissions The Si8440 family uses a RF carrier frequency of approximately 2.1 GHz. This will result in a small amount of radiated emissions at this frequency and its harmonics. The radiation is not from the IC chip but due to a small amount of RF energy driving the isolated ground planes which can act as a dipole antenna. The unshielded Si8440 evaluation board passes FCC requirements. Table 10 shows measured emissions compared to FCC requirements. Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less efficient antenna. Table 10. Radiated Emissions 18 Frequency (GHz) Measured (dBµV/m) FCC Spec (dBµV/m) Compared to Spec (dB) 2.094 70.0 74.0 –4.0 2.168 68.3 74.0 –5.7 4.210 61.9 74.0 –12.1 4.337 60.7 74.0 –13.3 6.315 58.3 74.0 –15.7 6.505 60.7 74.0 –13.3 8.672 45.6 74.0 –28.4 Rev. 0.3 Si8440/1/2 5. Pin Descriptions VDD1 GND1 A1 A2 A3 A4 EN1 GND1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD2 GND2 B1 B2 B3 B4 EN2 GND2 Top View Wide Body SOIC Name SOIC-16 Pin# Type Description VDD1 1 Supply Side 1 power supply. GND1 2 Ground Side 1 ground. A1 3 Digital Input Side 1 digital input. A2 4 Digital Input Side 1 digital input. A3 5 Digital I/O Side 1 digital input or output. A4 6 Digital I/O Side 1 digital input or output. EN1 7 Digital Input GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. EN2 10 Digital Input B4 11 Digital I/O Side 2 digital input or output. B3 12 Digital I/O Side 2 digital input or output. B2 13 Digital Output Side 2 digital output. B1 14 Digital Output Side 2 digital output. GND2 15 Ground Side 2 ground. VDD2 16 Supply Side 2 power supply. Side 1 active high enable. NC on Si8440. Side 2 active high enable. Rev. 0.3 19 Si8440/1/2 6. Ordering Guide Number of Inputs Maximum Data VDD2 Side Rate Ordering Part Number Number of Inputs VDD1 Side Si8440-A-IS 4 0 Si8440-B-IS 4 Si8440-C-IS Temperature Package Type 1 –40 to 125 °C SOIC-16 0 10 –40 to 125 °C SOIC-16 4 0 100 –40 to 125 °C SOIC-16 Si8441-A-IS 3 1 1 –40 to 125 °C SOIC-16 Si8441-B-IS 3 1 10 –40 to 125 °C SOIC-16 Si8441-C-IS 3 1 100 –40 to 125 °C SOIC-16 Si8442-A-IS 2 2 1 –40 to 125 °C SOIC-16 Si8442-B-IS 2 2 10 –40 to 125 °C SOIC-16 Si8442-C-IS 2 2 100 –40 to 125 °C SOIC-16 Note: All packages are Pb-free and RoHS compliant. Moisture sensitivity level is MSL2 with peak reflow temperature of 260 °C according to the JEDEC industry standard classifications, and peak solder temperature. 20 Rev. 0.3 Si8440/1/2 7. Package Outline: Wide Body SOIC Figure 17 illustrates the package details for the Quad-Channel Digital Isolator. Table 14 lists the values for the dimensions shown in the illustration. Figure 17. 16-Pin Wide Body SOIC Table 14. Package Diagram Dimensions Millimeters Symbol Min Max A — 2.65 A1 0.1 0.3 D 10.3 BSC E 10.3 BSC E1 7.5 BSC b 0.31 0.51 c 0.20 0.33 e 1.27 BSC h 0.25 0.75 L 0.4 1.27 θ 0° 7° Rev. 0.3 21 Si8440/1/2 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Added enable high and low typical current specifications to Tables 1, 2, and 3. Added startup time specifications (with note 5) to Tables 1, 2, and 3. Rewrote paragraph 1 in section "4.4. RF Immunity and Common Mode Transient Immunity" on page 17 to reflect 30 kV/µs transient immunity capability. 22 Rev. 0.3 Si8440/1/2 NOTES: Rev. 0.3 23 Si8440/1/2 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 24 Rev. 0.3