E910.48 LIN transceiver with voltage regulator and watchdog Features • • • • • • • • • • • • Brief Functional Description Operating voltage range (VS) 3 to 27V Selectable output voltage: 5V or 3.3V ±2.0% Output current 100mA Reset impulse with two selectable fixed durations (10ms, 65ms) and three selectable threshold levels Programmable Watchdog windows: fixed 35ms and 75ms, variable 3ms...50ms LIN bus interface, LIN Specification 2.1 / 1.3 BUS output slew rate control to reduce EMI BUS input voltage ranges from -24V to +40V Wake-up via BUS Sleep mode current < 20µA typical Over temperature and output current protection BUS pin ESD-protected ≥ 10 kV IEC-61000-4-2 Application • Voltage Regulator for supplying automotive applications with LIN interface. The device E910.48 is a voltage regulator with an integrated LIN-interface for automotive systems. The voltage regulator supplies the µC and generates the reset impulse. The LIN 2.0/2.1 compliant transceiver block of E910.48 interfaces the µC and LIN-bus. The voltage regulator is turned on by LIN bus wakeup request, by EN or by VS poweron. The output voltage is sensed by the pin VDDS and can be selected between 5V or 3.3V by the pin MOD. VDD and VDDS separation allows the use of an external driver transistor for VDD to supply currents >100mA. Using an external resistor between pins VS and VS1 allows to reduce the on chip power dissipation lower than 750mW in the whole operating range The watchdog has a programmable window duration with two fixed or a variable duration. The Reset impulse is influenced by the VDD voltage level, watch dog control and VS voltage level. The reset threshold of VDD has two programmable levels and two reset impulse durations. The reset warning signal provides information about low VS voltage before a reset is generated. Typical Application E910.48 Vbattery 1 VS > 0.1µF RS > 0.1µF R to GND or VDD R to GND or VDD µC VS1 SELRES VDD VDDS Cvdd > 0.1µF MOD to VDD or GND SELWD WU TXD EN RXD WDIN GND RESW BUS RES Voltage Regulator output VDD=5.0v / 3.3v Iload=0…100mA µC LIN bus ELMOS Semiconductor AG Specification 1 / 28 03SP0058E.01 March, 23rd 2007 E910.48 1 Pinout 1.1 Pin Description Pin No. Name Type Description 1 VS S Battery supply 2 VS1 S Battery supply through external resistor RS (*) 3 SELRES AI Reset threshold and timing select 4 SELWD AI Watchdog cycle select, weak pull up 5 TXD DI Transmitted serial data 6 RXD DO Received data output 7 GND S 8 BUS HV I/O LIN-bus bidirectional pin Ground 9 RES DO Reset output, active Low 10 RESW DO Reset warning output, active Low 11 WDIN DI Watch-dog input impulses from µC, pull down 12 EN HVI Enable input, pull down 13 WU DO Wake-up via LIN-bus 14 MOD DI Voltage regulator output mode, pulldown 15 VDDS AI Voltage regulator sense input 16 VDD AO Voltage regulator output D = digital, A = analog, S = Supply, I = Input, O = Output, HV = High Voltage (max. 40V) Note (*): Recommended RS nominal is described in Table 1. 1.2 Package Pinout E910.48 1 VS VDD VS1 VDDS SELRES MOD SELWD WU TXD EN RXD WDIN GND RESW BUS RES Figure 1.2.1: Package SO16W pinout. ELMOS Semiconductor AG Specification 2 / 28 03SP0058E.01 March, 23rd 2007 E910.48 2 Blockdiagram VS VDD Voltage Regulator VS1 VDDS EN Bias_Temp Control EN EN EN MOD WDIN SELRES SELWD Reset Watch Dog EN RXD TXD RESW RES Wake-up WU LIN Transceiver BUS Figure 2.1: Blockdiagram ELMOS Semiconductor AG Specification 3 / 28 03SP0058E.01 March, 23rd 2007 E910.48 3 Operating Conditions 3.1 Absolute Maximum Ratings Operating the device beyond these limits may cause permanent damage. Voltage reference is GND, if not otherwise specified. The current values are positive, if flowing into the circuit. Parameter Condition Symbol Min. Max. Unit Supply Voltage Pin 1, Pin2 continuous VS, VS1 - 0.3 30 V Supply Voltage Pin 1, Pin2 t < 500 ms VS, VS1 - 0.3 40 V LIN Bus Voltage Pin 8 continuous VBUS - 24 30 V t < 500 ms VBUS - 27 40 V VESD,bus 8 kV VESD,VS 4 kV VESD 2 kV VESD,bus 10 kV Vin - 0.3 VDDS+0.3 V LIN Bus Voltage Pin 8 ESD protection at Bus pin ESD protection at VS pin 1) 1) ESD protection at other pins 1) ESD protection at Bus pin, IEC 61000-4-2 CBUS=220pF Input Voltage Pins 3,4,6,9-11,13,14 Input Voltage Pin 5 continuous Vin -0.3 18 V Voltage at Pin 15 continuous VDDS -0.3 5.2 V Voltage at Pin 16 continuous VDD -0.3 7 V Input Voltage Pin 12 Vin -0.3 24 V Current of Pin 1, 2 2) Ipmax -100 300 mA Current of Pins 16 2) Ipmax -300 100 mA Ipmax -100 100 mA Ipmax -25 25 mA Current of Pins 7,8 2) Current of Pins 3, 4, 5, 6, 9-15 Power Dissipation 3) Power Dissipation 3) TA =<85ºC W dis_pack 620 mW TA =<125ºC W dis_pack 170 mW RTja 89 K/W Thermal Resistance Junction to Ambient Junction Temperature Tj -40 150 °C Operating Ambient Temperature TOP -40 125 °C Storage Temperature TSTG - 55 150 °C 1) AEC-Q 100 HBM chiplevel test 2) Withhin the allowed voltage range 3) To avoid thermal shutdown ELMOS Semiconductor AG Specification 4 / 28 03SP0058E.01 March, 23rd 2007 E910.48 3.2 Recommended Operating Conditions Parameters are guaranteed within the range of operating conditions unless otherwise specified. Parameter Symbol Min. Max. Unit VS 7 27 V LIN-bus voltage, Pin 8 VBUS -18 18 V Ambient Temperature Ta - 40 125 °C VTXD -0.3 5.2 V Tj -40 140 °C Supply Voltage Condition 1) Input Voltage Pin 5 Junction Temperature continuous 2) 1) LIN parameters are specified up to 18V 2) To avoid thermal shutdown ELMOS Semiconductor AG Specification 5 / 28 03SP0058E.01 March, 23rd 2007 E910.48 4 Detailed Electrical Specification All of the following parameters are valid for an ambient operating temperature range of -40°C up to 125°C (with respect to absolute maximum thermal power dissipation) and a supply voltage range of 6.5V < VS < 27V, unless otherwise specified. Voltage reference is GND, if not otherwise specified. The current values are positive, if flowing into the circuit. 4.1 Voltage Regulator No. Pin Parameter Condition Symbol Min. Typ. Max. Unit VS 6.5 12 27 V VSmin 5.9 4.5 6.5 5.5 V Vsmin 5.3 3.8 DC parameters 1 2 3 4 5 EN=H, VDD in range, IVDD=0...-100mA VS Supply voltage range VS EN=H, RVS1=68Ω, VDD in range, Supply voltage operation minimum IVDD=0...-100mA (Figure 5.3.1) MOD=H MOD=L VS VDD, MOD VDD Supply voltage operation minimum (Figure 5.3.1) 2) EN=H, RVS1=0Ω IVDD=0...-50mA MOD=H MOD=L EN=H, VS>Vsmin IVDD=0...-100mA MOD=H MOD=L Output voltage range Output voltage drop of regulator EN=H, 4.0V<VS<Vsmin, MOD=H, RL=50Ω MOD=L, RL=33Ω 6 VDD Output current EN=H, MOD=L/H 7 VDD Output current limitation EN=H 8 VS,VS1 9 VS,VS1 10 VDD Battery supply current in Sleep mode, I(pin VS)+I(pinVS1) Quiescent current, I(pin VS)+I(pinVS1) Load regulation voltage ELMOS Semiconductor AG VDD 4.90 3.23 5.00 3.30 5.10 3.37 V 0.9 1.1 1.5 2.1 V 0 mA -105 mA Vddtr IVDD -100 IVDD_lim -300 -190 EN=L, WU=L VS=12V, Tj=25°C EN=L, WU=L VS<18V Tj < 125°C V 20 IVS_sl µA 50 µA 2 mA 50 mV EN=L/H, WU=H, IVDD=0mA, IVS_q IVDD=0...100mA VDD_lr 0.90 TXD=H Specification 6 / 28 03SP0058E.01 March, 23rd 2007 E910.48 No. Pin Parameter Condition Symbol Min. Typ. Max. Unit AC parameters 13 VDD Voltage regulator enabled and stable after EN goes to H (Figure 5.5.1) 1) VS=12V, IVDD=100mA CVDD=0.1µF 14 VDD Voltage regulator recovery time after short-circuit 2) VS=12V, IVDD=100mA, CVDD=0.1µF 15 VDD Power-supply rejection ratio EN=H, CVDD=0.1uF f=100 / 1000 Hz Rs=0Ω 2) 1) For higher capacitor values the turn on time is determined by 2) Not production tested ELMOS Semiconductor AG Specification t on = 7 / 28 tvr_en 20 µs tvr_rec 30 µs PSRR 60 dB C VDD∗VDD I VDD _lim 03SP0058E.01 March, 23rd 2007 E910.48 4.2 Reset No. Pin Parameter Condition Symbol Min. Typ. Max. Unit 0.3 0.3 V -200 µA 0.25 VDD DC parameters 1 RES, RESW Output low voltage Rload = 5kΩ to VDD VOLR VOLRW 2 RES, RESW Pull up current Vres,Vresw = 0V IRPU IRWPU -600 -375 3 SELRES input low voltage VIL,SELRES 4 SELRES input high voltage VIH,SELRES 0.75 ISRPU ISRPD -300 100 -200 200 -100 300 Vth1 Vth2 4.20 3.00 4.45 3.15 4.60 3.30 V Vth1 2.80 2.94 3.07 V Vth,VS 2.80 4.00 V EN or WU=H Vthw 7.0 V EN or WU=H Vwhys 200 mV Reset delay Figure 5.3.1 trr 20 30 µs Reset pulse duration (Figure 5.3.1) Pin resistor connected to VDD or GND Rselres=0kΩ Rselres=50kΩ 9 65 15 90 ms Output current (interrogate pin mode) VDD > 3V Pin connected to GND VDD, CSELRES,ext<200 pF RES, VDDS Reset threshold (Figure 5.3.1) MOD=H Pin SELRES connected to VDD GND RES, VDDS Reset threshold 1) (Figure 5.3.1) 5 SELRES 6 7 8 1) MOD=L Pin SELRES connected to VDD or GND RES, VS Reset threshold VS 1) 9 RESW, VS Reset warning threshold 10 RESW, VS Reset warning threshold hysteresis Figure 5.3.1 VDD µA AC parameters 11 12 RES, RESW RES trd 5 40 Reset is generated by supervision of VDDS and VS. Voltage going below one of the specified thresholds generates reset. 1) ELMOS Semiconductor AG Specification 8 / 28 03SP0058E.01 March, 23rd 2007 E910.48 4.3 Logic I/O No. Pin Parameter Condition Symbol Min. Typ. Max. Unit 0.4 V DC parameters 1 MOD Input low voltage VILMOD 2 MOD Input high voltage VIHMOD 2.4 3 MOD Pull down current IMODPD 70 4 EN Input low voltage VILEN 5 EN Input high voltage VIHEN 2.0 6 EN Pull down current UEN = VDD IENPD 70 Output low voltage VDD=5.0V: ILOAD=+1mA VDD=3.3V: ILOAD=+0.7mA VOLWU Output high voltage VDD=5.0V: ILOAD=-1mA VDD=3.3V: ILOAD=-0.7mA VOHWU 7 8 WU WU UMOD = VDD V 150 320 µA 0.8 V V 150 VDD-0.3 320 µA 0.3 V V AC parameters 9 1) EN Enable input debouncing 1) ten_m 2.0 µs Not production tested ELMOS Semiconductor AG Specification 9 / 28 03SP0058E.01 March, 23rd 2007 E910.48 4.4 Watch-Dog No. Pin Parameter Condition Symbol Min. Typ. Max. Unit 0.8 V DC parameters 1 WDIN Watch-dog input low voltage VILWDIN 2 WDIN Watch-dog input high voltage VIHWDIN 2.0 3 WDIN Watch-dog pull down current IWDINPD 70 4 SELWD Watch-dog select input low voltage VILSWD 5 SELWD Watch-dog select input high voltage VIHSWD 2.4 6 SELWD Watch-dog select pull up current ISWDPU -80 UWDIN = VDD USELWD = GND V 130 250 µA 0.3 V V -60 -40 µA 3.0 µs AC parameters 7 8 WDIN WDIN Watch-dog input debouncing1 Watch-dog cycle time tWD_M fixed cycletime SELWD=H SELWD=L variable cycletime e.g. Rselwd=619kΩ Rselwd=40.2kΩ tWDC Condition Symbol 50 20 75 35 100 50 ms 34 2.7 43 3.3 53 3.9 Min. Typ. Max. 4.5 Temperature protection. No. Pin 1) Parameter Unit 1 Thermal protect temperature 1) EN=H TOFF 165 ºC 2 Thermal protect temperature hysteresis EN=H THYS 10 ºC 1) Parameter is not production tested, functionality of temperature shutdown is tested in production. ELMOS Semiconductor AG Specification 10 / 28 03SP0058E.01 March, 23rd 2007 E910.48 4.6 LIN Transceiver All parameter are relating to the diagrams in this function description. The transceiver parameters are compliant to LIN 1.3 and 2.0 specification. Figure 4.6.1: LIN system application signal definition No. Pin Parameter Condition Symbol Min. Typ. Max. Unit DC parameters 1 TxD Input low voltage Vtxdl 2 TxD Input high voltage Vtxdh 2.0 3 TxD Pull down current Itxdpd 25 50 100 µA 4 TxD Pull up current Itxdpu -500 -300 -330 -230 -180 -150 µA 0.3 V EN=L, VTXD = VDD 0.8 5 RxD Output low voltage VDD=5.0V: ILOAD=+1mA VDD=3.3V: ILOAD=+0.7mA Vrxdol 6 RxD Output high voltage VDD=5.0V: ILOAD=-1mA VDD=3.3V: ILOAD=-0.7mA Vrxdoh VDD-0.3 7 BUS Recessive output voltage EN=H, TXD=H Vrec VS-1.0 Dominant output voltage EN=H, TXD=L, VS=7.3 V RL=0.5kΩ to VS EN=H, TXD=L, VS=18.0 V RL=0.5kΩ to VS 9 10 BUS BUS BUS V Vdom 1.2 V Vdom 2.0 V EN=H Vth_dom Receiver threshold of the recessive edge EN=H Vth_rec Specification 11 / 28 V VS Receiver threshold of the dominant edge ELMOS Semiconductor AG V EN=H, VTXD = GND MOD=H MOD=L 8 V VS-0.4 0.40 03SP0058E.01 VS 0.60 VS March, 23rd 2007 E910.48 No. Pin 11 BUS 12 13 BUS BUS Parameter Condition BUS center voltage (Vth_dom +Vth_rec)/2 Symbol Min. Vbus_cnt 0.475 Receiver hysteresis (Vth_rec-Vth_dom) EN=H/L Receiver threshold of the dominant edge in Sleep mode EN=L Vth_doms 3.9 Typ. Vhys Max. Unit 0.525 VS 0.175 VS 5.5 V 14 BUS Pulldown current limitation Vbus>2.5V Ibus_lim 40 85 200 mA 15 BUS Pull up resistance EN=H Rslave 20 30 60 kΩ 16 BUS Leakage current flowing into pin 20 µA 1 mA 100 µA EN=L, 7V <VS< 18V 7V <Vbus< 18V Vbus >= VS 17 BUS Leakage current, ground disconnected (GND device=VS) VS=0V, -12V <Vbus<0V 18 BUS Leakage current, supply disconnected VS=0V, 0V<Vbus<18V 19 BUS Clamping voltage VS=0V Ibus=1mA Ibus_pas_rec Ibus_no_ gnd -1 Ibus Vclamp 40 50 65 V |dV/dt| 1.0 1.8 3.0 V/µs |dV/dt| 0.5 1.8 3.0 V/µs -5.0 +5.0 µs 4 µs 2 µs AC parameters 20 CL=0.02...10nF RL=0.5...1kΩ 1µs < τBUS < 5µs VS=18V BUS Output slew rate 21 BUS Output slew rate CL=0.02...10nF RL=0.5...1kΩ 1µs < τBUS < 5µs VS=7.3V 22 BUS Symmetry of rising and falling edge VS=18V tSYM = tfall-trise tSYM 23 TXD, BUS Transmit propagation delay Figure 5.6.1 ttrans_pd 24 TXD, BUS Transmit propagation delay symmetry Figure 5.6.1 ttrans_pdf - ttrans_pdr ttrans_sym 25 BUS, RXD Receive propagation delay Figure 5.6.1 trec_pd 26 BUS, RXD Receive propagation delay symmetry Figure 5.6.1 trec_pdf - trec_pdr 27 BUS, RXD Input bus impulse debounce time 28 WU, BUS Dominant time for wake-up via BUS 1) trec_sym -2 6 -2 µs 2 µs 2 µs 150 µs 1) Figure 5.6.3 tbus_deb Figure 5.5.1 EN=0 tWU 40 75 Not production tested ELMOS Semiconductor AG Specification 12 / 28 03SP0058E.01 March, 23rd 2007 E910.48 Additional LIN 2.0 / 2.1 duty cycle parameters Nr. Symbol Min. D1 (Duty cycle 1)2) 3) 7.0V ≤ VS ≤ 18V; Tbit=50µs THREC(MAX)= 0.744 x VS THDOM(MAX)=0.581 x VS D1 = tBUS,REC(MIN) / (2 x Tbit) D1 0.396 D2 (Duty cycle 2)2) 3) 7.6V ≤ VS ≤ 18V; Tbit=50µs THREC(MIN)= 0.422 x VS THDOM(MIN)=0.284 x VS D2 = tBUS,REC(MAX) / (2 x Tbit) D2 31 D3 (Duty cycle 3)2) 3) 7.0V ≤ VS ≤ 18V; Tbit=96µs THREC(MAX)= 0.778 x VS THDOM(MAX)=0.616 x VS D3 = tBUS,REC(MIN) / (2 x Tbit) D3 32 D4 (Duty cycle 4) 7.6V ≤ VS ≤ 18V; Tbit=96µs THREC(MIN)= 0.389 x VS THDOM(MIN)=0.251 x VS D4 = tBUS,REC(MAX) / (2 x Tbit) D4 29 30 Parameter Bedingung 2) 3) Typ. 0.417 see figure 5.6.2 valid for bus load combinations of RBUS / CBUS = 1kΩ / 1nF ; 660Ω / 6.8nF ; 500Ω / 10nF Specification 13 / 28 03SP0058E.01 - - 0.590 3) Einheit - 0.581 2) ELMOS Semiconductor AG Max. - March, 23rd 2007 E910.48 5 Functional Description 5.1 General description The device E910.48 is a voltage regulator with an integrated LIN-interface for automotive systems. The voltage regulator supplies the µC and generates the reset impulse. The internal programmable watchdog supervises the microcontroller and will generate a reset condition if the µC does not trigger the watchdog properly. The voltage regulator is switched on by LIN-bus wake up request or at power on at pin VS or when EN is active (high). The output voltage is sensed by the pin VDDS. By using VDDS to sense the output voltage and adding an external driver transistor (bipolar recommended due to abs max ratings) at VDD, output currents >100mA can be supplied. (Consider an increase in minimum supply voltage at VS.) Using an external resistor between pins VS and VS1 allows to reduce the power dissipation on chip below 750mW at all operating voltages VS=3...27V. With the input MOD the output voltage VDD can be selected between 5V or 3.3V. The LIN transceiver block of E910.48 provides the data exchange between µC and LIN-bus. The LIN transceiver is conform to the LIN physical layer specification 1.3 and 2.0/2.1. The reset output signal is triggered by the VDD voltage level and by watchdog control with a programmable reset delay. Two fixed values for the VDD reset threshold are available. A timing diagram including watchdog and reset behaviour is provided in Figure 5.5.1. ELMOS Semiconductor AG Specification 14 / 28 03SP0058E.01 March, 23rd 2007 E910.48 5.2 Operating modes The device E910.48 provides three operation modes: Sleep mode (low power), Standby mode(transceiver deactivated) and Active mode. Active Mode VS < VSPOR or EN = 1 VR = on TXD = enabled after one WDIN pulse RXD = enabled T > TOFF 1) VS > VSPOR and T < TOFF and EN = high EN=1 EN=1 Stby Mode EN=0 EN VR TXD RXD = = = = 0 on disabled enabled Sleep Mode EN VR TXD RXD = = = = bus-activity 0 off disabled disabled VS > VSPOR and T < TOFF and EN = low VS < VSPOR or T > TOFF 1) OFF 1) over temperature shutoff. In case of an over temperature shutoff the circuit comes back to the system start automatically after cooling down Figure 5.2.1: Operation modes 5.3 Voltage Regulator The circuit turns on automatically after the battery voltage (VS) is greater than typical 3V (Figure 5.3.1). After this, it is necessary to set EN to a voltage greater than VIH,EN before it is possible to use the LIN-transceiver path or to set circuit into sleep mode. The Voltage regulator provides the output voltage VDD=5.0V or 3.3V (MOD=H/L) with the maximum output current of IVDD=100mA. Short current protection at Pin VDD is activated if the load current reaches typical 190mA (Figure 5.3.2). If due to VDD drop the EN input signal fails to reach the high threshold the circuit goes into sleep mode. The over voltage protection is activated, if the output voltage is about 400mV higher than the specified values (5.0V and 3.3V) and reduces the output voltage to nominal value. ELMOS Semiconductor AG Specification 15 / 28 03SP0058E.01 March, 23rd 2007 E910.48 Moreover the device provides three options of thermal power management: Variant 1 The Pins VS and VS1 are connected directly. In this case the whole power dissipation is located on chip. The maximum continuous load current depends on the ambient temperature (see absolute maximum ratings). Peak currents are limited by current limitation of typical 190mA. Variant 2 The pin VS1 is connected to the battery (VS) through resistor a resistor named RS. This resistor provides a pullup at VS1 to VS. Internal circuitry limits the drop across RS and keeps VS1 sufficiently high to generate VDD from VS1. Advantage of this concept is, that the onchip power dissipation for high load current of up to 100mA can be reduced by shifting it to RS. Typical values for RS are shown in Table 1 . More detailed examples for power dissipation sharing between external RS and the device is shown in Figure 5.3.3. The basical behaviour of the voltage regulator under output overloading / current limitation is shown in (Figure 5.3.2). Voltage Regulator load current IVDD, mA Nominal and power on resistor RS, VDD = 5v or 3.3v 0…50 mA 0…100 mA 200 Ω, Power dissipation in the package 0.5W 130 Ω, 1W Comments <0.3W See Figure 5.3.3 <0.6W f load current IVDD <=50mA, a power dissipation on a chip is less 0.8W and resistor RS may be 0 ohm Table 1. recommended value of the external resistor RS Variant 3 The Pins VS and VS1 are connected as in Variant 1 or Variant 2 and the the pin VDD provides the current for an external driver transistor. The Pin VDDS is used to sense the output voltage and provides a base/gate voltage for the driver transistor at VDD. The maximum output current and the voltage drop depends on the external driver transistor choosen. ELMOS Semiconductor AG Specification 16 / 28 03SP0058E.01 March, 23rd 2007 E910.48 8 Voltage, V 7 Vthw 6 Vsmin 5 VDD VS Reset warning threshold +-2% 4 3 2 VDD Reset threshold Vth Vddtr 3v Vth_v s 1 t 0 VR off Vdd tracks Vsup Vdd in range Vdd tracks Vs trd trr RES trr trr RESW Figure 5.3.1 Output voltage VDD and Reset on Power-ON (mode 5V, Rload=33Ohm) Rload time Ivdd_lim Ivdd 100mA time VDD 5V Vth trr RES trd time Figure 5.3.2 Output voltage VDD and reset on over load situation (mode 5V) ELMOS Semiconductor AG Specification 17 / 28 03SP0058E.01 March, 23rd 2007 E910.48 Voltage Regulator. Power dissipation vs. RS nominal VCC=5.0v, Ivcc=150mA Voltage Regulator. Power dissipation vs. RS nominal VCC=3.3v, Ivcc=150mA 3 3 W_BAT W_BAT 2.5 2.5 W_chip_RS=0 W_chip_RS=0 W_chip_RS=60 W_chip_RS=60 W_chip_RS=70 2 W_chip_RS=70 Power, W Power, W 2 W_chip_RS=80 1.5 W_chip_RS=80 1.5 1 1 0.5 0.5 0 0 4 6 8 10 12 Supply voltage, V 14 16 18 4 20 6 10 12 14 16 18 20 Supply voltage, V Voltage Regulator. Power dissipation vs. RS nominal VCC=5.0v, Ivcc=50mA Votage Regulator. Power dissipation vs. RS nominal VCC=3.3v, Ivcc=50mA 1 1 W_BAT W_BAT W_chip_RS=0 0.8 0.8 W_chip_RS=60 W_chip_RS=0 W_chip_RS=60 W_chip_RS=120 W_chip_RS=200 0.6 Power, W P ower, W 8 0.4 W_chip_RS=120 0.6 W_chip_RS=200 0.4 0.2 0.2 0 0 4 6 8 10 12 14 Supply voltage, V 16 18 20 4 6 8 10 12 14 16 18 20 Supply voltage, V Figure 5.3.3 Battery power and power dissipation on chip vs. RS ( if RS value is higher, curve is shifted to right ) ELMOS Semiconductor AG Specification 18 / 28 03SP0058E.01 March, 23rd 2007 E910.48 5.4 Reset programming The E910.48 provides a programmable power-on/-off reset and an additional reset warning output. The reset threshold and the reset duration can be programmed by the pin SELRES in four different combinations. The pin SELRES can be tied directly to GND or VDD or by a resistor Rselres. With SELRES tied to GND the low reset threshold is selected or by tying SELRES to VDD the high reset threshold is active. By connecting SELRES directly to VDD or GND the reset delay time trd is 10ms. If SELRES is tied to VDD or GND by a resistor of typ. 56kOhm, a reset time of 65ms is selected. The SELRES evaluation starts after the voltage regulator is switched on and output voltage has reached the reset threshold. The SELRES evaluation needs typ. 100us. The reset thresholds are depending on the selected mode and are shown in Table 2: programming of reset mode. In 3.3V mode the threshold of typ. 2.94V is selected regardless of the SELRES programming. RESET threshold, Vth Reset duration, trd VDD directly 4,45 V 10 ms VDD by Rselres typ. 56kΩ 4,45 V 65 ms GND directly 3,15 V 10 ms 1 GND by Rselres typ. 56kΩ 3,15 V 65 ms 4 VDD directly 2.94 V 10 ms VDD by Rselres typ. 56kΩ 2.94 V 65 ms GND directly 2.94 V 10 ms GND by Rselres typ. 56kΩ 2.94 V 65 ms Progr. state Pin MOD connected to 4 3 VDD 2 (VDD output =5V) 3 GND 2 (VDD output =3.3V) 1 Pin SELRES connected to Table 2: programming of reset mode The internal VS reset occurs at typical VS=2.5V. This causes the voltage regulator to switch off. An additional reset warning is provided on pin RESW. RESW becomes low when supply voltage VS is lower than typical 7V. The reset warning allows the system to avoid malfunction or data loss in case of low VS voltage. ELMOS Semiconductor AG Specification 19 / 28 03SP0058E.01 March, 23rd 2007 E910.48 5.5 Watchdog The integrated watchdog allows supervision of the microcontrollers operation. Periodically It has to trigger the E910.48 on pin WDIN withhin a defined response time Twdc by a high-pulse with a minimal width of 2µs. If the watchdog is not triggered correctly the E910.48 generates a reset at the output RES. The length of the watchdog timeout can be adjusted by pin SELWD. By connecting this pin to GND or VDD one of two fixed timings is selected. If the pin WD is connected to GND by an external resistor Rselwd the watchdog cycle time twdc can be varied between typical 3.3ms and 43ms. For details see Table 3. SELWD Watchdog cycle time, connected... twdc to VDD directly to GND by Rselwd = 40k...619k to GND directly Comment 75 ms Fixed duration 3.3 ms ... 43 ms Duration is a function of Rselwd ( typ.): twdc [ms] = 70e-6 * Rselwd +0.5 35 ms Fixed duration Table 3: watchdog programming The evaluation of the input WDIN pulses is beginning after reset time trd has expired. If the WDIN pulse is provided by the microcontroller during the watchdog cycle, no reset will be generated and a new cycle is started. On the other hand the absence of the WDIN impulse generates an reset to the microcontroller, see Figure 5.5.1. ELMOS Semiconductor AG Specification 20 / 28 03SP0058E.01 March, 23rd 2007 ELMOS Semiconductor AG Specification 21 / 28 03SP0058E.01 WU BUS WDIN RES internal CLK VDD internal ENVR EN POR intern al VS Opening the WD-analyze windows, twd t rd t < t wdc VDD launch by power ON 5V or 3.3V t=twdc t rd t rd VDD launch by EN Data transmit enable no new reset, if t< t rr tvr_en rd Wake-up request t wu t rd VDD launch by bus wakeup Data transmit enable t E910.48 Figure 5.5.1: Reset and Watch dog function March, 23rd 2007 E910.48 5.6 LIN transceiver The integrated LIN transceiver is compliant to LIN specification V1.3 and V2.0/2.1. Transmitter Path To activate the transmitter part, the microcontroller has to pull up the EN pin to high state and has to apply at least one WDIN pulse to trigger the integrated watchdog. Low level on the TXD pin activates the open-collector transistor at the bus pin. In order to minimise the EMC radiation on the bus, the rise and fall time of the transmit pulse on the bus pin is generated by a slew rate controller. The maximum rising slewrate is limited, but also depends on the BUS timeconstant τ =RBUS*CBUS, because the output driver switches off and the system pullup resistors of all slaves and the master pulls the LIN-line to recessive state. (see Figure 5.6.1) TXD tTrans_pdf VS tTrans_pdr t60/40 t t40/60 VREC Vth,rec = 60% VS VSWING Vth,dom = 40% VS VDOM RXD trec_pdr trec_pdf t t dV/dt, fall = 0.2*VSWING / t60/40 dV/dt, rise = 0.2*VSWING / t40/60 Figure 5.6.1: Bus driver slew rate Symmetry of rising and falling edge in figure 5.6.1 is defined as TSYM = TFALL-TRISE (with TFALL= T60/40 / 0.2 and TRISE= T40/60 / 0.2 ). ELMOS Semiconductor AG Specification 22 / 28 03SP0058E.01 March, 23rd 2007 E910.48 Figure 5.6.2 LIN2.x Parameter Definitions Receiver Path The bus voltage is compared against half the VS voltage including hysteresis. A deglitched bus signal is digitally provided at RXD if VDD is enabled and EN is set to high. (see Figure 5.6.1) Wake up If the device is in sleep mode, it can recognize an wake up request on LIN bus to activate the internal voltage regulator. A wakeup request is detected by dominant bus state for at least 150us after a falling edge. Wakeup enables the voltage regulator and the uC has to enable the receiver by setting EN to high state. To activate the transmiter least one WDIN pulse has to be applied. ELMOS Semiconductor AG Specification 23 / 28 03SP0058E.01 March, 23rd 2007 E910.48 VREC VS are ignored, if t < tBUS_DEB BUS VTH_DOM VDOM Ground S tWU wake-up event WU VTHW VCC RES RESW tRD Sleep mode Standby mode Figure 5.6.3: Wake-up request via Bus In order to reduce the current consumption in sleep mode a fixed receiver threshold voltage of typical 4.8V is implemented. ELMOS Semiconductor AG Specification 24 / 28 03SP0058E.01 March, 23rd 2007 E910.48 6 Package 6.1 Marking Top Side ELMOS E 910.48 A XXX#LYWW*@ where E/M/T 000.01 Volume Production / Prototype / Test Circuit ELMOS Project Number A Version # Assembler Code YWW Year and Week of Fabrication * Mask Revision Number @ ELMOS internal Marking L Production Location Bottom Side No Marking 6.2 Package Dimensions ELMOS packages meet the requirements of the latest JEDEC outline specification. All JEDEC outline specifications can be free downloaded from http://www.jedec.org or please contact your local ELMOSKeyacount-Manager. ELMOS Semiconductor AG Specification 25 / 28 03SP0058E.01 March, 23rd 2007 E910.48 7 General 7.1 Other Documents LIN Physical Layer Specification (Revision 1.3) LIN Physical Layer Specification (Revision 2.0) LIN Physical Layer Specification (Revision 2.1) (see also www.lin-subbus.org) 8 Record of Revisions Chapter Rev. Change and Reason for Change Date Released ELMOS 01 First released specification version ELMOS Semiconductor AG Specification March,23 2007 rd 26 / 28 03SP0058E.01 ASu March, 23rd 2007 E910.48 Table of Contents 1 Pinout................................................................................................................................................................2 1.1 Pin Description.........................................................................................................................................2 1.2 Package Pinout........................................................................................................................................2 2 Blockdiagram....................................................................................................................................................3 3 Operating Conditions........................................................................................................................................4 3.1 Absolute Maximum Ratings.....................................................................................................................4 3.2 Recommended Operating Conditions......................................................................................................5 4 Detailed Electrical Specification.......................................................................................................................6 4.1 Voltage Regulator.....................................................................................................................................6 4.2 Reset........................................................................................................................................................8 4.3 Logic I/O...................................................................................................................................................9 4.4 Watch-Dog.............................................................................................................................................10 4.5 Temperature protection..........................................................................................................................10 4.6 LIN Transceiver......................................................................................................................................11 5 Functional Description....................................................................................................................................14 5.1 General description................................................................................................................................14 5.2 Operating modes....................................................................................................................................15 5.3 Voltage Regulator...................................................................................................................................15 5.4 Reset programming................................................................................................................................19 5.5 Watchdog...............................................................................................................................................20 5.6 LIN transceiver.......................................................................................................................................22 6 Package........................................................................................................................................................25 6.1 Marking.................................................................................................................................................25 6.2 Package Dimensions...........................................................................................................................25 7 General.........................................................................................................................................................26 7.1 Other Documents.................................................................................................................................26 8 Record of Revisions.....................................................................................................................................26 ELMOS Semiconductor AG Specification 27 / 28 03SP0058E.01 March, 23rd 2007 E910.48 WARNING – Life Support Applications Policy ELMOS Semiconductor AG is continually working to improve the quality and reliability of its products. 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Copyright © 2007 ELMOS Reproduction, in part or whole, without the prior written consent of ELMOS, is prohibited. ELMOS Semiconductor AG Specification 28 / 28 03SP0058E.01 March, 23rd 2007