LIN-Transceiver LDO TLE 6286 Target Data Sheet 1 Overview 1.1 Features • • • • • • • • • • • • • • • • • • Single-wire transceiver, suitable for LIN protocol Transmission rate up to 20 kBaud Compatible to LIN specification Compatible to ISO 9141 functions Very low current consumption in sleep mode Control output for voltage regulator Short circuit proof to ground and battery Overtemperature protection Output voltage tolerance ≤ ± 2 % 200 mA output current capability Low-drop voltage Very low standby current consumption Overtemperature protection Reverse polarity protection Short-circuit proof Watchdog Wide temperature range Suitable for use in automotive electronics P-DSO-16-4 Type Ordering Code Package TLE 6286 G on request P-DSO-16-4 1.2 Description The TLE 6286 is a single-wire transceiver with a LDO. It is chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6286 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. In order to reduce the current consumption the TLE 6286 offers a sleep operation mode. In this mode a voltage regulator can be controlled in order to minimize the current consumption of the whole application. The on-chip voltage regulator is designed for this Version 1.02 1 2001-10-15 Target Data TLE 6286 application but it is also possible to use an external voltage regulator. A wake-up caused by a message on the bus enables the voltage regulator and sets the RxD output low until the device is switched to normal operation mode. The IC is based on the Smart Power Technology SPT® which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit. The TLE 6286 is designed to withstand the severe conditions of automotive applications. Version 1.02 2 2001-10-15 Target Data TLE 6286 1.3 Pin Configuration (top view) GND 1 16 GND RD 2 15 RO WD 3 14 INHI VCC 4 13 VBAT INHO 5 12 BUS RxD 6 11 TxD ENLIN 7 10 VS GND 8 9 GND P-DSO-16-4 GND 1 RD 2 WD 3 VCC Leadframe 16 GND 15 RO 14 INHI 4 13 VBAT INHO 5 12 BUS RxD 6 11 TxD ENLIN 7 10 VS GND 8 9 Chip: Voltage Regulator Chip: Transceiver GND P-DSO-16-4 Figure 1 Version 1.02 Pinout 3 2001-10-15 Target Data TLE 6286 1.4 Pin Definitions and Functions: Pin No. Symbol Function 1,8,9,16 GND Ground; place to cooling tabs to improve thermal behavior 2 RD Reset delay; connected to ground with capacitor 3 WD Window Watchdog; rising-edge triggered, for monitoring a microcontroller 4 VCC 5V Output; connected to GND with 22µF capacitor, ESC<3Ω 5 INHO Inhibit LIN Output; to control a voltage regulator 6 RxD Receive Data Output; internal 30kΩ pull up to Vs, LOW in dominat state 7 ENLIN Enable LIN Input; integrated 30kΩ pull down, transceiver in normal operation mode when HIGH 10 VS 5V Supply Input; VCC input to supply the LIN transceiver 11 TxD Transmit Data Input; internal 30kΩ pull up to Vs, LOW in dominant state 12 BUS LIN BUS Output/Input; internal 30kΩ pull up to Vs, LOW in dominant state 13 VBAT Battery Supply Input; a reverse current protection diode is required, block GND with 100nF ceramic capacitor and 22µF capacitor 14 INHI Inhibit Voltage Regulator Input; TTL compatible, low active input 15 RO Reset Output; open collector output connected to the output via a resistor of 30kΩ Version 1.02 4 2001-10-15 Target Data TLE 6286 1.5 Functional Block Diagram VBAT 13 30 kΩ Bus Mode Control Output Stage 5 INHO 10 VS 7 ENLIN 11 TxD 6 RxD 5 GND 4 VCC 2 RD 15 RO Driver 30 kΩ 12 Temp.Protection Receiver TLE 6259 G WD 3 Saturation Control and Protection Circuit Temperature Sensor VBAT Watchdog 13 Control Amplifier Buffer Reset Generator Bandgap Reference Adjustment TLE 4263 G Figure 2 Version 1.02 14 1 INHI GND Block Diagram 5 2001-10-15 Target Data TLE 6286 2 Circuit Description The TLE 6286 is a single-wire transceiver combined with a LDO. It is a chip by chip integrated circuit in a P-DSO-16-4 package. It works as an interface between the protocol controller and the physical bus. The TLE 6286 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. The on-chip voltage regulator with watchdog is designed for sleep mode applications but it is also possible to use an external voltage regulator. Start Up Power Up Normal Mode ENLIN INHO VCC ON high high ENLIN ENLIN high low Stand-By ENLIN (VCC high ON) ENLIN INHO RxD VCC low high low1) ON high3) Sleep Mode Wake Up t > tWAKE ENLIN INHO VCC low floating OFF2) 1) 2) 3) Figure 3 2.1 after wake-up via bus ON when INHO not connected to INHI after start up Operation Mode State Diagram Operation Modes In order to reduce the current consumption the TLE 6286 offers a sleep operation mode. This mode is selected by switching the enable input EN low (see figure 3, state diagram). In the sleep mode a voltage regulator can be controlled via the INH output in order to minimize the current consumption of the whole application. A wake-up caused by a message on the communication bus automatically enables the voltage regulator by switching the INH output high. In parallel the wake-up is indicated by setting the RxD output low. When entering the normal mode this wake-up flag is reset and the RxD output is released to transmit the bus data. Version 1.02 6 2001-10-15 Target Data TLE 6286 In case the voltage regulator control input is not connected to INH output or the microcontroller is active respectively, the TLE6286 can be set in normal operation mode without a wake-up via the communication bus. 2.2 LIN Transceiver The LIN Transceiver has already a pull up resistor of 30kΩ as termination implemented. There is also a diode in this path, to protect the circuit from feedback of voltages from the bus line to the power supply. To configure the TLE 6286 as a master node, an additional external termination resistor of 1kΩ is required. To avoid reverse currents from the bus line into the battery supply line in case of an unpowered node, it is also recommended to place a diode in series to the external pull up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1nF in the master node (see figure 6, application circuit). An capacitor of 10µF at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. 2.3 Voltage Regulator The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any over-saturation of the power element. If the externally scaled down output voltage at the reset threshold input drops below 1.35 V, the external reset delay capacitor is discharged by the reset generator. When the voltage of the capacitor reaches the lower threshold VDRL, a reset signal occurs at the reset output and is held until the upper threshold VDU is exceeded. If the reset threshold input is connected to GND, reset is triggered at an output voltage of typ. 4.65 V. A connected microcontroller will be monitored through the watchdog logic. In case of missing pulses at pin W, the reset output is set to low. The pulse sequence time can be set in a wide range with the reset delay capacitor. The IC can be switched at the TTL-compatible, low-active inhibit input. The IC also incorporates a number of internal circuits for protection against overload, overtemperature, reverse polarity 2.4 Input Capacitor The input capacitor CI is necessary for compensation of line influences. Using a resistor of approx. 1 Ω in series with CI, the oscillating circuit consisting of input inductivity and input capacitance can be damped. The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values ≥ 22 µF and an ESR of ≤ 3 Ω within the operating temperature range. For small tolerances of the reset delay the spread of the capacitance of the delay capacitor and its temperature coefficient should be noted. Version 1.02 7 2001-10-15 Target Data TLE 6286 2.5 Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows: CD = (trd × ID,ch)/∆V Definitions:CD = delay capacitor trd = reset delay time ID,ch = charge current, typical 60 µA ∆V = VDU, typical 1.70 V VDU = upper delay switching threshold at CD for reset delay time 2.6 Watchdog Timing The frequency of the watchdog pulses has to be higher than the minimum pulse sequence which is set by the external reset delay capacitor CD. Calculation can be done according to the formulas given in Figure 5. Version 1.02 8 2001-10-15 Target Data TLE 6286 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. -0.3 6 V -0.3 40 V -20 32 V -20 40 V t<1s -0.3 VCC V 0 V < VCC < 5.5 V Voltages Supply voltage Battery supply voltage Bus input voltage Bus input voltage Logic voltages at EN, TxD, RxD Input voltages at INH VCC VS Vbus Vbus VI + 0.3 VINH -0.3 VS V + 0.3 Output current at INH Reset output voltage Reset delay voltage Output voltage Vcc INHIBIT voltage Watchdog voltage Electrostatic discharge voltage at Vs, Bus Electrostatic discharge voltage IINH VR VD VQ VINH VW VESD 1 mA – 0.3 42 V – 0.3 42 V – 0.3 7 V – – 42 45 V – – 0.3 6 V – -4 4 kV human body model (100 pF via 1.5 kΩ) VESD -2 2 kV human body model (100 pF via 1.5 kΩ) Tj -40 150 °C – – Temperatures Junction temperature Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Version 1.02 9 2001-10-15 Target Data TLE 6286 3.2 Operating Range Parameter Supply voltage Battery Supply Voltage Junction temperature Symbol VCC VS Tj Limit Values Unit Remarks min. max. 4.5 5.5 V 6 20 V – 40 150 °C – Thermal Shutdown (junction temperature) Thermal shutdown temp. Thermal shutdown hyst. TjSD ∆T 150 170 190 °C – 10 – K Rthj-a – 115 K/W Thermal Resistances Junction ambient Version 1.02 10 – 2001-10-15 Target Data TLE 6286 3.3 Electrical Characteristics 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Remarks Current Consumption Current consumption ICC 0.5 1.5 mA recessive state; VTxD = VCC Current consumption IS 0.5 1.0 mA recessive state; VTxD = VCC Current consumption ICC 0.7 2.0 mA dominant state; VTxD = 0 V Current consumption IS 0.7 1.5 mA dominant state; VTxD = 0 V Current consumption IS 20 30 µA sleep mode; Tj = 25 °C Current consumption IS 20 40 µA sleep mode IRD,H IRD,L -0.7 -0.4 mA VRD = 0.8 x VCC, Receiver Output R×D HIGH level output current LOW level output current 0.4 0.7 mA VRD = 0.2 x VCC, 0.44 x VS 0.48 x VS V -8 V < Vbus < Vbus,dom Bus receiver Receiver threshold voltage, recessive to dominant edge Vbus,rd Receiver threshold voltage, dominant to recessive edge Vbus,dr 0.52 x VS 0.56 x VS V Vbus,rec < Vbus < 20 V Receiver hysteresis Vbus,hys 0.02 x VS Vwake 0.40 x VS 0.04 x VS 0.06 x VS mV Vbus,hys = Vbus,rec - Vbus,dom 0.55 x VS 0.70 x VS V HIGH level input voltage threshold VTD,H 2.9 0.7 x V TxD input hysteresis VTD,hys wake-up threshold voltage Transmission Input T×D Version 1.02 recessive state VCC 300 11 600 mV 2001-10-15 Target Data TLE 6286 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. LOW level input voltage threshold VTD,L TxD pull up current ITD typ. Unit Remarks max. 0.3 x 2.1 V dominant state -80 µA VTxD < 0.3 Vcc VS V VTxD = VCC 1.5 V VTxD = 0 V; 125 mA Vbus,short = 13.5 V µA VCC = 0 V, VS = 0 V, Vbus = -8 V, Tj < 85 °C VCC = 0 V, VS = 0 V, Vbus = 20 V, Tj < 85 °C VCC -150 -110 Bus transmitter Bus recessive output voltage Vbus,rec 0.9 x VS Bus dominant output voltage Vbus,dom 0 Bus short circuit current Leakage current Bus pull up resistance Ibus,sc Ibus,lk Rbus 40 85 -350 -100 20 5 20 µA 30 47 kΩ 2.8 0.7 x V normal mode V low power mode Enable input (pin ENLIN) HIGH level input voltage threshold VEN,on LOW level input voltage threshold VEN,off EN input hysteresis VEN,hys REN EN pull down resistance VCC 0.3 x 2.2 VCC 300 600 mV 15 30 60 kΩ 0.5 1.0 V IINH = - 0.15 mA 5.0 µA sleep mode; VINHO = 0 V Inhibit output (pin INHO) HIGH level drop voltage ∆VINH = VS − VINH ∆VINH Leakage current IINH,lk Version 1.02 - 5.0 12 2001-10-15 Target Data TLE 6286 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Remarks Vcc Output (pin Vcc) Output voltage VQ 4.90 5.00 5.10 V 5 mA ≤ IQ ≤ 150 mA; 6 V ≤ VI ≤ 28 V Output voltage VQ 4.90 5.00 5.10 V 6 V ≤ VI ≤ 32 V; IQ = 100 mA; Tj = 100 °C Output current IQ Iq 200 250 – mA 1) – 0 50 µA VINH = 0 Iq Iq Iq Vdr ∆VQ,lo ∆VQ.li – – – 900 10 15 1300 µA 18 mA 23 mA – 0.35 0.50 V IQ = 150 mA1) – – 25 mV IQ = 5 mA to 150 mA – 3 25 mV VI = 6 V to 28 V; IQ = 150 mA PSRR – 54 – dB fr = 100 Hz; Vr = 0.5 VPP 4.5 4.65 4.8 V 1.26 1.35 1.44 V VQ > 3.5 V – 0.10 0.40 V IRO = 1 mA – 50 100 mV VQ < VR,th 1.45 1.70 2.05 V – 0.20 0.35 0.55 V – 40 60 85 µA – 1.3 2.8 4.1 ms CD = 100 nF 0.5 1.2 4 µs CD = 100 nF Current consumption; Iq = II – IQ Drop voltage Load regulation Line regulation Power Supply Ripple Rejection IQ = 0 mA IQ = 150 mA IQ = 150 mA; VI = 4.5 V Reset Genarator (pin RD) VQ,rt VRADJ,th Reset adjust threshold Reset low voltage VRO,l Saturation voltage VD,sat Upper timing threshold VDU Lower reset timing threshold VDRL Charge current ID,ch Reset delay time trd Reset reaction time trr Switching threshold Version 1.02 13 2001-10-15 Target Data TLE 6286 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Remarks min. typ. max. ID,wd VDU VDWL TWI,tr 4.40 6.25 9.10 µA VD = 1.0 V 1.45 1.70 2.05 V – 0.20 0.35 0.55 V – 16 22.5 27 ms CD = 100 nF VINH,ON VINH,OFF IINH 3.6 – – V IC turned on – – 0.8 V IC turned off 5 10 25 µA VINH = 5 V Watchdog (pin WD) Discharge current Upper timing threshold Lower timing threshold Watchdog trigger time Inhibit Input (INHI) Switching voltage Turn-OFF voltage Input current Note: The reset output is low within the range VQ = 1 V to VQ,rt 1) Drop voltage = Vi – VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 6 V input) Version 1.02 14 2001-10-15 Target Data TLE 6286 3.3 Electrical Characteristics (cont’d) 4.5 V < VCC < 5.5 V; 6.0 V < VS < 20 V; RL = 1 kΩ; VEN > VEN,ON; -40 °C < Tj < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Remarks Dynamic Transceiver Characteristics falling edge slew rate Sbus(L) -3 -2.0 -1 V/µs 80% > Vbus > 20% Cbus= 3.3 nF; Tambient < 85 °C; VCC = 5 V; VS = 13.5 V rising edge slew rate Sbus(H) 1 1.5 3 V/µs 20% < Vbus < 80% Cbus= 3.3 nF; VCC = 5 V; VS = 13.5 V Propagation delay td(L),TR TxD-to-RxD LOW (recessive to dominant) 2 5 10 µs Cbus = 3.3nF; VCC = 5 V; VS = 13.5 V CRxD = 20 pF Propagation delay td(H),TR TxD-to-RxD HIGH (dominant to recessive) 2 5 10 µs Cbus = 3.3 nF; VCC = 5 V; VS = 13.5 V CRxD = 20 nF Propagation delay TxD LOW to bus td(L),T 1 4 µs VCC = 5 V Propagation delay TxD HIGH to bus td(H),T 1 4 µs VCC = 5 V Propagation delay bus dominant to RxD LOW td(L),R 1 4 µs VCC = 5V; CRxD = 20pF Propagation delay bus recessive to RxD HIGH td(H),R 1 4 µs VCC = 5 V; CRxD = 20 pF Receiver delay symmetry tsym,R tsym,T twake -2 2 µs tsym,R = td(L),R - td(H),R -2 2 µs tsym,T = td(L),T - td(H),T 200 µs Transmitter delay symmetry Wake-up delay time Version 1.02 30 15 100 2001-10-15 Target Data TLE 6286 4 Diagrams VI < trr t VQ VQ, rt dV ID, ch = dt CD VD t VDU VDRL trd trr t VRO t Power-ON Reset Figure 4 Overtemperature Voltage Drop at Input Undervoltage Secondary Load Bounce Spike AET03066 Time Response, Watchdog with High-Frequency Clock VW t VΙ VQ t T WD, p VD t T WI, tr VDU VDWL VRO T WI, tr = t WD, L (VDU - VDWL ) Ι D, wd C D ; T WD, p = (VDU -VDWL ) (Ι D, wc + Ι D, wd ) Ι D, wc x Ι D, wd C D ; t WD, L = t (VDU - VDWL ) Ι D, wc t CD AED03099 Figure 5 Version 1.02 Timing of the Watchdog FunctionReset 16 2001-10-15 Target Data TLE 6286 5 Application Vbat LIN bus master node WD 13 RO 15 VBAT 22 µF 100 nF W 1k 12 5 ENLIN 7 RxD 6 2 µP TxD 11 Bus VS 10 INHO TLE 6286 G 14 3 100 nF VCC INHI RD GND 4 100 nF 5V 22 µF GND 1,8,9,16 CD 100 nF ECU 1 slave node WD 13 RO 15 VBAT 22 µF 100 nF 12 5 ENLIN 7 RxD 6 2 VS 10 INHO VCC INHI RD GND 100 nF Version 1.02 GND 100 nF 4 100 nF 5V 22 µF 1,8,9,16 CD Figure 6 µP TxD 11 Bus TLE 6286 G 14 3 ECU X Application Circuit 17 2001-10-15 Target Data TLE 6286 6 Package Outlines P-DSO-16-4 (Plastic Dual Small Outline Package) Pictures of the housing will be added in near future! Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Dimensions in mm Version 1.02 18 2001-10-15 Target Data TLE 6286 Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 München © Infineon Technologies AG1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Version 1.02 19 2001-10-15