High-Performance Memories for Packet Processing Chris Johnson Global DRAM Applications Engineering Manager ©2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. ©2012 Micron Technology, Inc. | 1 High Performance Networking Memories Requirements • • • • • • • Low-tRC/high access rate High bandwidth Density and Scalability Low pin-count Small footprint Low power consumption Reasonable system cost Trends • • • • • Low-tRC architectures Managed DRAM SerDes interfacing 2.5/3D integration Photonics Requires Leading Edge DRAM Technologies Commodity DRAM Architectures do not address these needs ©2012 Micron Technology, Inc. | 2 Commodity DRAMDRAM Drivers (DDR1/2/3/4) Commodity Drivers Volume Die Size Primary driver Increased die per wafer Equates directly to yield Improved yield Manufacturing efficiencies Test times Tooling Back end flexibility Amortized R&D cost Appropriate Design Margin IO Count Commodity Functionality ©2012 Micron Technology, Inc. | 3 Solutions for High Performance Reduced Page Size Faster core timing Lower power Increases die size Beef Up Power Bussing Eliminates tRRD and tFAW type restrictions Adds metal count or die size Reduce Turn Times Change functionality or architecture Added posting registers Adds die size ©2012 Micron Technology, Inc. | 4 RL3 Solves Access Rate Gap Reduce Random Access (Row Cycle Time Fragments the array Reduced digit line length Bus Turn-around Time Add WRITE registers Eliminate internal bus contention Eliminate RAS Chain Limitations Move to flip chip Increased power bussing ©2012 Micron Technology, Inc. | 5 Bus Turnaround Delay Effect on Bandwidth RL3 Delivers Sustained Bus Utilization Under Networking Workloads RL3-2133 BL8 RL2-1066 CIO BL8 DDR3-2133 BL8 CL=13 2,133 Bandwidth per Data Pin (Mb/s) 1,867 1,600 1,333 1,067 800 533 267 0 0.01 0.10 1.00 10.00 100.00 Read/Write Ratio Key Parameters • <8ns tRC • x36/x18 configurations • tRRD/tFAW – no delay • Burst Lengths 2,4,8 ©2012 Micron Technology, Inc. | 6 Process Characteristics DRAM Process Create really good capacitors Memory Cells Limits Speed Increases Power Limited Metal Layers Low Cost Logic Process Low Capacitance High speed Low Power Large number of metal steps Design flexibility ©2012 Micron Technology, Inc. | 7 Hybrid Memory Cube (HMC) Hybrid Memory Cube Introduction of Managed DRAM Through-Silicon Vias (TSV) Abstraction Protocol DRAM DRAM DRAM DRAM Many Buses > 1Tb/s Processor Logic Die High Speed Links Reduced Pin count Increased Bandwidth Note: Tb/s = Terabits / second ©2012 Micron Technology, Inc. | 8 HMC Architecture Logic Base Vault Control Vault Control Vault Control Vault Control Add advanced switching, optimized memory control and simple interface to host processor(s)… Memory Control Crossbar Switch Link Interface Controller Link Interface Controller Link Interface Controller Processor Links HMC T X Link Interface Controller 3DI & TSV Technology DRAM7 DRAM6 DRAM5 DRAM4 DRAM3 DRAM2 DRAM1 DRAM0 Logic Chip Host 16 Lanes R X Vault R X 16 Lanes T X DRAM Logic Base ©2012 Micron Technology, Inc. | 9 2.5D/2D/MCM System/3D 2.5D SOC IP Block DRAM Stack Si Interposer(2.5D) MCM substrate (2D) ▶ DRAM IP Block part of SOC Can be tailored to SOC interface requirement Emulate another DRAM technology interface if necessary Manage DRAM arrays ▶ Reduced memory footprint ▶ Various DRAM stacks for different purposes (e.g. low-power or low-latency) ▶ Short channel routing ▶ Ease of implementation into foundry model DRAM IP block available as part of node library 3D Opens New Possibilities DRAM Stack e.g. 64GB/s Parallel Interface PHY BIST, Repair, APG Memory Control (Refresh Scheduling, Sequencer, Read/Write Buffers, etc. ) ASIC *Size relationship of memory stack, IP blocks, and ASIC for illustration only and are not to scale. ©2012 Micron Technology, Inc. | 10