Advance‡ PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Introduction Micron PISMO™ Module Data Sheet PISMO2-00014: Mobile DDR DRAM + NAND Flash Package-On-Package Introduction The PISMO (Platform Independent Storage MOdule) specification provides a standard external interface to ease memory performance evaluation. This document describes the mechanical and functional features, configuration options, and design specifications of a Micron PISMO2-compliant module. This small, stackable module features a combination of Mobile DRAM and NAND Flash memory, as described in Table 1. The board includes: • Bottom connector to the host system (J2) • Top connector (J1, for stacking multiple boards) • 64Kb serial EEPROM for configuration and presence detection Micron PISMO2-00014 Features Physical Module Mechanics • • • • • Stackable memory module (up to four active modules) Plain rectangular PCB (60mm x 50mm) Stacking height: 7mm (other stacking heights will become available later) Supports additional debugging tools (for example, a logic state analyzer) Supports spacers with or without screw option Supported Memory Interfaces • Mobile DDR DRAM and NAND Flash PoP (MT29C1G12MABCACG/ MT29C1G12MADCACG) – 512Mb; x32; 1.8V Micron Mobile DDR SDRAM – 4 Meg x 32 x 4 banks – NAND memory: 1Gb; x16; 1.8V NAND Flash memory • Serial EEPROM for presence detection: 64Kb Table 1: PISMO2-00014 Module Memory Technologies Technology Mobile DDR DRAM NAND Flash PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Density Voltage Data Bus Package 512Mb 1Gb 1.8V 1.8V 32-bit 8- or 16-bit, multiplexed 152-ball FBGA 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Micron PISMO2-00014 Features Micron Mobile DDR DRAM and NAND PoP PISMO2 Module (PISMO2-00014) Top Side Bottom Side - + C40 C4 - C57 C3 R5 C56 C17 C19 C55 C23 C12 C21 C54 C11 C6 C42 + C8 C58 R15 R14 C18 C20 + C15 C5 MCP POP R10 R11 RN4 C41 U1 R9 C50 C51 C52 2 R4 C2 U5 C30 C7 C22 C53 5 R7 R3 C1 C31 C10 6 3 C61 R6 R8 R18 R17 C9 8 7 R16 C13 J1 J2 RN9 R13 R12 - Figure 1: C24 C16 C14 Mobile DDR DRAM Features • DM_VCORE = DM_POWER = +1.8V ±0.1V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center-aligned with data for WRITEs • Four internal banks for concurrent operation • Data masks (DM) for masking write data—one mask per byte • Programmable burst lengths: 2, 4, or 8 • Concurrent auto precharge option • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible signaling standard • On-chip temperature sensor to control refresh rate • Partial-array self refresh (PASR) • Deep power-down (DPD) • Selectable output drive (DS) • Clock-stop capability • 64ms refresh NAND Flash Features • Organization – Page size: 1,056 words (1,024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – Device size: 1,024/2,048 blocks • Read performance – Random read: 25µs – Sequential read: 50ns PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Pin Assignments and Descriptions • Write performance – Page program: 300µs (TYP) – Block erase: 2ms (TYP) • Endurance: 100,000 PROGRAM/ERASE cycles (with ECC and invalid block mapping) • The first block (block address 00h) is guaranteed to be valid without ECC (up to 1,000 PROGRAM/ERASE cycles) • NA_VCORE = NA_VI/O = NA_V18 = 1.65–1.95V • Automated PROGRAM and ERASE • Basic NAND command set – PAGE READ, RANDOM DATA READ, READ ID, READ STATUS – PROGRAM PAGE, RANDOM DATA INPUT, PROGRAM PAGE CACHE MODE – INTERNAL DATA MOVE, INTERNAL DATA MOVE with RANDOM DATA INPUT – BLOCK ERASE, RESET • Advanced NAND command set – PAGE READ CACHE MODE – READ ID2, READ UNIQUE ID • Operation status byte: provides a software method for detecting – PROGRAM/ERASE operation completion – PROGRAM/ERASE pass/fail condition – Write-protect status • Ready/Busy_N pin (R/B_N) provides a hardware method for detecting PROGRAM or ERASE cycle completion • Hardware write protect pin (WP_N) Pin Assignments and Descriptions The signal name prefixes are defined in Table 2. The signal locations within the bottom and top PISMO2-00014 connectors are listed in Table 3 on page 4 and Table 4 on page 5, respectively. Table 2: Naming Conventions for PISMO2 Specification Signals Signal Prefix SM DM NA FS AUX PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Definition The “SM_” prefix identifies PISMO2 static memory interface signals. This interface supports NOR Flash, DiskOnChip, SRAM or PSRAM memory, and memory-mapped I/O devices. The “DM_” prefix identifies PISMO2 dynamic memory interface signals. This interface supports single data rate (SDR) or double data rate (DDR) SDRAM memory. The “NA_” prefix identifies PISMO2 NAND memory interface signals. This interface supports NAND Flash memory. The “FS_” prefix identifies PISMO2 serial memory interface signals. This interface supports serial Flash memory or I/O devices with a serial bus interface. The “AUX_” prefix identifies PISMO2 module management interface signals. This interface supports hardware production and testing, module control functions, and plug-and-play enumeration. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Pin Assignments and Descriptions Table 3: PISMO2-00014 Bottom Connector (J2) Pin Assignments Col. Row A Row B Row C Row D Row E Row F Row G Row H 1 DM_DQS3_DH DM_DQS3_DL DNU11 DM_CS1_N VSS46 FS_SCK FS_SO FS_RESET_N 2 DM_D26 DM_D24 DM_BA2 DM_A15 DM_A4 VSS45 FS_SI FS_HOLD_N 3 DM_D27 DM_D25 DM_RESET_N DM_A7 DM_A6 FS_V33_0 DNU9 FS_CS3_N 4 DM_D29 DM_D28 DM_ODT1 DM_A11 DM_A9 VSS44 FS_VIO_1 FS_CS2_N 5 DM_D30 DM_D31 DM_ODT0 DM_CKE1 DM_CKE0 VSS43 FS_VIO_0 FS_CS1_N 6 DM_DQS1_DH DM_DQS1_DL DM_VREF DM_A14 DM_DQM3 VSS42 FS_V18_0 FS_CS0_N 7 DM_D8 DM_D9 DM_VIO_9 DM_A8 DM_A12 VSS41 FS_WP_N AUX_SA2 8 DM_D10 DM_D11 DM_VIO_3 DM_DQM1 DM_A5 VSS40 AUX_SCL AUX_SA1 9 DM_D12 DM_D13 DM_VIO_6 VSS37 VSS38 VSS39 AUX_SDA AUX_SA0 10 DM_D15 DM_D14 DM_VIO_5 DM_CLK1_DH DM_CLK1_DL VSS36 AUX_TDI AUX_TDO 11 DM_D1 DM_D0 DM_VIO_8 VSS34 VSS35 AUX_V33_1 AUX_TCK AUX_TMS 12 DM_D3 DM_D2 DM_VIO_4 DM_CLK0_DH DM_CLK0_DL VSS33 DNU13 AUX_PRESENT_N 13 DM_D5 DM_D4 DM_VCC_3 VSS31 VSS32 AUX_V33_0 AUX_POR_N AUX_HMR_N 14 DM_D6 DM_D7 DM_VIO_2 DM_A10 DM_A2 VSS30 AUX_V33_2 AUX_STANDBY_N 15 DM_DQS0_DH DM_DQS0_DL DM_VIO_7 DM_WE_N DM_CS0_N VSS29 DNU7 DNU8 16 DM_D16 DM_D17 DM_VCC_2 DM_DQM0 DM_A13 NA_VIO_2 NA_IO15 NA_IO7 17 DM_D19 DM_D18 DM_VCC_1 DM_RAS_N DM_CAS_N VSS28 NA_IO14 NA_IO6 18 DM_D22 DM_D20 DM_VIO_1 DM_BA1 DM_BA0 VSS27 NA_IO13 NA_IO5 19 DM_D23 DM_D21 DM_VIO_0 DM_A1 DM_A0 VSS26 NA_IO12 NA_IO4 20 DM_DQS2_DH DM_DQS2_DL DM_VCC_0 DM_DQM2 DM_A3 VSS25 NA_IO11 NA_IO3 21 VSS20 VSS21 VSS22 VSS23 VSS24 NA_VIO_1 NA_IO10 NA_IO2 NA_IO1 22 SM_D23 SM_D31 SM_V33_2 SM_A30 SM_A31 VSS19 NA_IO9 23 SM_D22 SM_D30 SM_V33_1 SM_A28 SM_A29 VSS18 NA_IO8 NA_IO0 24 SM_D21 SM_D29 SM_V33_0 SM_A26 SM_A27 VSS17 DNU12 NA_PRE 25 SM_D20 SM_D28 SM_VIO_8 SM_A24 SM_A25 VSS16 NA_RY NA_RE_N 26 SM_D19 SM_D27 SM_VIO_7 SM_A22 SM_A23 NA_VIO_0 NA_CS2_N NA_CS3_N 27 SM_D18 SM_D26 SM_VIO_6 SM_A20 SM_A21 NA_V33_0 NA_CS1_N NA_CS0_N 28 SM_D17 SM_D25 SM_VIO_5 SM_A18 SM_A19 NA_V18_0 NA_CLE NA_ALE 29 SM_D16 SM_D24 SM_CLK3 SM_A16 SM_A17 VSS15 NA_WE_N NA_WP_N 30 DNU16 VSS12 SM_CLK2 VSS13 SM_BE2 VSS14 DNU5 DNU6 31 DNU17 VSS9 SM_CLK1 VSS10 SM_BE3 SM_OE_N VSS11 DNU4 32 SM_D7 SM_D15 SM_CLK0 SM_A14 SM_A15 SM_WE_N VSS8 DNU3 33 SM_D6 SM_D14 SM_VIO_4 SM_A12 SM_A13 SM_LBA_N VSS7 SM_WP_N 34 SM_D5 SM_D13 SM_VIO_3 SM_A10 SM_A11 SM_BUSY_N VSS6 SM_RESET_N 35 SM_D4 SM_D12 SM_VIO_2 SM_A8 SM_A9 SM_BWAIT_N VSS5 SM_PD 36 SM_D3 SM_D11 SM_VIO_1 SM_A6 SM_A7 VSS4 DNU1 DNU2 37 SM_D2 SM_D10 SM_VIO_0 SM_A4 SM_A5 VSS3 SM_IRQ_N SM_CS3_N SM_CS2_N 38 SM_D1 SM_D9 SM_V18_2 SM_A2 SM_A3 VSS2 SM_CRE 39 SM_D0 SM_D8 SM_V18_1 SM_A0 SM_A1 VSS1 SM_DMARQ_N SM_CS1_N 40 DNU14 DNU15 SM_V18_0 SM_BE0 SM_BE1 VSS0 DNU0 SM_CS0_N PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Pin Assignments and Descriptions Table 4: PISMO2-00014 Top Connector (J1) Pin Assignments Col. Row A Row B Row C 1 DM_DQS3_DH DM_DQS3_DL DNU11 2 DM_D26 DM_D24 DM_BA2 3 DM_D27 DM_D25 DM_RESET_N 4 DM_D29 DM_D28 Row D Row E Row F Row G Row H DM_FB VSS46 FS_SCK FS_SO FS_RESET_N DM_A15 DM_A4 VSS45 FS_SI FS_HOLD_N DM_A7 DM_A6 FS_V33_0 DNU9 FS_CS3_N DM_ODT1 DM_A11 DM_A9 VSS44 FS_VIO_1 FS_CS2_N FS_CS1_N 5 DM_D30 DM_D31 DM_ODT0 DM_CKE1 DM_CKE0 VSS43 FS_VIO_0 6 DM_DQS1_DH DM_DQS1_DL DM_VREF DM_A14 DM_DQM3 VSS42 FS_V18_0 FS_CS0_N 7 DM_D8 DM_D9 DM_VIO_9 DM_A8 DM_A12 VSS41 FS_WP_N AUX_SA1 8 DM_D10 DM_D11 DM_VIO_3 DM_DQM1 DM_A5 VSS40 AUX_SCL AUX_SA0 9 DM_D12 DM_D13 DM_VIO_6 VSS37 VSS38 VSS39 AUX_SDA AUX_V33 10 DM_D15 DM_D14 DM_VIO_5 DM_CLK1_DH DM_CLK1_DL VSS36 AUX_TDI AUX_TDO 11 DM_D1 DM_D0 DM_VIO_8 VSS34 VSS35 AUX_V33_1 AUX_TCK AUX_TMS 12 DM_D3 DM_D2 DM_VIO_4 DM_CLK0_DH DM_CLK0_DL VSS33 DNU13 AUX_PRESENT_N 13 DM_D5 DM_D4 DM_VCC_3 VSS31 VSS32 AUX_V33_0 AUX_POR_N AUX_HMR_N 14 DM_D6 DM_D7 DM_VIO_2 DM_A10 DM_A2 VSS30 AUX_V33_2 AUX_STANDBY_N 15 DM_DQS0_DH DM_DQS0_DL DM_VIO_7 DM_WE_N DM_CS1_N VSS29 DNU7 DNU8 16 DM_D16 DM_D17 DM_VCC_2 DM_DQM0 DM_A13 NA_VIO_2 NA_IO15 NA_IO7 17 DM_D19 DM_D18 DM_VCC_1 DM_RAS_N DM_CAS_N VSS28 NA_IO14 NA_IO6 18 DM_D22 DM_D20 DM_VIO_1 DM_BA1 DM_BA0 VSS27 NA_IO13 NA_IO5 19 DM_D23 DM_D21 DM_VIO_0 DM_A1 DM_A0 VSS26 NA_IO12 NA_IO4 20 DM_DQS2_DH DM_DQS2_DL DM_VCC_0 DM_DQM2 DM_A3 VSS25 NA_IO11 NA_IO3 21 VSS20 VSS21 VSS22 VSS23 VSS24 NA_VIO_1 NA_IO10 NA_IO2 22 SM_D23 SM_D31 SM_V33_2 SM_A30 SM_A31 VSS19 NA_IO9 NA_IO1 23 SM_D22 SM_D30 SM_V33_1 SM_A28 SM_A29 VSS18 NA_IO8 NA_IO0 24 SM_D21 SM_D29 SM_V33_0 SM_A26 SM_A27 VSS17 DNU12 NA_PRE NA_RE_N 25 SM_D20 SM_D28 SM_VIO_8 SM_A24 SM_A25 VSS16 NA_RY 26 SM_D19 SM_D27 SM_VIO_7 SM_A22 SM_A23 NA_VIO_0 NA_CS3_N NA_FB 27 SM_D18 SM_D26 SM_VIO_6 SM_A20 SM_A21 NA_V33_0 NA_CS2_N NA_CS1_N 28 SM_D17 SM_D25 SM_VIO_5 SM_A18 SM_A19 NA_V18_0 NA_CLE NA_ALE 29 SM_D16 SM_D24 SM_CLK3 SM_A16 SM_A17 VSS15 NA_WE_N NA_WP_N 30 DNU16 VSS12 SM_CLK2 VSS13 SM_BE2 VSS14 DNU5 DNU6 31 DNU17 VSS9 SM_CLK1 VSS10 SM_BE3 SM_OE_N VSS11 DNU4 32 SM_D7 SM_D15 SM_CLK0 SM_A14 SM_A15 SM_WE_N VSS8 DNU3 33 SM_D6 SM_D14 SM_VIO_4 SM_A12 SM_A13 SM_LBA_N VSS7 SM_WP_N 34 SM_D5 SM_D13 SM_VIO_3 SM_A10 SM_A11 SM_BUSY_N VSS6 SM_RESET_N 35 SM_D4 SM_D12 SM_VIO_2 SM_A8 SM_A9 SM_BWAIT_N VSS5 SM_PD 36 SM_D3 SM_D11 SM_VIO_1 SM_A6 SM_A7 VSS4 DNU1 DNU2 37 SM_D2 SM_D10 SM_VIO_0 SM_A4 SM_A5 VSS3 SM_IRQ_N SM_CS3_N 38 SM_D1 SM_D9 SM_V18_2 SM_A2 SM_A3 VSS2 SM_CRE SM_CS2_N 39 SM_D0 SM_D8 SM_V18_1 SM_A0 SM_A1 VSS1 SM_DMARQ_N SM_CS1_N 40 DNU14 DNU15 SM_V18_0 SM_BE0 SM_BE1 VSS0 DNU0 SM_CS0_N Table 5 on page 6 lists and briefly describes all (and only) the signals that are routed to and from the memory devices installed on the PISMO2-00014, with reference to the corresponding bottom connector ball. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Pin Assignments and Descriptions Table 5: PISMO2-00014 Ball Description (Referenced to the Bottom Connector) Ball No. (Bottom) Symbol Type Description DM_CLK0_DH DM_CLK0_DL Input E5 DM_CKE0 Input E15 DM_CS0_N Input D17 DM_RAS_N Input E17 DM_CAS_N Input D15 DM_WE_N Input DM_DQM0 to DM_DQM3 Input DM_BA0 DM_BA1 Input DM_A0 to DM_A13 Input System clock: DM_CLK_DH and DM_CLK_DL are differential clock inputs. All address and control input signals are sampled on the positive edge of DM_CLK_DH and the negative edge of DM_CLK_DL. Output (read) data is referenced to both edges of DM_CLK. Internal clock signals are derived from DM_CLK_DH/ DM_CLK_DL. Mobile SDRAM only uses DM_CLK_DH. Both DM_CLK_DH and DM_CLK_DL apply to Mobile DDR SDRAM. Clock enable: DM_CKE HIGH activates, and DM_CKE LOW deactivates, internal clock signals and device input buffers and output drivers. Taking DM_CKE LOW provides PRECHARGE power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). DM_CKE is synchronous for power-down entry and exit, and for self refresh entry. DM_CKE is asynchronous for self refresh exit. DM_CKE must be kept HIGH throughout read and write accesses. Chip select: DM_CS_N enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when DM_CS_N is registered HIGH. DM_CS_N provides external bank selection on multi-bank systems. DM_CS_N is considered part of the command code. Row address strobe: Latches row addresses on the positive edge of the DM_CLK with DM_RAS_N LOW. Enables row access and precharge. Column address strobe: Latches column addresses on the positive edge of the DM_CLK with DM_CAS_N LOW. Enables column access. Write enable: Enables WRITE operation and row precharge. Latches data in starting from DM_CAS_N, DM_WE_N active. Data input/output mask: Makes data output High-Z, tSHZ after the clock and masks the output. Blocks data input when DM_DQM active. Bank select address: DM_BA0 and DM_BA1 define which bank an ACTIVE, READ, WRITE, or PRECHARGE command is applied to. Bank address also determines whether the mode register or extended mode register is to be accessed during an MRS or EMRS cycle. Address: Row/column addresses are multiplexed on the same pins. DM_D0 to DM_D31 I/O Data input/output: Data inputs/outputs are multiplexed on the same pins. DM_DQS0_DH to DM_DQS3_DH I/O Data strobes: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Only applicable to Mobile DDR configurations. DRAM Section D12, E12 D16, D8, D20, E6 E18, D18 E19, D19, E14, E20, E2, E8, E3, D3, D7, E4, D14, D4, E7, E16 B11, A11, B12, A12, B13, A13, A14, B14, A7, B7, A8, B8, A9, B9, B10, A10, A16, B16, B17, A17, B18, B19, A18, A19, B2, B3, A2, A3, B4, A4, A5, B5 A15, A6, A20, A1 PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Pin Assignments and Descriptions Table 5: PISMO2-00014 Ball Description (Referenced to the Bottom Connector) (Continued) Ball No. (Bottom) Symbol Type DM_VIO_0 to DM_VIO_3 DM_V18_0 to DM_V18_6 Supply NA_ALE Input H27 NA_CS0_N Input G28 NA_CLE Input H25 NA_RE_N Input G29 NA_WE_N Input H29 NA_WP_N Input H23, H22, H21, H20, H19, H18, H17, H16, G23, G22, G21, G20, G19, G18, G17, G16 G25 NA_IO0 to NA_IO15 I/O NA_RY Output F28 NA_V18_0 Supply C19, C18, C14, C8, C12, C10, C9, C15, C11, C7 C20, C17, C16, C13 NAND Section H28 Supply Description Data output power: Isolates the output buffer power supply to provide improved noise immunity. Power supply: Power for the core logic. Address latch enable: Controls the address registers. When active (HIGH), an address is latched from NA_IO0–NA_IO7 into the address registers with the rising edge of the write enable signal. When addresses are not being loaded, NA_ALE is driven LOW. Chip enable (active-LOW signal): These device select control signals are active (LOW) and are ignored during any of the busy states. The NAND devices go into a low-power standby mode when driven HIGH during ready states. The host should implement as many chip select signals as supported by the host CPU, starting at NA_CS0_N and pulling-up all remaining NA_CSN_N signals to NA_VIO. Command latch enable: Controls the command register. When active (HIGH), commands are latched from NA_IO0–NA_IO7 into the register with the rising edge of the write enable signal. When a command is not being loaded, this signal is driven LOW. Read enable (active-LOW signal): Initiates the transfer of information from the device to the host and increments the internal column counter by one. Information is valid when it is active (LOW) and is driven HIGH when information is not being transferred. Write enable (active-LOW signal): Initiates the transfer of information from the host to the device. Command, address, and data are latched with the rising edge and WE is driven HIGH when information is not being transferred. Write protect (active-LOW signal): Provides a hardware method for protecting NAND memory contents. LOW means write-protected. Data inputs and outputs: These bidirectional signals are used to input command and address. They can input data during WRITE operation and output data during READ operation. All signals are inputs during non-READ operations. Ready/Busy: Indicates the operating condition of the device. It is busy, active (LOW) during PROGRAM, ERASE, and READ operation and returns to ready, active (HIGH) after completing the operation. This signal is an open drain output buffer on memory modules. The host must implement a pull-up resistor to NA_VIO. The value of this pull-up resistor determines the rise time of the NA_RY signal and should be calculated as specified in the NAND Flash memory data sheets. 1.8V power supply: The host implementation supplies 1.8V DC on this pin, independent of the I/O voltage. This power supply is used as memory core voltage. EEPROM Section PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Pin Assignments and Descriptions Table 5: PISMO2-00014 Ball Description (Referenced to the Bottom Connector) (Continued) Ball No. (Bottom) H9, H8, H7 G8 G9 F13, F11, G14 Ground Pins F40, F39, F38, F37, F36, G35, G34, G33, G32, B31, D31, G31, B30, D30, F30, F29, F25, F24, F23, F22, A21, B21, C21, D21, E21, F20, F19, F18, F17, F15, F14, D13, E13, F12, D11, E11, F10, D9, E9, F9, F8, F7, F6, F5, F4, F2, E1 PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Symbol Type Description AUX_SA0 to AUX_SA2 Input AUX_SCL AUX_SDA Input I/O AUX_V33_0 to AUX_V33_2 Supply Used by the EEPROM for multiple device operation. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the comparison is true. Up to eight devices may be connected to the same bus by using different chip select bit combinations. Synchronizes data transfer to and from the device. This bidirectional pin transfers addresses and data into and data out of the device. It is an open drain terminal; therefore, the SDA bus requires a pull-up resistor to VCC (typical 10kΩ for 100 kHz, 2kΩ for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL LOW. Changes during SCL HIGH are reserved for indicating start and stop conditions. +1.8V to 5.5V power supply. VSS0 to VSS46 Supply Ground. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Functional Block Diagram Functional Block Diagram Figure 2 illustrates the connections among the host system, the PISMO2-00014 DRAM/ NAND (MT29C1G12MABCACG or MT29C1G12MADCACG) interface, and the presencedetect EEPROM. All the listed interface signals are also connected straight through from bottom to top on the PISMO2 connector, except the DM_CS[1:0] and NA_CS[3:0] signals, which are connected as shown in “Chip Select Routing” on page 10. The STATIC and FAST SERIAL interface signals are only “routed through” (no devices are connected). For clarity, in Figure 2, the NAND and DRAM interface signal connections between the top and bottom connectors have been omitted. Figure 2: PISMO2-00014 Functional Block Diagram CPU PISMO2-00014 DRAM Controller DRAM Interface DRAM Interface NAND and Mobile DDR PoP DM_ BUS 512Mb Mobile DDR NAND Interface NAND Controller NAND Interface NA_ BUS 1Gb NAND Flash Auxiliary Signals Interface Auxiliary Signals Controller Microchip Auxiliary Interface PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN AUX_ BUS 9 24AA64-I/ST I2C Serial EEPROM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Chip Select Routing Chip Select Routing The PISMO2 specification enables the DRAM interface to support up to two memory banks, adopting the same signaling, whereas up to four memory banks can be connected to the static interface, and four memory banks can be connected to the NAND interface. The Micron PISMO2-00014 memory module uses one DRAM and one NAND bank in the same package, but with separate interfaces. Table 6 clarifies the chip select routing scheme adopted for this implementation. This method automatically maps host controller chip select signals to the NAND memory banks installed within a PISMO2 memory module stack. If the number of stacked memory banks exceeds host controller support, only the first two DRAM, the first four static, and the first four NAND banks (starting at the bottommost module) are used. All remaining banks are forced inactive. Table 6: PISMO2-00014 DRAM and NAND Interface Chip Select Routing Chip Select Connections Memory Interface DRAM Interface – 1 device installed (MCP) – 1 CS_N used Bottom Side Top Side DM_CS0_N To Mobile DDR (MCP) DM_CS0_N DM_CS1_N DM_CS1_N DM_VIO Chip Select Routing Top Connector DM_CS0_N DM_CS1_N To the DRAM interface of the MCP DM_IO DM_CS0_N DM_CS1_N Bottom Connector NAND Interface – 1 device installed (MCP) – 1 CS_N used NA_CS0_N NA_CS1_N NA_CS2_N NA_CS3_N NA_VIO To NAND (MCP) Top Connector NA_CS0_N NA_CS0# NA_CS1# NA_CS1_N NA_CS2_N NA_CS3_N To the NA_CS2# NA_CS3# NAND interface of the MCP NA_CS0# NA_FB NA_CS1# NA_CS2# NA_CS3# Bottom Connector Design for Testability Although the PISMO2 specification prohibits routing used chip selects back to the top connector, the PISMO2-00014 board features a configuration option that enables the user to scope CS# with the Micron PISMO2-P6960 logic state analyzer (LSA) tile. Every chip select signal that is connected to an installed memory chip can be routed back to the higher CS# position available for the bank on the top connector, just by moving a configuration resistor. (For example, the NA_CS0_N ball of the bottom connector can be routed back to NA_CS3_N position of the top connector by R10.) Configuration options are listed in Table 7 on page 11. See the PISMO2-P6960 data sheet for more information. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Serial Presence-Detect Table 7: PISMO2-00014 CS# Feedback Configurations Configuration Resistor Top Connector Position Notes Signal R12 DM_VIO D1 R13 DM_CS0_N D1 R14 NA_POWER H26 R15 NA_CS0_N H26 If R12 is installed, the board is compliant with the PISMO2 specification If R13 is installed, the CS is routed back to the top connector If R14 is installed, the board is compliant with the PISMO2 specification If R15 is installed, the CS is routed back to the top connector Serial Presence-Detect The Micron PISMO2-00014 module features serial presence-detect (SPD). The SPD function is implemented using a 64Kb serial EEPROM compliant with the PISMO2 specification. This nonvolatile storage device contains 8KB. System READ/WRITE operations between the master (host system) and the slave EEPROM device occur via a standard I2C bus using the PISMO2-00014 AUX_SCL (clock) and AUX_SDA (data) signals, together with AUX_SA[2:0], which provide eight unique PISMO2/EEPROM addresses. The memory write protect pin (WP_N) is tied to ground on the module, permanently disabling hardware write protect. All these signals are in the AUX_V33 I/O voltage domain, which is fixed at 3.3V. The configuration EEPROM contains information about the memory module itself, such as vendor, complete part number, and serial number. It also contains information about the memory devices installed on the module. The operating system or the application running on the host system processor can use the data from the configuration EEPROM to perform the following tasks: • Initialize the memory space • Identify the PISMO2 memory card vendors, model, and revision • Validate system configurations • Query product names of installed memory devices in terms of speed grade, data bus width, density of memory chip, and addressing scheme • Query key memory device parameters, such as timing and voltage options • Optimize host controller settings according to detected memory parameters • Select optimized programming algorithms • Select software drivers based on identified memory modules • Obtain additional vendor-specific information The Micron PISMO2-00014 board complies with the PISMO 2.0 specification, which defines a scheme for automatically assigning two-wire addresses to two-wire devices on the memory module. As shown in Figure 3, the PISMO2-00014 module automatically assigns two-wire device addresses by module location in the stack. No additional logic is required for this function. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Serial EEPROM Data Structure Figure 3: PISMO2-00014 Two-Wire Address Generation Scheme Host Memory Module A AUX_V33 Memory Module B AUX_V33 AUX_V33 Bottom Top Bottom AUX_SCL AUX_SDA AUX_SCL AUX_SDA AUX_SCL AUX_SDA AUX_SCL AUX_SDA AUX_SA0 AUX_SA1 AUX_SA2 AUX_SA0 AUX_SA1 AUX_SA2 AUX_SA0 AUX_SA1 AUX_SA2 AUX_SA0 AUX_SA1 AUX_SA2 On-board two-wire device(s) SCL SDA A0 A1 A2 Two-wire address(es): A6 A5 A4 A3 0 0 0 R/W Two-wire address(es): 2nd module: xxxx001x 3rd module: xxxx011x 4th module: xxxx111x The connections shown in Figure 3 result in the two-wire device address assignments shown in Table 8. Table 8: EEPROM Addresses Memory Module Stack Location EEPROM Address (Hexadecimal) 1st 0xA0 (WRITE), 0xA1 (READ) 0xA2 (WRITE), 0xA3 (READ) 0xA6 (WRITE), 0xA7 (READ) 0xAE (WRITE), 0xAF (READ) memory module (bottommost) 2nd memory module 3rd memory module 4th memory module (topmost) Serial EEPROM Data Structure TBD Mechanical Specifications Connector Description The PISMO2-00014 board/host system connection is provided by a Samtec SE (singleended) array connector system designed for high-speed/high-density applications where high pin-count flexibility, space savings, and routability are critical. The Edge Rate™ blade and beam interface was designed to provide maximum signal integrity at 50Ω on a popular 0.050in x 0.050in grid. The SE array connector has been tested up to 4 GHz (single-ended) and 9 GHz (differentially) at the 7mm mated height. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Mechanical Specifications Figure 4: PISMO2 Connectors For clarity, some contacts are not shown SEAF (Female) Connector SEAM (Male) Connector Connector Specifications • • • • • • • • • • PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Male P/N: SEAM-40-02.0-SM-8-2-A-K Female P/N: SEAF-40-05.0-SM-8-2-A-K Black liquid crystal polymer 320 positions (8 x 40 grid) 1.27mm (0.050in) pitch 7mm mated height 30 microinch Au duplex contact plating Copper alloy contact material –55°C to +125°C operating temperature range Pb-free solder 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Memory Module Memory Module Figure 5 illustrates the mechanical construction of the PISMO2-00014 memory module. The A1 mark denotes the location of the A1 pin on both connectors. Figure 5: PISMO2-00014 Memory Module Dimensions Top view Bottom view 60.0 7.0 30.0 26.0 50.0 39.0 A1 A1 26.0 Side views 11.2 1.5 SEAF (female/top) SEAM (male/bottom) The bottom side is used as the primary assembly side. The top side carries module documentation, such as the label. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Vertical Space Vertical Space The connectors chosen for PISMO2 use a 7mm stacked height. This means that a 7mm vertical space exists between the host system and the first memory module PCBs and also between the PCBs of the two neighboring memory modules. The PISMO2 specification defines requirements for vertical space assignments on PISMO2 memory modules and host controllers. Because Micron’s PISMO2-00014 complies with this requirement, it can be plugged into any PISMO2 host controller or on top of any other memory module. Figure 6 illustrates the PISMO2 vertical space requirements. Figure 6: PISMO2-00014 Vertical Space Requirements SEAF Label Assembly side SEAM Top side Bottom (assembly aide) Maximum component height: 2mm Maximum component height: 4mm No components in keep-out areas around mounting holes Label Ø8.0 PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Ø8.0 15 Ø8.0 Ø8.0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Schematics Figure 7: Bottom Connector Schematic 4 5 3 1 2 SM_A[0..31] DM_D[0..31] DM_D[0..31] STATIC MEMORY INTERFACE DM_A[0..15] AUX_3V3 F13 F11 G14 DYNAMIC MEMORY INTERFACE DM_A0 DM_A1 DM_A2 DM_A3 DM_A4 DM_A5 DM_A6 DM_A7 DM_A8 DM_A9 DM_A10 DM_A11 DM_A12 DM_A13 DM_A14 DM_A15 DM_A0 DM_A1 DM_A2 DM_A3 DM_A4 DM_A5 DM_A6 DM_A7 DM_A8 DM_A9 DM_A10 DM_A11 DM_A12 DM_A13 DM_A14 DM_A15 DM_BA0 DM_BA1 DM_BA2 DM_BA0 DM_BA1 DM_BA2 E18 D 18 C2 DM_BA0 DM_BA1 DM_BA2 DM_DQM0 DM_DQM1 DM_DQM2 DM_DQM3 D16 D8 D20 E6 DM_DQM0 DM_DQM1 DM_DQM2 DM_DQM3 DM_CLK0_DL DM_CLK0_DH DM_CKE0 E12 D12 E5 DM_CLK0_DL DM_CLK0_DH DM_CKE0 DM_CLK1_DL DM_CLK1_DH DM_CKE1 E10 D10 D5 DM_CLK1_DL DM_CLK1_DH DM_CKE1 DM_CLK0_DL DM_CLK0_DH DM_CKE0 C DM_CLK1_DL DM_CLK1_DH DM_CKE1 DM_RAS_N DM_CAS_N DM_WE_N DM_RAS_N DM_CAS_N DM_WE_N 16 DM_CS0_N DM_CS1_N_BOT D17 E17 D15 DM_RAS_N DM_CAS_N DM_WE_N DM_CS0_N E15 DM_CS1_N_BOT D1 DM_CS0_N DM_CS1_N DM_RESET_N C3 DM_RESET_N DM_ODT0 DM_ODT1 C5 C4 DM_ODT0 DM_ODT1 DM_RESET_N DM_ODT0 DM_ODT1 DM_D0 DM_D1 DM_D2 DM_D3 DM_D4 DM_D5 DM_D6 DM_D7 DM_D8 DM_D9 DM_D10 DM_D11 DM_D12 DM_D13 DM_D14 DM_D15 DM_D16 DM_D17 DM_D18 DM_D19 DM_D20 DM_D21 DM_D22 DM_D23 DM_D24 DM_D25 DM_D26 DM_D27 DM_D28 DM_D29 DM_D30 DM_D31 B11 A11 B12 A12 B13 A13 A14 B14 A7 B7 A8 B8 A9 B9 B10 A10 A16 B16 B17 A17 B18 B19 A18 A19 B2 B3 A2 A3 B4 A4 A5 B5 DM_D0 DM_D1 DM_D2 DM_D3 DM_D4 DM_D5 DM_D6 DM_D7 DM_D8 DM_D9 DM_D10 DM_D11 DM_D12 DM_D13 DM_D14 DM_D15 DM_D16 DM_D17 DM_D18 DM_D19 DM_D20 DM_D21 DM_D22 DM_D23 DM_D24 DM_D25 DM_D26 DM_D27 DM_D28 DM_D29 DM_D30 DM_D31 DM_DQS0_DL DM_DQS0_DH B15 A15 DM_DQS0_DL DM_DQS0_DH DM_DQS1_DL DM_DQS1_DH B6 A6 DM_DQS1_DL DM_DQS1_DH DM_DQS2_DL DM_DQS2_DH B20 A20 DM_DQS2_DL DM_DQS2_DH DM_DQS3_DL DM_DQS3_DH B1 A1 DM_DQS3_DL DM_DQS3_DH DM_VREF C6 AUX_V33_0 AUX_V33_1 AUX_V33_2 SM_VIO SM_3V3 SM_1V8 C37 C36 C35 C34 C33 C28 C27 C 26 C25 C24 C23 C22 C40 C39 C38 SM_VIO_0 SM_VIO_1 SM_VIO_2 SM_VIO_3 SM_VIO_4 SM_VIO_5 SM_VIO_6 SM_VIO_7 SM_VIO_8 SM_V33_0 SM_V33_1 SM_V33_2 SM_V18_0 SM_V18_1 SM_V18_2 C19 C18 C14 C8 C12 C10 C9 C15 C11 C7 C20 C17 C16 C13 DM_VIO_0 DM_VIO_1 DM_VIO_2 DM_VIO_3 DM_VIO_4 DM_VIO_5 DM_VIO_6 DM_VIO_7 DM_VIO_8 DM_VIO_9 DM_VCC_0 DM_VCC_1 DM_VCC_2 DM_VCC_3 DM_POWER DM_DQS0_DL DM_DQS0_DH DM_DQS1_DL DM_DQS1_DH FS_VIO DM_DQS2_DL DM_DQS2_DHVref DM_DQS3_DL DM_DQS3_DH FS_3V3 G5 G4 F3 G6 FS_1V8 FS_VIO_0 FS_VIO_1 FS_V33_0 FS_V18_0 J2G SEAM-40-02.0-S-08-2-A-K B F26 F 21 F16 F27 F 28 NA_1V8 DNU DNU0 DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU11 DNU12 DNU13 DNU14 DNU15 DNU16 DNU17 NA_VIO_0 NA_VIO_1 NA_VIO_2 NA_V33_0 NA_V18_0 STATIC MEMORY VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 DYNAMIC VSS25 MEMORY VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 FAST SERIAL VSS38 MEMORY VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 NAND F40 F39 F38 F37 F36 G35 G34 G33 G32 B31 D31 G31 B30 D30 F30 F29 F25 F24 F23 F22 A21 B21 C 21 D21 E21 F20 F19 F18 F17 F15 F14 D 13 E13 F12 D11 E11 F10 D9 E9 F9 F8 F7 F6 F5 F4 F2 E1 SM_BE0 SM_BE1 SM_BE2 SM_BE3 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 SM_CS0_N SM_CS1_N SM_CS2_N SM_CS3_N SM_WE_N SM_OE_N SM_LBA_N SM_WP_N SM_RESET_N SM_CRE_N FS_CS0_N FS_CS1_N FS_CS2_N FS_CS3_N AUX AUX_SDA AUX_SCL AUX_SA0_BOT AUX_SA1_BOT AUX_SA2_BOT SM_BE0 SM_BE1 SM_BE2 SM_BE3 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 C32 C31 C30 C29 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 SM_CS0_N SM_CS1_N SM_CS2_N SM_CS3_N H40 H39 H38 H37 SM_CS0_N SM_CS1_N SM_CS2_N SM_CS3_N SM_WE_N SM_OE_N SM_LBA_N SM_WP_N SM_RESET_N SM_CRE_N F32 F31 F33 H33 H34 G38 SM_WE_N SM_OE_N SM_LBA_N SM_WP_N SM_RESET_N SM_CRE_N SM_PD_N H35 SM_PD_N SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_D8 SM_D9 SM_D10 SM_D11 SM_D12 SM_D13 SM_D14 SM_D15 SM_D16 SM_D17 SM_D18 SM_D19 SM_D20 SM_D21 SM_D22 SM_D23 SM_D24 SM_D25 SM_D26 SM_D27 SM_D28 SM_D29 SM_D30 SM_D31 A39 A38 A37 A36 A35 A34 A33 A32 B39 B38 B 37 B36 B 35 B34 B 33 B32 A 29 A28 A27 A26 A25 A24 A23 A22 B29 B28 B27 B26 B25 B24 B23 B22 D C SM_IRQ_N G37 SM_IRQ_N SM_BWAIT_N F35 SM_BWAIT_N SM_BUSY_N F34 SM_BUSY_N SM_DMARQ_N SM_IRQ_N SM_BWAIT_N SM_BUSY_N G39 SM_DMARQ_N SM_DMARQ_N J 2C SEAM-40-02.0-S-08-2-A-K J2E SEAM-40-02.0-S-08-2-A-K AUX_SDA AUX_SCL AUX_SA0_BOT AUX_SA1_BOT AUX_SA2_BOT D40 E40 E30 E31 SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_D8 SM_D9 SM_D10 SM_D11 SM_D12 SM_D13 SM_D14 SM_D15 SM_D16 SM_D17 SM_D18 SM_D19 SM_D20 SM_D21 SM_D22 SM_D23 SM_D24 SM_D25 SM_D26 SM_D27 SM_D28 SM_D29 SM_D30 SM_D31 MEMORY NA_IO[0..15] NA_IO[0..15] SM_BE0 SM_BE1 SM_BE2 SM_BE3 SM_PD_N FS_SI FS_SCK FS_WP_N FS_RESET J 2D SEAM-40-02.0-S-08-2-A-K SM_A0 SM_A1 SM_A2 SM_A3 SM_A4 SM_A5 SM_A6 SM_A7 SM_A8 SM_A9 SM_A10 SM_A11 SM_A12 SM_A13 SM_A14 SM_A15 SM_A16 SM_A17 SM_A18 SM_A19 SM_A20 SM_A21 SM_A22 SM_A23 SM_A24 SM_A25 SM_A26 SM_A27 SM_A28 SM_A29 SM_A30 SM_A31 G9 G8 H9 H8 H7 AUX_SDA AUX_SCL AUX_SA0 AUX_SA1 AUX_SA2 AUX_TDI AUX_TCK AUX_TMS G10 G11 H11 AUX_TDI AUX_TCK AUX_TMS AUX_STANDBY_N H 14 AUX_STANDBY_N AUX_POR_N AUX_HMR_N G13 H 13 AUX_POR_N AUX_HMR_N FAST SERIAL MEMORY INTERFACE FS_SI FS_SCK FS_WP_N FS_RESET G2 F1 G7 H1 FS_SI FS_SO FS_SCK FS_HOLD_N FS_WP_N FS_RESET_N FS_CS0_N FS_CS1_N FS_CS2_N FS_CS3_N H6 H5 H4 H3 FS_CS0_N FS_CS1_N FS_CS2_N FS_CS3_N B G1 H2 FS_SO FS_HOLD_N FS_SO FS_HOLD_N 2-wire CONFIG NAND MEMORY INTERFACE NA_CLE NA_ALE NA_RE_N NA_WE_N A NA_PRE NA_WP_N NA_CS0_N NA_CS1_N_BOT NA_CS2_N_BOT NA_CS3_N_BOT NA_CLE NA_ALE G28 H28 NA_CLE NA_ALE NA_RE_N NA_WE_N H25 G29 NA_RE_N NA_WE_N NA_PRE NA_WP_N H24 H 29 NA_PRE NA_WP_N NA_CS0_N NA_CS1_N_BOT NA_CS2_N_BOT NA_CS3_N_BOT H 27 G27 G26 H26 NA_CS0_N NA_CS1_N NA_CS2_N NA_CS3_N NA_IO0 NA_IO1 NA_IO2 NA_IO3 NA_IO4 NA_IO5 NA_IO6 NA_IO7 NA_IO8 NA_IO9 NA_IO10 NA_IO11 NA_IO12 NA_IO13 NA_IO14 NA_IO15 H23 H 22 H 21 H20 H19 H 18 H 17 H 16 G23 G22 G21 G20 G19 G18 G17 G16 NA_RY G25 NA_IO0 NA_IO1 NA_IO2 NA_IO3 NA_IO4 NA_IO5 NA_IO6 NA_IO7 NA_IO8 NA_IO9 NA_IO10 NA_IO11 NA_IO12 NA_IO13 NA_IO14 NA_IO15 JTAG AUX_TDI AUX_TCK AUX_TMS AUX_STANDBY_N AUX_POR_N AUX_HMR_N AUX_TDO H10 AUX_TDO Micron Technology Systems Engineering AUX_TDO via A. Pacinotti, 7 67051, Avezzano ITALY H12 BOTTOM CONNECTOR Document Number MICRON-PISMO2-00014 Revision 3.0 Size A-3 CONFIDENTIAL AND PROPRIETARY INFORMATION NA_RY The information contained herein is proprietary of Micron Technology. Any reproduction, in whole or in part, disclosure, or use of this drawing is expressly prohibited except as specified in writing by Micron Technology. NA_RY Date: Friday, July 14, 2006 5 A Title AUX_PRESENT 4 3 2 Sheet 2 1 of 5 Advance Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. NA_3V3 G40 G36 H36 H32 H31 G30 H30 G15 H15 G3 C1 G24 G12 A40 B40 A30 A31 AU X D39 E39 D38 E38 D37 E37 D36 E36 D35 E35 D34 E34 D33 E33 D32 E32 D29 E29 D28 E28 D27 E27 D26 E26 D25 E25 D24 E24 D23 E23 D22 E22 PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Vertical Space E19 D19 E14 E20 E2 E8 E3 D3 D7 E4 D14 D4 E7 E16 D6 D2 D SM_A0 SM_A1 SM_A2 SM_A3 SM_A4 SM_A5 SM_A6 SM_A7 SM_A8 SM_A9 SM_A10 SM_A11 SM_A12 SM_A13 SM_A14 SM_A15 SM_A16 SM_A17 SM_A18 SM_A19 SM_A20 SM_A21 SM_A22 SM_A23 SM_A24 SM_A25 SM_A26 SM_A27 SM_A28 SM_A29 SM_A30 SM_A31 POWER J2A SEAM-40-02.0-S-08-2-A-K DM_A[0..15] SM_D[0..31] J2F SEAM-40-02.0-S-08-2-A-K DM_DQM[0..3] DM_DQM[0..3] SM_D[0..31] J2B SEAM-40-02.0-S-08-2-A-K SM_A[0..31] PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Figure 8: Top Connector Schematic 4 5 3 1 2 SM_A[0..31] J1F SEAF-40-05.0-S-08-2-A-K DM_DQM[0..3] DM_DQM[0..3] DM_D[0..31] DM_D[0..31] AUX_3V3 DM_A0 DM_A1 DM_A2 DM_A3 DM_A4 DM_A5 DM_A6 DM_A7 DM_A8 DM_A9 DM_A10 DM_A11 DM_A12 DM_A13 DM_A14 DM_A15 DM_BA0 DM_BA1 DM_BA2 DM_BA0 DM_BA1 DM_BA2 E18 D18 C2 DM_BA0 DM_BA1 DM_BA2 DM_DQM0 DM_DQM1 DM_DQM2 DM_DQM3 D16 D8 D20 E6 DM_DQM0 DM_DQM1 DM_DQM2 DM_DQM3 DM_CLK0_DL DM_CLK0_DH DM_CKE0 E12 D12 E5 DM_CLK0_DL DM_CLK0_DH DM_CKE0 DM_CLK1_DL DM_CLK1_DH DM_CKE1 E10 D10 D5 DM_CLK1_DL DM_CLK1_DH DM_CKE1 DM_CLK0_DL DM_CLK0_DH DM_CKE0 C DM_CLK1_DL DM_CLK1_DH DM_CKE1 DM_RAS_N DM_CAS_N DM_WE_N DM_RAS_N DM_CAS_N DM_WE_N DM_CS1_N_BOT D17 E17 D15 DM_RAS_N DM_CAS_N DM_WE_N DM_CS1_N_BOT E15 DM_CS_FDBK D1 DM_CS0_N DM_CS1_N DM_RESET_N DM_RESET_N DM_ODT0 DM_ODT1 17 DM_ODT0 DM_ODT1 C3 DM_RESET_N C5 C4 DM_ODT0 DM_ODT1 DM_D0 DM_D1 DM_D2 DM_D3 DM_D4 DM_D5 DM_D6 DM_D7 DM_D8 DM_D9 DM_D10 DM_D11 DM_D12 DM_D13 DM_D14 DM_D15 DM_D16 DM_D17 DM_D18 DM_D19 DM_D20 DM_D21 DM_D22 DM_D23 DM_D24 DM_D25 DM_D26 DM_D27 DM_D28 DM_D29 DM_D30 DM_D31 B11 A11 B12 A12 B13 A13 A14 B14 A7 B7 A8 B8 A9 B9 B10 A10 A16 B16 B17 A17 B18 B19 A18 A19 B2 B3 A2 A3 B4 A4 A5 B5 DM_D0 DM_D1 DM_D2 DM_D3 DM_D4 DM_D5 DM_D6 DM_D7 DM_D8 DM_D9 DM_D10 DM_D11 DM_D12 DM_D13 DM_D14 DM_D15 DM_D16 DM_D17 DM_D18 DM_D19 DM_D20 DM_D21 DM_D22 DM_D23 DM_D24 DM_D25 DM_D26 DM_D27 DM_D28 DM_D29 DM_D30 DM_D31 DM_DQS0_DL DM_DQS0_DH B15 A15 DM_DQS0_DL DM_DQS0_DH DM_DQS1_DL DM_DQS1_DH B6 A6 DM_DQS1_DL DM_DQS1_DH DM_DQS2_DL DM_DQS2_DH B20 A20 DM_DQS2_DL DM_DQS2_DH DM_DQS3_DL DM_DQS3_DH B1 A1 DM_DQS3_DL DM_DQS3_DH DM_VREF C6 F13 F11 G14 AUX_V33_0 AUX_V33_1 AUX_V33_2 C37 C36 C35 C 34 C33 C 28 C27 C 26 C25 C 24 C23 C22 C40 C39 C38 SM_VIO_0 SM_VIO_1 SM_VIO_2 SM_VIO_3 SM_VIO_4 SM_VIO_5 SM_VIO_6 SM_VIO_7 SM_VIO_8 SM_V33_0 SM_V33_1 SM_V33_2 SM_V18_0 SM_V18_1 SM_V18_2 C19 C18 C14 C8 C12 C10 C9 C15 C 11 C7 C 20 C17 C16 C13 DM_VIO_0 DM_VIO_1 DM_VIO_2 DM_VIO_3 DM_VIO_4 DM_VIO_5 DM_VIO_6 DM_VIO_7 DM_VIO_8 DM_VIO_9 DM_VCC_0 DM_VCC_1 DM_VCC_2 DM_VCC_3 SM_3V3 SM_1V8 DM_POWER DM_POWER TP4 C40 + C41 + 10u 10U DM_DQS0_DL DM_DQS0_DH DM_DQS1_DL DM_DQS1_DH FS_VIO DM_DQS2_DL DM_DQS2_DH FS_3V3 Vref G5 G4 F3 G6 FS_1V8 DM_DQS3_DL DM_DQS3_DH NA_3V3 DM_POWER FS_VIO_0 FS_VIO_1 FS_V33_0 FS_V18_0 F26 F21 F16 F 27 F28 NA_1V8 R12 DNU0 DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU11 DNU12 DNU13 DNU14 DNU15 DNU16 DNU17 0 DNI R13 DM_CS0_N DM_CS_FDBK NA_1V8 TP1 0 + NA_VIO_0 NA_VIO_1 NA_VIO_2 NA_V33_0 NA_V18_0 STATIC MEMORY VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 DYNAMIC VSS25 MEMORY VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 FAST SERIAL VSS38 MEMORY VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 NAND F40 F39 F38 F37 F36 G35 G34 G33 G32 B31 D31 G31 B30 D30 F30 F29 F25 F24 F23 F22 A21 B21 C21 D21 E21 F20 F19 F18 F17 F15 F14 D13 E13 F12 D11 E11 F10 D9 E9 F9 F8 F7 F6 F5 F4 F2 E1 SM_BE0 SM_BE1 SM_BE2 SM_BE3 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 SM_CS0_N SM_CS1_N SM_CS2_N SM_CS3_N SM_WE_N SM_OE_N SM_LBA_N SM_WP_N SM_RESET_N SM_CRE_N NA_RE_N NA_WE_N NA_PRE NA_WP_N A NA_CS1_N_BOT NA_CS2_N_BOT NA_CS3_N_BOT NA_1V8 R14 0 DNI R15 NA_CS0_N G28 H28 NA_CLE NA_ALE NA_RE_N NA_WE_N H 25 G29 NA_RE_N NA_WE_N H 24 H29 NA_PRE NA_WP_N NA_PRE NA_WP_N H27 G27 G26 H 26 NA_CS0_N NA_CS1_N NA_CS2_N NA_CS3_N FS_SI FS_SCK FS_WP_N FS_RESET FS_CS0_N FS_CS1_N FS_CS2_N FS_CS3_N AUX NA_IO0 NA_IO1 NA_IO2 NA_IO3 NA_IO4 NA_IO5 NA_IO6 NA_IO7 NA_IO8 NA_IO9 NA_IO10 NA_IO11 NA_IO12 NA_IO13 NA_IO14 NA_IO15 H 23 H 22 H 21 H20 H 19 H 18 H 17 H16 G23 G22 G21 G20 G19 G18 G17 G16 NA_RY G25 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 C32 C31 C30 C29 SM_CLK0 SM_CLK1 SM_CLK2 SM_CLK3 SM_CS0_N SM_CS1_N SM_CS2_N SM_CS3_N H40 H39 H38 H 37 SM_CS0_N SM_CS1_N SM_CS2_N SM_CS3_N SM_WE_N SM_OE_N SM_LBA_N SM_WP_N SM_RESET_N SM_CRE_N F 32 F31 F33 H33 H34 G38 SM_WE_N SM_OE_N SM_LBA_N SM_WP_N SM_RESET_N SM_CRE_N SM_PD_N H35 SM_PD_N SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_D8 SM_D9 SM_D10 SM_D11 SM_D12 SM_D13 SM_D14 SM_D15 SM_D16 SM_D17 SM_D18 SM_D19 SM_D20 SM_D21 SM_D22 SM_D23 SM_D24 SM_D25 SM_D26 SM_D27 SM_D28 SM_D29 SM_D30 SM_D31 A39 A38 A37 A36 A35 A34 A33 A32 B39 B38 B37 B36 B35 B34 B33 B32 A29 A28 A27 A26 A25 A24 A23 A22 B29 B28 B27 B26 B25 B24 B23 B22 D C SM_IRQ_N G37 SM_IRQ_N SM_BWAIT_N F 35 SM_BWAIT_N SM_BUSY_N F34 SM_BUSY_N SM_DMARQ_N SM_IRQ_N SM_BWAIT_N SM_BUSY_N G39 SM_DMARQ_N SM_DMARQ_N J1C SEAF-40-05.0-S-08-2-A-K AUX_3V3 AUX_SDA AUX_SCL NA_CLE NA_ALE SM_BE0 SM_BE1 SM_BE2 SM_BE3 GND TP7 AUX_SDA AUX_SCL G9 G8 H9 H8 H7 AUX_SDA AUX_SCL AUX_SA0 AUX_SA1 AUX_SA2 AUX_TDI AUX_TCK AUX_TMS G10 G11 H11 AUX_TDI AUX_TCK AUX_TMS AUX_STANDBY_N H 14 AUX_STANDBY_N AUX_POR_N AUX_HMR_N G 13 H13 AUX_POR_N AUX_HMR_N NAND MEMORY INTERFACE NA_CLE NA_ALE D40 E40 E30 E31 SM_PD_N J1E SEAF-40-05.0-S-08-2-A-K NA_IO0 NA_IO1 NA_IO2 NA_IO3 NA_IO4 NA_IO5 NA_IO6 NA_IO7 NA_IO8 NA_IO9 NA_IO10 NA_IO11 NA_IO12 NA_IO13 NA_IO14 NA_IO15 SM_BE0 SM_BE1 SM_BE2 SM_BE3 SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_D8 SM_D9 SM_D10 SM_D11 SM_D12 SM_D13 SM_D14 SM_D15 SM_D16 SM_D17 SM_D18 SM_D19 SM_D20 SM_D21 SM_D22 SM_D23 SM_D24 SM_D25 SM_D26 SM_D27 SM_D28 SM_D29 SM_D30 SM_D31 C42 NA_IO[0..15] J1 D SEAF-40-05.0-S-08-2-A-K SM_A0 SM_A1 SM_A2 SM_A3 SM_A4 SM_A5 SM_A6 SM_A7 SM_A8 SM_A9 SM_A10 SM_A11 SM_A12 SM_A13 SM_A14 SM_A15 SM_A16 SM_A17 SM_A18 SM_A19 SM_A20 SM_A21 SM_A22 SM_A23 SM_A24 SM_A25 SM_A26 SM_A27 SM_A28 SM_A29 SM_A30 SM_A31 MEMORY 10 u NA_IO[0..15] D 39 E39 D 38 E38 D37 E37 D36 E36 D35 E35 D34 E34 D33 E33 D32 E32 D29 E29 D28 E28 D27 E27 D26 E26 D25 E25 D24 E24 D23 E23 D22 E22 AUX_SA0_BOT AUX_SA1_BOT B FAST SERIAL MEMORY INTERFACE FS_SI FS_SCK FS_WP_N FS_RESET G2 F1 G7 H1 FS_SI FS_SO FS_SCK FS_HOLD_N FS_WP_N FS_RESET_N FS_CS0_N FS_CS1_N FS_CS2_N FS_CS3_N H6 H5 H4 H3 FS_CS0_N FS_CS1_N FS_CS2_N FS_CS3_N FS_SO FS_HOLD_N G1 H2 2-wire CONFIG JTAG AUX_TDI AUX_TCK AUX_TMS AUX_STANDBY_N AUX_POR_N AUX_HMR_N AUX_TDO H10 AUX_TDO Micron Technology Systems Engineering AUX_TDO via A. Pacinotti, 7 67051, Avezzano ITALY A Title AUX_PRESENT H12 TOP CONNECTOR Document Number MICRON-PISMO2-00014 NA_RY Revision 3.0 Size A-3 NA_RY 0 CONFIDENTIAL AND PROPRIETARY INFORMATION The information contained herein is proprietary of Micron Technology. Any reproduction, in whole or in part, disclosure, or use of this drawing is expressly prohibited except as specified in writing by Micron Technology. Date: Friday, July 14, 2006 5 4 FS_SO FS_HOLD_N 3 2 Sheet 3 1 of 5 Advance Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. B G40 G36 H36 H32 H31 G30 H30 G15 H15 G3 C1 G24 G12 A40 B40 A30 A31 AU X SM_VIO J1G SEAF-40-05.0-S-08-2-A-K DNU SM_D[0..31] PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Vertical Space E19 D19 E14 E20 E2 E8 E3 D3 D7 E4 D14 D4 E7 E16 D6 D2 SM_A0 SM_A1 SM_A2 SM_A3 SM_A4 SM_A5 SM_A6 SM_A7 SM_A8 SM_A9 SM_A10 SM_A11 SM_A12 SM_A13 SM_A14 SM_A15 SM_A16 SM_A17 SM_A18 SM_A19 SM_A20 SM_A21 SM_A22 SM_A23 SM_A24 SM_A25 SM_A26 SM_A27 SM_A28 SM_A29 SM_A30 SM_A31 POWER J1A SEAF-40-05.0-S-08-2-A-K DYNAMIC MEMORY INTERFACE DM_A0 DM_A1 DM_A2 DM_A3 DM_A4 DM_A5 DM_A6 DM_A7 DM_A8 DM_A9 DM_A10 DM_A11 DM_A12 DM_A13 DM_A14 DM_A15 D SM_A[0..31] STATIC MEMORY INTERFACE DM_A[0..15] DM_A[0..15] SM_D[0..31] J1B SEAF-40-05.0-S-08-2-A-K 4 5 3 1 2 DM_D[0..31] NAND CAPS NA_1V8 DM_POWER NA_1V8 TERM_DM_DQS2_DH C51 R4 DM_DQS2_DH 33 DM_DQS2_DH C53 C52 RN4 N2 T2 Y7 AA6 100n 100n 100n 100n Vcc_1 Vcc_2 Vcc_3 Vcc_4 DM_A[0..15] VddQ_1 VddQ_2 VddQ_3 VddQ_4 VddQ_5 VddQ_6 VddQ_7 VddQ_8 VddQ_9 DM_A[0..15] B16 H21 J1 P21 Y14 AA11 AA17 U1 D Vdd_1 Vdd_2 Vdd_3 Vdd_4 Vdd_5 Vdd_6 Vdd_7 A3 A15 B5 F2 F21 L20 W21 AA14 AA19 C50 TERM_DM_D21 TERM_DM_D23 TERM_DM_D20 TERM_DM_D22 8 7 6 5 TERM_DM_D18 TERM_DM_D19 TERM_DM_D17 TERM_DM_D16 8 7 6 5 1 2 3 4 DM_D21 DM_D23 DM_D20 DM_D22 1 2 3 4 DM_D18 DM_D19 DM_D17 DM_D16 D 33 RN2 C H1 A4 A14 A18 DQM0 DQM1 DQM2 DQM3 TERM_DM_DQS3_DH TERM_DM_DQS1_DH TERM_DM_DQS0_DH TERM_DM_DQS2_DH C2 B8 B15 A19 DQS0 DQS1 DQS2 DQS3 DM_CAS_N DM_RAS_N DM_WE_N DM_CS0_N U20 V21 Y18 T21 DM_CKE0 Y15 AA12 18 NA_WE_N K1 WE_N NA_RE_N L2 RE NA_WP_N Y5 WP Y10 R/B AA8 CE 1k NA_RY NA_CS0_N NA_CLE AA10 CLE NA_ALE AA9 ALE A1 NA_1V8 R10 NA_WE_N NA_RE_N NA_WE_N NA_RE_N NA_WP_N NA_RY NA_CS0_N NA_CLE NA_ALE A Do Not Install 1k NA_WP_N NA_RY NA_CS0_N NA_CLE NA_ALE DM_CS0_N DM_WE_N DM_CAS_N DM_RAS_N DM_CKE0 DM_DQS0_DH DM_DQS1_DH DM_DQS2_DH DM_DQS3_DH NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC R11 1k DM_CS0_N DM_WE_N DM_CAS_N DM_RAS_N DM_CKE0 DM_DQS0_DH DM_DQS1_DH DM_DQS2_DH DM_DQS3_DH A2 A20 A21 B1 B2 B20 B21 Y20 Y21 AA20 Do Not Install A12 B13 33 TERM_DM_DQS0_DH TERM_DM_D7 TERM_DM_D6 TERM_DM_D4 TERM_DM_D5 8 7 6 5 TERM_DM_D2 TERM_DM_D3 TERM_DM_D0 TERM_DM_D1 8 7 6 5 TERM_DM_D15 TERM_DM_D14 TERM_DM_D12 TERM_DM_D13 8 7 6 5 TERM_DM_D10 TERM_DM_D11 TERM_DM_D8 TERM_DM_D9 8 7 6 5 1 2 3 4 DM_D7 DM_D6 DM_D4 DM_D5 1 2 3 4 DM_D2 DM_D3 DM_D0 DM_D1 1 2 3 4 DM_D15 DM_D14 DM_D12 DM_D13 1 2 3 4 DM_D10 DM_D11 DM_D8 DM_D9 RN3 RN6 DM_CLK0_DH 33 RN7 NA_IO0 NA_IO1 NA_IO2 NA_IO3 NA_IO4 NA_IO5 NA_IO6 NA_IO7 NA_IO8 NA_IO9 NA_IO10 NA_IO11 NA_IO12 NA_IO13 NA_IO14 NA_IO15 U2 U1 V2 V1 AA3 AA4 Y3 Y4 R1 T1 N1 P2 P1 M1 J2 K2 1n TERM_DM_DQS1_DH R8 DM_DQS1_DH 33 DM_DQS1_DH DM_CLK0_DL RN8 TERM_DM_D31 TERM_DM_D30 TERM_DM_D29 TERM_DM_D28 8 7 6 5 TERM_DM_D25 TERM_DM_D27 TERM_DM_D24 TERM_DM_D26 8 7 6 5 1 2 3 4 DM_D31 DM_D30 DM_D29 DM_D28 1 2 3 4 DM_D25 DM_D27 DM_D24 DM_D26 B 33 NA_IO[0..15] AA21 W1 W2 Y2 Y8 Y9 AA5 L1 Y1 AA1 AA2 33 C61 R6 49.9 NA_IO[0..15] C57 C22 C54 C55 C58 C59 100n 100n 100n 100n 100n 100n RN9 33 TERM_DM_DQS3_DH R16 33 DM_DQS3_DH DM_DQS3_DH DM_POWER MT29C1G12MABCACG C6 C5 C7 C8 C1 C2 C9 C3 C4 C10 C21 100n 100n 100n 100n 100n 100n 1 00 n 100n 100n 1 0 0n 100n Micron Technology Systems Engineering via A. Pacinotti, 7 67051, Avezzano ITALY DM_POWER A Title C17 C16 C18 C19 C14 C15 C13 C11 C12 C20 C23 C24 C56 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n Document Number MICRON-PISMO2-00014 Revision 3.0 Size A-3 CONFIDENTIAL AND PROPRIETARY INFORMATION The information contained herein is proprietary of Micron Technology. Any reproduction, in whole or in part, disclosure, or use of this drawing is expressly prohibited except as specified in writing by Micron Technology. Date: Friday, July 14, 2006 5 C 33 DM_BA0 DM_BA1 DM_BA0 DM_BA1 DM_DQS0_DH 33 DM_POWER NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 DM_DQS0_DH 33 RN5 R3 4 9. 9 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 R7 Mobile DDR + NAND PoP and EEPROM DM_CLK0_DL DM_CLK0_DH DM_CLK0_DL DM_CLK0_DH CLK CLK TERM_DM_D27 TERM_DM_D29 TERM_DM_D24 TERM_DM_D25 TERM_DM_D26 TERM_DM_D28 TERM_DM_D30 TERM_DM_D31 TERM_DM_D15 TERM_DM_D8 TERM_DM_D13 TERM_DM_D12 TERM_DM_D14 TERM_DM_D9 TERM_DM_D10 TERM_DM_D11 TERM_DM_D1 TERM_DM_D3 TERM_DM_D2 TERM_DM_D0 TERM_DM_D4 TERM_DM_D5 TERM_DM_D7 TERM_DM_D6 TERM_DM_D17 TERM_DM_D18 TERM_DM_D19 TERM_DM_D20 TERM_DM_D16 TERM_DM_D22 TERM_DM_D21 TERM_DM_D23 4 3 2 Sheet 4 1 of 5 Advance Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. B CKE TQ NAND Device NA_1V8 R9 CAS RAS WE_D CS E1 E2 G2 D1 G1 D2 B3 B4 B10 B6 A8 B9 A9 A5 B7 A6 A10 B11 B12 A11 A17 A16 B18 B17 C20 D20 C21 E20 B19 D21 G21 E21 VssN_1 VssN_2 VssN_3 VssN_4 DM_DQM3 DM_DQM1 DM_DQM0 DM_DQM2 DM_DQM[0..3] DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 M2 R2 Y6 AA7 BA0 BA1 0 1 Gb NAND & 512 Mb Mobile DDR SDRAM Multi Chip Package on Package AA18 V20 R5 Vss_1 Vss_2 Vss_3 Vss_4 Vss_5 Vss_6 Vss_7 DM_BA0 DM_BA1 mo-DDR Device PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Vertical Space A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 VssQ_1 VssQ_2 VssQ_3 VssQ_4 VssQ_5 VssQ_6 VssQ_7 VssQ_8 VssQ_9 DM_DQM[0..3] G20 K20 J20 J21 U21 R20 M21 M 20 N20 K21 Y16 N21 R21 AA15 A13 H2 H20 P20 Y11 Y17 AA13 DM_A0 DM_A1 DM_A2 DM_A3 DM_A4 DM_A5 DM_A6 DM_A7 DM_A8 DM_A9 DM_A10 DM_A11 DM_A12 DM_A13 A7 B14 C1 F1 F20 L21 W20 Y19 AA16 PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Figure 9: Mobile DDR + NAND PoP and EEPROM Schematic PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN Figure 10: EEPROM Schematic 4 5 3 1 2 D D SERIAL MEMORY (PD) AUX_3V3 NA_1V8 C C DNI 0805 C30 19 U9 AUX_SA0_BOT AUX_SA1_BOT AUX_SA2_BOT AUX_SA0_BOT AUX_SA1_BOT AUX_SA2_BOT 1 2 3 A0 A1 A2 4 VSS 0805 VCC 8 WP SCL SDA 7 6 5 100n AUX_SCL AUX_SDA C31 10 0 n AUX_SCL AUX_SDA 24xx64-I/ST B Micron Technology Systems Engineering via A. Pacinotti, 7 67051, Avezzano ITALY A A Title EEPROM Document Number MICRON-PISMO2-00014 Revision 3.0 Size A-3 CONFIDENTIAL AND PROPRIETARY INFORMATION The information contained herein is proprietary of Micron Technology. Any reproduction, in whole or in part, disclosure, or use of this drawing is expressly prohibited except as specified in writing by Micron Technology. Date: Friday, July 14, 2006 5 4 3 2 Sheet 5 1 of 5 Advance Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved. B PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Vertical Space R18 0 R17 0 Advance PISMO2-00014: Mobile DDR DRAM + NAND Flash PoP Appendix A Appendix A Figure 11: PISMO2-00014 Part Number Diagram PISMO2-00014-D12- C75-N1-A Micron Module Part Number Operating Temperature Range Blank = Commercial (0° to +70°C) IT = Industrial/Extended (–40° to +85°C) Mobile DDR DRAM Density PoP Package D12 = 512Mb A = 152-ball FBGA Mobile DDR DRAM Cycle Timing Table 9: C06 = 6ns @ CAS latency = 3 NAND Density C75 = 7.5ns @ CAS latency = 3 N1 = 1Gb Reference Documents Document Description Manufacturer Part Numbers PISMO2 specification 1Gb NAND data sheet 512Mb Mobile DDR DRAM data sheet 1 Gb NAND MCP PoP data sheet Serial EEPROM data sheet – Micron Micron Micron Microchip – MT29F1GxxABB MT46H32M16LF MT29C1G12MADCACG 24AA64-I/ST I2C Notes: 1. Micron data sheets can be downloaded from www.micron.com. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Advance: This data sheet contains initial descriptions of products still under development. PDF: 09005aef82885bd2/Source: 09005aef82885c14 PISMO2_00014_datasheet.fm - Rev. B 5/07 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2007 Micron Technology, Inc. All rights reserved.