Preliminary‡ 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Mobile LPDDR 168-Ball Package-on-Package (PoP) TI OMAP™ MT46HxxxMxxLxJG Features Options • Vdd/Vddq = 1.70–1.95V • Bidirectional data strobe per byte of data (DQS) • Internal, pipelined double data rate (DDR) architecture; 2 data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks (DM) for masking write data—one mask per byte • Programmable burst lengths (BL): 2, 4, 8, or 161 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Deep power-down (DPD) • STATUS READ REGISTER (SRR) supported2 • Selectable output drive strength • Clock stop capability • 64ms refresh • Vdd/Vddq – 1.8V/1.8V • Configuration – 128 Meg x 16 (32 Meg x 16 x 4 banks) – 64 Meg x 32 (16 Meg x 32 x 4 banks) – 64 Meg x 16 (16 Meg x 16 x 4 banks) – 32 Meg x 32 (8 Meg x 32 x 4 banks) • Device version – Single die, standard addressing – 2-die stack, standard addressing • Plastic “green” package – 168-ball VFBGA (12mm x 12mm) • Timing – cycle time – 5ns @ CL = 3 – 5.4ns @ CL = 3 – 6ns @ CL = 3 • Operating temperature range – Commercial (0° to +70°C) – Industrial (–40°C to +85°C) Table 1: Marking H 128M16 64M32 64M16 32M32 LF L2 JG -5 -54 -6 None IT Notes: 1. Contact factory for availability. 2. Contact factory for remapped SRR output. Configuration Addressing Architecture Configuration Refresh count Row addressing Column addressing 128 Meg x 16 64 Meg x 32 64 Meg x 16 32 Meg x 32 32 Meg x 16 x 4 banks 8K 16K (A[13:0]) 1K (A[9:0]) 16 Meg x 32 x 4 banks 8K 8K (A[12:0]) 1K (A[9:0]) 16 Meg x 16 x 4 banks 8K 16K (A[13:0]) 1K (A[9:0]) 8 Meg x 32 x 4 banks 8K 8K (A[12:0]) 1K (A[9:0]) PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Part Numbering Information - 168-Ball PoP Micron® 168-ball packaged LPDDR-SDRAM devices are available in several configurations. Figure 1: 168-Ball Part Number Chart MT 46 H 32M32 LF JG -6 IT :A Micron Technology Design Revision :A = First generation Product Family Operating Temperature 46 = LPDDR-SDRAM Blank = Commercial (0°C to +70°C) Operating Voltage IT = Industrial (–40°C to +85°C) H = 1.8V/1.8V Cycle Time 128 Meg x 16 -5 = 5ns tCK CL = 3 -54 = 5.4ns tCK CL = 3 64 Meg x 32 -6 = 6ns tCK CL = 3 Configuration 64 Meg x 16 Package Codes 32 Meg x 32 JG = 12mm x 12mm VFBGA “green” Device Version LF = Single die, standard addressing L2 = Dual die, standard addressing Table 2: 168-Ball Production Part Numbers Part Numbers MT46H32M32LFJG-5:A MT46H32M32LFJG-5 IT:A MT46H32M32LFJG-54:A MT46H32M32LFJG-54 IT:A MT46H32M32LFJG-6:A MT46H32M32LFJG-6 IT:A MT46H64M32L2JG-5:A MT46H64M32L2JG-5 IT:A MT46H64M32L2JG-54:A MT46H64M32L2JG-54 IT:A MT46H64M32L2JG-6:A MT46H64M32L2JG-6 IT:A LPDDR Product 1Gb DDR, x32, 200 MHz 1Gb DDR, x32, 200 MHz 1Gb DDR, x32, 185 MHz 1Gb DDR, x32, 185 MHz 1Gb DDR, x32, 166 MHz 1Gb DDR, x32, 166 MHz 2 x 1Gb DDR, x32, 200 MHz 2 x 1Gb DDR, x32, 200 MHz 2 x 1Gb DDR, x32, 185 MHz 2 x 1Gb DDR, x32, 185 MHz 2 x 1Gb DDR, x32, 166 MHz 2 x 1Gb DDR, x32, 166 MHz Physical Part Marking D9KFD D9KFC D9KVC D9KVD D9KNG D9KCK D9KDK D9KDG D9KDJ D9KVB D9KCX D9KCW Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,” at www.micron.com/csn. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum General Description The 1Gb Mobile LPDDR die contained within this package is a high-speed CMOS, dynamic random access memory containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as 16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits. Figure 2: Functional Block Diagram (64 Meg x 16) CKE CK# CK WE# CAS# RAS# Command decode CS# Control logic Bank 3 Bank 2 Bank 1 Refresh counter Standard mode register Extended mode register Bank 0 rowaddress latch and decoder Rowaddress MUX Bank 0 memory array Data 16 32 Read latch Sense amplifiers 16 MUX DRVRS 16 2 DQS generator DQ0– DQ15 Col 0 I/O gating DM mask logic 2 Address BA0, BA1 Address register 2 CK 32 Bank control logic DQS Input registers 2 2 2 2 16 16 16 16 Mask 32 Column decoder Columnaddress counter/ latch Write FIFO and drivers CK out CK in LDQS, UDQS 2 4 32 RCVRS 16 LDM, UDM Data CK 2 Col 0 1 PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Figure 3: Functional Block Diagram (32 Meg x 32) CKE CK# CK WE# CAS# RAS# Command decode CS# Control logic Bank 3 Bank 2 Bank 1 Refresh counter Standard mode register Extended mode register Bank 0 rowaddress latch and decoder Rowaddress MUX Bank 0 memory array Data 32 64 Read latch Sense amplifiers 32 MUX DRVRS 32 4 DQS generator DQ0– DQ31 Col 0 I/O gating DM mask logic 2 Address, BA0, BA1 Address register 2 CK 64 Bank control logic 4 DQS Input registers 64 Column decoder Columnaddress counter/ latch Write FIFO and drivers CK out CK in DQS0, DQS1, DQS2, DQS3 4 Mask 4 4 4 32 32 8 64 RCVRS 32 32 32 Data CK DM0, DM1, DM2, DM3 4 Col 0 1 PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Ball Assignments and Descriptions Figure 4: 168-Ball VFBGA (x32) Ball Assignments 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DQ21 DQ23 Vddq CK Vdd DQ9 DQ11 Vddq DQ13 DM1 Vddq DQ15 DM3 DQ25 DNU DNU A DQ20 DQ22 Vssq CK# Vss DQ8 DQ10 Vssq DQ12 DQS1 Vssq DQ14 DQS3 DQ24 DNU DNU B DQS0 Vssq Vddq C DQ7 DQ6 DQ26 DQ27 D E Vddq Vssq DQ28 DQ29 E F DQ5 DQ4 Vssq Vddq F G DQ3 DQ2 DQ30 DQ31 G H Vddq Vssq Vss Vdd H J DQ1 DQ0 CKE0 CKE1 J K Vdd Vss Vss WE# K L NC1 Vss CAS# RAS# L M NC NC CS0# CS1# M N NC NC A0 A1 N P NC1 Vss A2 A3 P R NC NC A4 A5 R T NC NC A6 A7 T U NC1 Vss A8 A9 U V NC NC A10 A11 V W NC NC A12 RFU W Y NC NC RFU Vdd Y AA NC1 Vss Vss Vdd AA AB DNU DNU INC NC Vss NC NC Vss NC NC NC NC Vss Vss NC NC NC NC NC Vss BA0 DNU DNU AB AC DNU DNU NC NC NC1 NC NC NC1 NC NC NC NC NC1 TQ NC NC NC NC NC NC BA1 DNU DNU AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 A DNU DNU DQ17 Vddq DQ19 DM2 Vddq B DNU DNU DQ16 Vssq DQ18 DQS2 Vssq C DM0 D 8 9 Top View – Ball Down Notes: LPDDR Supply Ground 1. Although not bonded to the die, these pins may be connected on the package substrate. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Figure 5: 168-Ball VFBGA (x16) Ball Assignments 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Vddq DQ10 DQ8 Vddq CK Vdd DQ6 DQ4 Vddq DQ2 LDM Vddq DQ0 DNU DNU DNU DNU A DQ11 DQ9 Vssq CK# Vss DQ7 DQ5 Vssq DQ3 LDQS Vssq DQ1 DNU DNU DNU DNU B DNU Vssq Vddq C DNU DNU DNU DNU D E Vddq Vssq DNU DNU E F DNU DNU Vssq Vddq F G DNU DNU DNU DNU G H Vddq Vssq Vss Vdd H J DNU DNU CKE0 CKE1 J K Vdd Vss Vss WE# K L NC1 Vss CAS# RAS# L M NC NC CS0# CS1# M N NC NC A0 A1 N P NC1 Vss A2 A3 P R NC NC A4 A5 R T NC NC A6 A7 T U NC1 Vss A8 A9 U V NC NC A10 A11 V W NC NC A12 A13 W Y NC NC RFU Vdd Y AA NC1 Vss Vss Vdd AA AB DNU DNU NC NC Vss NC NC Vss NC NC NC NC Vss Vss NC NC NC NC NC Vss BA0 DNU DNU AB AC DNU DNU NC NC NC1 NC NC NC1 NC NC NC NC NC1 TQ NC NC NC NC NC NC BA1 DNU DNU AC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 3 5 4 1 2 A DNU DNU DQ14 Vddq DQ12 B DNU DNU DQ15 C DNU D Vssq 6 UDM DQ13 UDQS 7 Vssq 8 Top View – Ball Down Notes: LPDDR Supply Ground 1. Although not bonded to the die, these pins may be connected together on the package substrate. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Table 3: x16/x32 LPDDR Ball Descriptions x16 Balls x32 Balls W23, W22, V23, V22, W22, V23, V22, U23, U23, U22, T23, T22, R23, U22, T23, T22, R23, R22, R22, P23, P22, N23, N22 P23, P22, N23, N22 Symbol Type Description A[13:0] (x16) Input Address inputs: Specify row/column addresses. Also used to load the mode registers. The maximum address is determined by density and configuration. Consult the product data sheet for the maximum address for a given density and configuration. Unused address pins become RFU1. Bank address inputs: Specifies one of the 4 banks. Column select: Specifies the command to execute. CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#. Clock enable: CKE0 is used for a single LPDDR product. CKE1 is used for dual LPDDR products and is considered RFU for single products. Chip select: CS0# is used for a single LPDDR product. CS1# is used for dual LPDDR products and is considered RFU for single products Data mask: Determines which bytes are written during WRITE operations. For x16 LPDDR, unused DM balls become DNU. A[12:0] (x32) AB21, AC21 AB21, AC21 BA0, BA1 Input L22 L22 CAS# Input A11, B11 A11, B11 CK, CK# J22, J23 J22, J23 CKE0, CKE1 Input M22, M23 M22, M23 CS0#, CS1# Input A17, A6 A20, A6, A17, C1 LDM, UDM (x16) Input L23 L23 DM[3:0] (x32) RAS# K23 K23 WE# B3, A3, B5, A5, B8, A8, G23, G22, E23, E22, D23, DQ[15:0] B9, A9, B13, A13, B14, D22, A21, B21, A9, B9, (x16) A14, B16, A16, B19, A19 A8, B8, A5, B5, A3, B3, A19, B19, A16, B16, A14, DQ[31:0] B14, A13, B13, D1, D2, (x32) F1, F2, G1, G2, J1, J2 B17, B6 B20, B6, B17, C2 LDQS, UDQS (x16) AC14 AC14 A12, H23, K1, Y23, AA23 A12, H23, K1, Y23, AA23 A4, A7, A10, A15, A18, A4, A7, A10, A15, A18, C23, E1, F23, H1 C23, E1, F23, H1 Notes: DQS[3:0] (x32) TQ Vdd Vddq Input Input Input/ output Input/ output Row select: Specifies the command to execute. Write enable: Specifies the command to execute. Data bus: Data inputs/outputs. DQ[31:16] are DNU for x16 LPDDR devices. Note: For dual-die devices, the I/O capacitance will be twice the value shown in the packaged data sheet. Data strobe: Coordinates read/write transfers of data; one DQS per DQ byte. Output Temperature sensor output: TQ HIGH when LPDDR TJ exceeds 85°C. Supply Vdd: LPDDR power supply. Supply Vddq: LPDDR I/O power supply. 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Table 4: Non-Device-Specific Ball Descriptions Shared Balls x16 x32 Symbol Type Description B12, H22, K2, K22, L2, P2, AA2, AA22, AB5, AB8, AB13, AB14, AB20 B12, H22, K2, K22, L2, P2, AA2, AA22, AB5, AB8, AB13, AB14, AB20 Vss Supply Symbol Type NC – No connect: Not internally connected. DNU – Do not use: Must be grounded or left floating. RFU1 – Reserved for future use. Vss: Shared ground. Miscellaneous Balls x16 x32 A20, A21, B20, B21, C1, L1, M1, M2, N1, N2, P1, C2, D1, D2, D22, D23, R1, R2, T1, T2, U1, V1, E22, E23, F1, F2, G1, G2, V2, W1, W2, Y1, Y2, G22, G23, J1, J2, L1, M1, AA1, AB3, AB4, AB6, M2, N1, N2, P1, R1, R2, AB7, AB9, AB10, AB11, T1, T2, U1, V1, V2, W1, AB12, AB15, AB16, W2, Y1, Y2, AA1, AB3, AB17, AB18, AB19, AC3, AB4, AB6, AB7, AB8, AC4, AC5, AC6, AC7, AB9, AB10, AB11, AB12, AC8, AC9, AC10, AC11, AB15, AB16, AB17, AC12, AC13, AC15, AB18, AB19, AC3, AC4, AC16, AC17, AC18, AC5, AC6, AC7, AC8, AC19, AC20 AC9, AC10, AC11, AC12, AC13, AC15, AC16, AC17, AC18, AC19, AC20 A1, A2, A22, A23, B1, A1, A2, A22, A23, B1, B2, B22, B23, AB1, AB2, B2, B22, B23, AB1, AB2, AB22, AB23, AC1, AC2, AB22, AB23, AC1, AC2, AC22, AC23 AC22, AC23 Y22 W23, Y22 Notes: Description 1. Balls marked RFU may or may not be connected internally. These balls should not be used. Contact factory for details. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Electrical Specifications Table 5: Absolute Maximum Ratings Parameters/Conditions Vdd, Vddq Supply voltage relative to Vss Voltage on any pin relative to Vss Storage temperature range Symbol Min Max Unit Vdd, Vddq Vin –1.0 2.4 V –0.5 2.4 or (Vddq + 0.3V), whichever is less +150 V –55 °C Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 6: Recommended Operating Conditions Parameters Supply voltage I/O supply voltage Operating temperature range PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 9 Symbol Min Typ Max Unit Vdd Vddq 1.70 1.70 –40 1.80 1.80 – 1.95 1.95 +85 V V °C Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Device Diagram Figure 6: 168-Ball VFBGA Functional Block Diagram CS# Vdd CK Vddq CK# DM LPDDR CKE RAS# DQ CAS# WE# DQS TQ Address, Vss BA0, BA1 PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN Vssq 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Package Dimensions Figure 7: 168-Ball VFBGA 0.6 ±0.05 Seating plane 0.08 A 168X Ø0.326 Dimensions apply to solder balls postreflow. Pre-reflow ball is Ø0.3 on Ø0.27 SMD ball pads. A Solder ball material: SAC105 (98.5% Sn, 1% Ag, 0.5% Cu) Substrate material: plastic laminate with OSP finish 12 ±0.15 Mold compound: epoxy novolac 6 ±0.08 Ball A1 ID 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Ball A1 ID 0.5 TYP 11 5.5 A B C D E F 6 G H J K L M N P R T U V W Y AA AB AC ±0.08 0.5 TYP 5.5 11 Notes: 12 ±0.15 0.9 MAX 1. All dimensions are in millimeters. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved. Preliminary 168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR SDRAM Addendum Revision History Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/09 • “Mobile LPDDR” on page 1: Changed title from “LPDDR-SDRAM” to “Mobile LPDDR.” • “General Description” on page 3: Deleted “SDRAM” from description. • Table 4, “Non-Device-Specific Ball Descriptions,” on page 8: Removed V2 from Vss x16 and x32 balls; divided table into shared balls and miscellaneous balls. Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/08 • Initial release. PDF: 09005aef833508fb/Source: 09005aef83350d72 ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2008 Micron Technology, Inc. All rights reserved.