4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM

Preliminary‡
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Features
TwinDie™ DDR3L SDRAM
MT41K1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks
MT41K512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks
Features
Options
• Configuration
– 64 Meg x 4 x 8 banks x 2 ranks
– 32 Meg x 8 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 78-ball FBGA
(9mm x 11.5mm x 1.2mm)
– 78-ball FBGA
(8mm x 11.5mm x 1.2mm)
• Timing – cycle time1
– 1.25ns @ CL = 11 (DDR3L-1600)
– 1.5ns @ CL = 9 (DDR3L-1333)
– 1.87ns @ CL = 7 (DDR3L-1066)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C ≤ TC ≤ 95°C)
• Revision
• Uses 2Gb Micron die
• Two ranks (includes dual CS#, ODT, CKE, and ZQ
balls)
• Each rank has eight internal banks for concurrent
operation
• VDD = VDDQ = +1.35V (1.283V to 1.45V), backward
compatible to VDD = VDDQ = +1.5V ±0.075V
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ball-out
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Description
The 4Gb (TwinDie™) DDR3L SDRAM (1.35V) uses
Micron’s 2Gb DDR3L SDRAM die (essentially two
ranks of the 2Gb DDR3L SDRAM). Refer to Micron’s
2Gb DDR3L SDRAM data sheet for the specifications
not included in this document. Specifications for base
part number MT41K512M4 correlate to TwinDie manufacturing part number MT41K1G4; specifications for
base part number MT41K256M8 correlate to TwinDie
manufacturing part number MT41K512M8.
Note:
Marking
1G4
512M8
THD
THV
-125
-15E
-187E
None
None
:D/:M
1. CL = CAS (READ) latency.
Table 1: Key Timing Parameters
Speed
Grade
Data Rate
(MT/s)
Target tRCD-tRP-CL
-125
1600
11-11-11
13.75
13.75
13.75
-15E
1333
9-9-9
13.5
13.5
13.5
-187E
1066
7-7-7
13.1
13.1
13.1
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DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
tRCD
1
(ns)
tRP
(ns)
tCL
(ns)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
1024 Meg x 4
512 Meg x 8
64 Meg x 4 x 8 banks x 2 ranks
32 Meg x 8 x 8 banks x 2 ranks
8K
8K
Row address
32K A[14:0]
32K A[14:0]
Bank address
8 BA[2:0]
8 BA[2:0]
2K A[11, 9:0]
1K A[9:0]
Column address
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA Ball Assignments (Top View)
A
1
2
3
VSS
VDD
VSS
VDDQ
4
5
6
7
8
9
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
B
C
D
VSSQ
E
VREFDQ
NF, DQ7 NF, DQ5 VDDQ
VDDQ NF, DQ4
F
ODT1
VSS
RAS#
CK
VSS
CKE1
ODT0
VDD
CAS#
CK#
VDD
CKE0
CS1#
CS0#
WE#
A10/AP
ZQ0
ZQ1
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
G
H
J
K
L
M
N
Note:
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DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
1. Dark balls (with ring) designate balls that differ from the monolithic versions.
3
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© 2010 Micron Technology, Inc. All rights reserved.
Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions
Symbol
Type
Description
A14, A13,
A12/BC#, A11,
A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = burst length (BL) of 8 or
no burst chop, LOW = burst chop (BC) of 4, burst chop).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All command, address, and control input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE[1:0]
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3L SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#[1:0]
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command
code.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to VREFDQ. DM has an optional use as TDQS on the x8.
ODT[1:0]
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3L SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver
is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤
0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
DQ[3:0]
I/O
Data input/output: Bidirectional data bus for x4 configuration. DQ[3:0] are referenced
to VREFDQ.
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions (Continued)
Symbol
Type
DQ[7:0]
I/O
Data input/output: Bidirectional data bus for x8 configuration. DQ[7:0] are referenced
to VREFDQ.
DQS, DQS#
I/O
Data strobe: DQS and DQS# are differential data strobes: Output with read data; edge
aligned with read data; input with write data; center-aligned with write data.
TDQS, TDQS#
I/O
Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,
DM is disabled, and the TDQS and TDQS# balls provide termination resistance.
VDD
Supply
Power supply: 1.35V (1.283V to 1.45V operational; compatible with 1.5V operation)
VDDQ
Supply
DQ power supply: 1.35V (1.283V to 1.45V operational; compatible with 1.5V operation). Isolated on the device for improved noise immunity.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained
at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation.
VSS
Supply
Ground.
Supply
DQ ground: Isolated on the device for improved noise immunity.
VSSQ
ZQ[1:0]
Description
Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
NC
–
No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
NF
–
No function: When configured as a x4 device, these balls are NF. When configured as a
x8 device, these balls are defined as TDQS#, DQ[7:4].
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DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Functional Description
Functional Description
The TwinDie DDR3L SDRAM is a high-speed, CMOS dynamic random access memory
device internally configured as two 8-bank DDR3L SDRAM devices.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
The DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O balls.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3L SDRAM input receiver. DQS is center-aligned with
data for WRITEs. The read data is transmitted by the DDR3L SDRAM and edge-aligned
to the data strobes.
Read and write accesses to the DDR3L SDRAM are burst oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which
is then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits (including CSn#, BAn, and An) registered coincident with the READ or
WRITE command are used to select the rank, bank, and starting column location for the
burst access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron monolithic DDR3L data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die
operation.
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 2: Functional Block Diagram (64 Meg x 4 x 8 Banks x 2 Ranks)
Rank 1
(64 Meg x 4 x 8 banks)
Rank 0
(64 Meg x 4 x 8 banks)
CS1#
CAS#
CKE1
RAS#
ODT1
WE#
CK
CK#
CS0#
CKE0
A[14:0],
BA[2:0]
ZQ1
ODT0
ZQ0
DQS, DQS#
DQ[3:0]
DM
Figure 3: Functional Block Diagram (32 Meg x 8 x 8 Banks x 2 Ranks)
Rank 1
(32 Meg x 8 x 8 banks)
Rank 0
(32 Meg x 8 x 8 banks)
CS1#
RAS#
CKE1
CAS#
ODT1
WE#
CK
CK#
CS0#
CKE0
A[14:0],
BA[2:0]
ZQ1
ODT0
ZQ0
DQS, DQS#
DQ[7:0]
DM/TDQS
TDQS#
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Electrical Specifications – Absolute Ratings
Electrical Specifications – Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 4: Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
Notes
VDD supply voltage relative to VSS
VDD
–0.4
1.975
V
1
VDD supply voltage relative to VSSQ
VDDQ
–0.4
1.975
V
Voltage on any ball relative to VSS
VIN, VOUT
–0.4
1.975
V
Input leakage current
Any input 0V ≤ VIN ≤ VDD,
VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
II
–4
4
µA
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
IVREF
–2
2
µA
2
TC
0
95
°C
3, 4
TSTG
–55
150
°C
Operating case temperature
Storage temperature
Notes:
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV.
2. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
3. MAX operating case temperature. TC is measured in the center of the package (see Figure 4 (page 9)).
4. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
Temperature and Thermal Impedance
It is imperative that the DDR3L SDRAM device’s temperature specifications, shown in
the following table, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances listed in Table 6 (page 9) apply to the current die
revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications,” prior to using the values listed in the
thermal impedance table. For designs that are expected to last several years and require
the flexibility to use several DRAM die shrinks, consider using final target theta values
(rather than existing values) to account for increased thermal impedances from the die
size reduction.
The DDR3L SDRAM device’s safe junction temperature range can be maintained when
the TC specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case
temperature specifications.
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Electrical Specifications – Absolute Ratings
Table 5: Thermal Characteristics
Notes 1–3 apply to entire table
Parameter
Operating temperature
Notes:
Symbol
Value
Units
TC
0 to 85
°C
0 to 95
°C
Notes
4
1. MAX operating case temperature TC is measured in the center of the package, as shown
below.
2. A thermal solution must be designed to ensure that the device does not exceed the maximum TC during operation.
3. Device functionality is not guaranteed if the device exceeds maximum TC during
operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate. The use of self refresh temperature (SRT) or automatic self refresh
(ASR), if available, must be enabled.
Figure 4: Temperature Test Point Location
Test point
Length (L)
0.5 (L)
0.5 (W)
Width (W)
Table 6: Thermal Impedance
Die Rev
Package
Substrate
Θ JA (°C/W)
Airflow =
0m/s
D
78-ball
2-layer
61.0
43.7
37.3
27.1
4-layer
44.5
35.3
31.5
23.2
M
78-ball
2-layer
TBD
TBD
TBD
TBD
4-layer
TBD
TBD
TBD
TBD
Note:
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Θ JA (°C/W)
Airflow =
1m/s
Θ JA (°C/W)
Airflow =
2m/s
Θ JB (°C/W)
Θ JC (°C/W)
Notes
2.8
1
TBD
1
1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
9
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Electrical Specifications – ICDD Parameters
Electrical Specifications – ICDD Parameters
Table 7: DDR3L ICDD Specifications and Conditions (Rev D)
Note 1 applies to the entire table
Combined
Symbol
Individual
Die Status
Bus
Width
-187E
-15E
Units
ICDD0
ICDD0 =
IDD0 + IDD2P0 + 5
x4, x8
92
102
mA
ICDD1
ICDD1 =
IDD1 + IDD2P0 + 5
x4, x8
112
117
mA
ICDD2P0 (slow exit)
ICDD2P0 =
IDD2P0 + IDD2P0
x4, x8
24
24
mA
ICDD2P1 (fast exit)
ICDD2P1 =
IDD2P1 + IDD2P0
x4, x8
37
42
mA
ICDD2Q
ICDD2Q =
IDD2Q + IDD2P0
x4, x8
42
47
mA
ICDD2N
ICDD2N =
IDD2N + IDD2P0
x4, x8
44
49
mA
ICDD2N T
ICDD2NT =
IDD2NT + IDD2P0
x4, x8
52
57
mA
ICDD3P
ICDD3P = IDD3P + IDD2P0
x4, x8
42
47
mA
ICDD3N
ICDD3N =
IDD3N + IDD2P0
x4, x8
47
52
mA
ICDD4R
ICDD4R =
IDD4R + IDD2P0 + 5
x4
142
162
mA
x8
157
177
ICDD4W
ICDD4W =
IDD4W + IDD2P0 + 5
x4
152
172
x8
162
182
ICDD5B
ICDD5B =
IDD5B + IDD2P0
x4, x8
202
212
mA
ICDD6
ICDD6 =
IDD6 + IDD6
x4, x8
24
24
mA
ICDD6ET
ICDD6ET =
IDD6ET + IDD6ET
x4, x8
30
30
mA
ICDD7
ICDD7 =
IDD7 + IDD2P0 + 5
x4, x8
352
402
mA
ICDD8
ICDD8 = 2 × IDD2P0 + 4
x4, x8
32
32
mA
Note:
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DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
mA
1. ICDD values reflect the combined current of both individual die. IDDx represents individual die values.
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Electrical Specifications – ICDD Parameters
Table 8: DDR3L ICDD Specifications and Conditions (Rev M)
Note 1 applies to the entire table
Combined
Symbol
Individual
Die Status
Bus
Width
-15E
-125
Units
ICDD0
ICDD0 =
IDD0 + IDD2P0
x4, x8
67
72
mA
ICDD1
ICDD1 =
IDD1 + IDD2P0
x4, x8
82
87
mA
ICDD2P0 (slow exit)
ICDD2P0 =
IDD2P0 + IDD2P0
x4, x8
24
24
mA
ICDD2P1 (fast exit)
ICDD2P1 =
IDD2P1 + IDD2P0
x4, x8
40
45
mA
ICDD2Q
ICDD2Q =
IDD2Q + IDD2P0
x4, x8
40
45
mA
ICDD2N
ICDD2N =
IDD2N + IDD2P0
x4, x8
42
47
mA
ICDD2N T
ICDD2NT =
IDD2NT + IDD2P0
x4, x8
47
52
mA
ICDD3P
ICDD3P = IDD3P + IDD2P0
x4, x8
54
59
mA
ICDD3N
ICDD3N =
IDD3N + IDD2P0
x4, x8
59
64
mA
ICDD4R
ICDD4RCDD4R =
IDD4R + IDD2P0
x4
122
137
mA
x8
137
152
ICDD4W
ICDD4W =
IDD4W + IDD2P0
x4
112
127
x8
122
137
ICDD5B
ICDD5B =
IDD5B + IDD2P0
x4, x8
197
202
mA
ICDD6
ICDD6 =
IDD6 + IDD6
x4, x8
24
24
mA
ICDD6ET
ICDD6ET =
IDD6ET + IDD6ET
x4, x8
30
30
mA
ICDD7
ICDD7 =
IDD7 + IDD2P0
x4, x8
217
232
mA
ICDD8
ICDD8 = 2 × IDD2P0 + 4
x4, x8
28
28
mA
Note:
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DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
mA
1. ICDD values reflect the combined current of both individual die. IDDx represents individual die values.
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Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Package Dimensions
Package Dimensions
Figure 5: 78-Ball FBGA (package code THD)
Seating
plane
0.12 A
0.85 ±0.1
A
78X Ø0.45
Solder ball
material: SAC305.
Dimensions apply
to solder balls postreflow on Ø0.33
NSMD ball pads.
Ball A1 ID
9 8
7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
9.6 CTR
11.5 ±0.15
H
J
K
L
M
0.8 TYP
N
0.8 TYP
1.2 MAX
6.4 CTR
0.25 MIN
9 ±0.15
Notes:
PDF: 09005aef8460911b
DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Preliminary
4Gb: x4, x8 1.35V TwinDie DDR3L SDRAM
Package Dimensions
Figure 6: 78-Ball FBGA (package code THV)
Seating
plane
0.12 A
0.85 ±0.1
A
78X Ø0.45
Solder ball
material: SAC305.
Dimensions apply
to solder balls postreflow on Ø0.33
NSMD ball pads.
8 ±0.15
9
8
7
3
2
Ball A1 ID
1
Ball A1 ID
A
B
C
D
0.8 TYP
E
F
9.6 CTR
G
11.5 ±0.15
H
J
K
L
M
N
0.8 TYP
1.2 MAX
6.4 CTR
Note:
0.25 MIN
1. All dimensions are in millimeters.
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Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
PDF: 09005aef8460911b
DDR3L_4Gb_1_35V_TwinDie.pdf - Rev. B 4/11 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.