2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features 1.55V DDR2 SDRAM FBDIMM MT18RTF25672FDZ – 2GB Features • • • • • • • • • Information in the 1.8V DDR2 FBDIMM data sheet is directly applicable to this 1.55V DDR2 FBDIMM, except where stated otherwise in this data sheet. 240-pin, fully buffered DIMM (FBDIMM) Very low-power DDR2 operation Component configuration: 256 Meg x 8 1.5V ≤ VDD ≤ 1.9V for DDR2 SDRAM 1.5V ≤ VDD ≤ 1.9V for advanced memory buffer (AMB) DRAM I/O VDD = 1.55V Backward compatible with systems designed for the standard (1.8V) FBDIMM Dual rank Halogen-free Figure 1: 240-Pin FBDIMM (MO-256 R/C B) Module height: 30.35mm (1.19in) Options • Package – 240-pin DIMM (halogen-free) • Frequency/CL1 – 3.0ns @ CL = 5 (DDR2-667) Functionality This 1.55V FBDIMM consumes less power than a standard 1.8V FBDIMM. However, it has the same timing and operating parameters as a standard FBDIMM. This enables backward compatibility with systems designed for use with standard FBDIMMs. Note: Marking Z -667 1. CL = CAS (READ) latency. Table 1: Key Timing Parameters Data Rate (MT/s) tRCD tRP tRC CL = 3 (ns) (ns) (ns) 553 400 15 15 55 553 400 15 15 55 Speed Grade Industry Nomenclature CL = 5 CL = 4 -667 PC2-5300 667 -53E PC2-4200 – PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Features Table 2: Addressing Parameter 2GB Refresh count 8K Device bank address 8 BA[2:0] Device page size per bank 1KB Device configuration 1Gb (256 Meg x 8) Row address 16K A[13:0] Column address 1K A[9:0] Module rank address 2 S#[1:0] Table 3: Part Numbers and Timing Parameters – 2GB Base device: MT47R128M8,1 1Gb DDR2 SDRAM Module Module Memory Clock/ Clock Cycles Part Number2 Density Configuration Bandwidth Data Rate (CL -tRCD -tRP) MT18RTF25672FDZ-667__ Notes: 2GB 256 Meg x 72 PC2-5300 3.0ns/667 MT/s 5-5-5 Link Transfer Rate 4.0 GT/s 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a four-place code (not shown) that designates component, AMB vendor, and PCB revisions. Consult factory for current revision codes. Example: MT18RTF25672FDZ-667H1D6. PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 4: Pin Assignments 240-Pin FBDIMM Front 240-Pin FBDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol PS9#1 121 VDD 151 SN3 181 92 VSS 122 VDD 152 SN3# 93 PS5 123 VDD 153 VSS PN10# 94 PS5# 124 VSS 154 65 VSS 95 VSS 125 VDD 66 PN11 96 PS6 126 VDD PN5 67 PN11# 97 PS6# 127 VDD PN5# 68 VSS 98 VSS 128 VSS 69 VSS 99 PS7 129 VCC 1 VDD 31 PN3 61 PN9# 91 2 VDD 32 PN3# 3 VDD 33 VSS 62 VSS 63 PN10 4 VSS 34 PN4 64 5 VDD 6 VDD 35 PN4# 36 VSS 7 VDD 8 VSS 37 38 9 VCC 39 VSS SS9#1 SN9# 211 182 VSS 212 VSS 183 SN10 213 SS5 SN4 184 SN10# 214 SS5# 155 SN4# 185 VSS 215 VSS 156 VSS 186 SN11 216 SS6 157 SN5 187 SN11# 217 SS6# 158 SN5# 188 VSS 218 VSS 159 VSS 189 VSS 219 SS7 10 VCC 40 PN131 70 PS0 100 PS7# 130 VCC 160 SN131 190 SS0 220 SS7# 11 VSS 41 PN13#1 71 PS0# 101 VSS 131 VSS 161 SN13#1 191 SS0# 221 VSS 12 VCC 42 VSS 72 VSS 102 PS8 132 VCC 162 VSS 192 VSS 222 SS8 13 VCC 43 VSS 73 PS1 103 PS8# 133 VCC 163 VSS 193 SS1 223 SS8# 14 VSS 44 DNU 74 PS1# 104 VSS 134 VSS 164 DNU 194 SS1# 224 VSS 15 VTT 45 DNU 75 VSS 105 DNU 135 VTT 165 DNU 195 VSS 225 DNU 16 DNU 46 VSS 76 PS2 106 DNU 136 VID0 166 VSS 196 SS2 226 DNU 17 RESET# 47 VSS 77 PS2# 107 VSS 137 M_TEST (DNU) 167 VSS 197 SS2# 227 VSS 18 VSS 48 PN121 78 VSS 108 VDD 138 VSS 168 SN121 198 VSS 228 SCK 19 DNU 49 PN12#1 79 PS3 109 VDD 139 DNU 169 SN12#1 199 SS3 229 SCK# 20 DNU 50 VSS 80 PS3# 110 VSS 140 DNU 170 VSS 200 SS3# 230 VSS 21 VSS 51 PN6 81 VSS 111 VDD 141 VSS 171 SN6 201 VSS 231 VDD 22 PN0 52 PN6# 82 PS4 112 VDD 142 SN0 172 SN6# 202 SS4 232 VDD 23 PN0# 53 VSS 83 PS4# 113 VDD 143 SN0# 173 VSS 203 SS4# 233 VDD 24 VSS 54 PN7 84 VSS 114 VSS 144 VSS 174 SN7 204 VSS 234 VSS 25 PN1 55 PN7# 85 VSS 115 VDD 145 SN1 175 SN7# 205 VSS 235 VDD 26 PN1# 56 VSS 86 DNU 116 VDD 146 SN1# 176 VSS 206 DNU 236 VDD 27 VSS 57 PN8 87 DNU 117 VTT 147 VSS 177 SN8 207 DNU 237 VTT 28 PN2 58 PN8# 88 VSS 118 SA2 148 SN2 178 SN8# 208 VSS 238 VDDSPD 29 PN2# 59 VSS 89 VSS 119 SDA 149 SN2# 179 VSS 209 VSS 239 SA0 PN9 90 PS91 210 SS91 240 SA1 Note: 1. The following signals are cyclical redundancy code (CRC) bits and thus appear out of the normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#, SN13/SN13#, PS9/PS9#, and SS9/ SS9#. 30 VSS 60 PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 120 SCL 150 3 VSS 180 SN9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Symbol Type Description PS[9:0] Input Primary southbound data, positive lines. PS#[9:0] Input Primary southbound data, negative lines. SCK Input System clock input, positive line. SCK# Input System clock input, negative line. SCL Input Serial presence-detect (SPD) clock input. SS[9:0] Input Secondary southbound data, positive lines. SS#[9:0] Input Secondary southbound data, negative lines. PN[13:0] Output Primary northbound data, positive lines. PN#[13:0] Output Primary northbound data, negative lines. SN[13:0] Output Secondary northbound data, positive lines. SN#[13:0] Output Secondary northbound data, negative lines. VID0 Output Voltage identification, connected to VSS. Indicates 1.5V DRAM present on module. SA[2:0] I/O SPD address inputs, also used to select the FBDIMM number in the AMB. SPD data input/output. SDA I/O RESET# Supply AMB reset signal. VCC Supply AMB core power and AMB channel interface power (1.5V). VDD Supply DRAM power and AMB DRAM I/O power (1.5V). VTT Supply DRAM clock, command, and address termination power (VDD/2). VDDSPD Supply SPD/AMB SMBus power. VSS Supply Ground. M_TEST – The M_TEST pin provides an external connection for testing the margin of VREF, which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and will be included in this specification at that time. DNU – Do not use. PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram CS1# CS0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQ DQ DQ DQ DQ DQ DQ DQ U1 CS# DQS DQS# DM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U19 DQS1 DQS1# DM5 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM DQ DQ DQ DQ DQ DQ DQ DQ U18 CS# DQS DQS# DM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U2 DQS2 DQS2# DM2 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM DQ DQ DQ DQ DQ DQ DQ DQ U3 CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U17 DQS3 DQS3# DM5 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U13 CS# DQS DQS# U12 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U7 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U8 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U11 DQS7 DQS7# DM7 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 U16 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# DM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U4 Out to controller PN[13:0] PN#[13:0] In from controller PS[9:0] PS#[9:0] Data input/output signals to DDR2 channel U1–U4, U6–U9, U10–U19 SN[13:0] SN#[13:0] SS[9:0] SS#[9:0] DQ[63:0] DQS[8:0] DQS#[8:0] A M B CB0–CB7 DM0–DM8 SCL SDA SA0 SA[2:0] RESET# A1 A2 VSS SA0 SA1 SA2 DM Out to adjacent FBDIMM Command, address, and clock signals to DDR2 channel U1–U4, U6–U9, U10–U19 CS0# CS1# CKE0 CKE1 SDA CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VTT Command, address, and clock line terminations: U20 SPD EEPROM A[15:0] BA[2:0] RAS#, CAS# WE#, ODT0 CS#[1:0] CKE[1:0] In from adjacent FBDIMM CK0, CK0# CK1, CK1# SCK, SCK# DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U10 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U9 DQS8 DQS8# DM8 U5 PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN U6 DM DQS6 DQS6# DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 WP A0 CS# DQS DQS# DQS5 DQS5# DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SCL DQ DQ DQ DQ DQ DQ DQ DQ VTT VDDSPD VTT 5 CS# DQS DQS# U14 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQS DQS# U15 Terminators SPD EEPROM, AMB VCC AMB VDD DDR2 SDRAM VREF ODT0, CK0, CK0# RAS#, CK1, CK1# CAS#, A[15:0] WE#, BA[2:0] DQ DQ DQ DQ DQ DQ DQ DQ VSS DDR2 SDRAM DDR2 SDRAM SPD EEPROM, AMB Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Absolute Maximum Ratings Parameter Symbol Min Max Units Notes Voltage on any signal pin relative to VSS VIN, VOUT –0.3 1.75 V 1 Voltage on VCC pin relative to VSS VCC –0.3 1.75 V Voltage on VDD pin relative to VSS VDD –0.5 2.3 V Voltage on VTT pin relative to VSS VTT –0.5 2.3 V DDR2 SDRAM device operating case temperature TC 0 95 °C 0 110 °C AMB device operating case temperature Notes: 2, 3 1. VIN should not be greater than VCC. 2. TC is specified at 95°C only when using 2X refresh timing (tREFI = 7.8µs at or below 85°C; tREFI = 3.9µs above 85°C); DDR2 SDRAM component data sheet. 3. See applicable DDR2 SDRAM component data sheet for tREFI and extended mode register settings. The tREFI parameter is used to specify the doubled refresh interval necessary to sustain <85°C operation. Table 7: Input DC Voltage and Operating Conditions Symbol Min Nom Max Units AMB supply voltage Parameter VCC 1.455 1.50 1.575 V Notes DDR2 SDRAM supply voltage VDD 1.5 1.55 1.9 V Termination voltage VTT 0.48 × VDD 0.50 × VDD 0.52 × VDD V EEPROM supply voltage VDDSPD 3.0 – 3.6 V 1 SPD input high (logic 1) voltage VIH(DC) 2.1 – VDDSPD V 2 SPD input low (logic 0) voltage VIL(DC) –0.6 – 0.8 V 2 RESET input high (logic 1) voltage VIH(DC) 1.0 – – V 3 RESET input low (logic 0) voltage VIL(DC) – – 0.5 V 2 Leakage current (RESET) IL –90 – 90 µA 3 Leakage current (link) IL –5 – 5 µA 4 Notes: 1. 2. 3. 4. Applies to AMB and SPD. Applies to SMBus and SPD bus signals. Applies to AMB CMOS signal RESET#. For all other AMB related DC parameters, refer to the high-speed differential link interface specification. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/ SPD. PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM IDD Specifications and Conditions IDD Specifications and Conditions Table 8: IDD Conditions Symbol Condition IDD_IDLE_0 Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IDLE_1 Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_ACTIVE_1 Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH IDD_ACTIVE_2 Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH; Command and address lines stable IDD_TRAINING Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_IBIST IBIST over all IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IDD_EI Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and CKE driven LOW Note: 1. Actual test conditions may vary from published JEDEC test conditions. Table 9: IDD Specifications – 2GB DDR2-667 Symbol IDD_IDLE_0 IDD_IDLE_1 IDD_ACTIVE_1 IDD_ACTIVE_2 IDD_TRAINING IDD_IBIST IDD_EI Units ICC 2600 3400 3900 3700 4000 4500 2500 A IDD 1150 1150 2178 1150 1150 1150 326 A 6.3 7.5 10.3 8 8.5 9.3 4.6 W Total power PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions Module Dimensions Figure 3: 240-Pin DDR2 FBDIMM Front view 5.1 (0.201) MAX 133.50 (5.256) 133.20 (5.244) 66.68 (2.63) TYP 0.595 (0.0234) R 0.75 (0.030) R 8X 0.5 (0.02) R (4X) 1.5 (0.059) R (4X) 2.0 (0.079) TYP U1 U2 U3 U4 U6 U5 U8 U7 17.3 (0.681) TYP 9.5 (0.374) TYP 2.60 (0.102) D (2X) 5.2 (0.205) TYP 1.25 (0.0492) TYP Pin 1 Detail A 1.0 (0.039) TYP 0.75 (0.03) R Pin 120 123.0 (4.843) TYP 9.9 (0.39) TYP (X4) 1.37 (0.054) 1.17 (0.046) 3.9 (0.153) TYP (x2) 0.80 (0.031) TYP 74.68 (2.94) TYP 5.48 (0.216) TYP 30.5 (1.201) 30.2 (1.189) U9 45° x 0.18 (0.0071) Back view 1.06 (0.042) 1.19 (0.047) 1.06 (0.042) Detail A 3.1 (0.122) TYP U10 U11 U12 U14 U13 U15 U16 U17 U18 U19 24.95 (0.982) TYP U20 3.05 (0.120) TYP 2.18 (0.086) TYP 120° (2X) Pin 240 5.0 (0.197) TYP 51.0 (2.01) TYP Pin 121 67.0 (2.638) TYP 66.68 (2.63) TYP 7.68 (0.302) MAX* Front view with heat spreader U1 U2 U3 U4 U6 U5 U8 U7 U9 1.37 (0.054) 1.17 (0.046) Back view with heat spreader U10 U11 U12 U14 U13 U15 U16 *Including clip radius 7.92 (0.312) MAX U17 U18 U19 U20 Notes: PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. 2GB (x72, DR) 240-Pin DDR2 SDRAM FBDIMM Module Dimensions 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef84281416 rtf18c256x72fdz.pdf - Rev. A 9/10 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.