512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Features DDR SDRAM UDIMM MT18VDDT6472A – 512MB1 MT18VDDT12872A – 1GB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 1: • 184-pin, unbuffered dual in-line memory module (UDIMM) • Fast data transfer rates: PC2100, PC2700, or PC3200 • 512MB (64 Meg x 72) and 1GB (128 Meg x 72) • Supports ECC error detection and correction • Vdd = VddQ = +2.5V (-40B: Vdd = VddQ = +2.6V) • Vddspd = +2.3V to +3.6V • 2.5V I/O (SSTL_2-compatible) • Internal, pipelined double data rate (DDR) 2n-prefetch architecture • Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture • Differential clock inputs (CK and CK#) • Multiple internal device banks for concurrent operation • Dual rank • Selectable burst lengths (BL): 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval • Serial presence-detect (SPD) with EEPROM • Selectable CAS latency (CL) for maximum compatibility • Gold edge contacts Table 1: 184-Pin UDIMM (MO-206 R/C B) Options Marking • Operating temperature2 – Commercial (0°C ≤ TA ≤ +70°C) None – Industrial (–40°C ≤ TA ≤ +85°C) I • Package – 184-pin DIMM (standard) G – 184-pin DIMM (Pb-free) Y • Memory clock, speed, CAS latency – 5.0ns (200 MHz), 400 MT/s, CL = 3.0 -40B – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335 – 7.5ns (133 MHz), 266 MT/s, CL = 2.01 -262 – 7.5ns (133 MHz), 266 MT/s, CL = 2.01 -26A – 7.5ns (133 MHz), 266 MT/s, CL = 2.51 -265 1. Not recommended for new designs. 2. Contact Micron for industrial temperature module offerings. Key Timing Parameters Data Rate (MT/s) tRCD tRP tRC (ns) (ns) (ns) Speed Grade Industry Nomenclature CL = 3 -40B PC3200 400 333 266 15 15 55 -335 PC2700 – 333 266 18 18 60 CL = 2.5 CL = 2 -262 PC2100 – 266 266 15 15 60 -26A PC2100 – 266 266 20 20 65 -265 PC2100 – 266 200 20 20 65 Notes: PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN Notes 1 tRCD and tRP 1. The values of for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Draft 9/ 9/ 2008 PCB height: 31.75mm (1.25in) 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Features Table 2: Addressing Parameter Refresh count 512MB 1GB 8K 8K Row address 8K (A0–A12) 8K (A0–A12) Device bank address 4 (BA0, BA1) 4 (BA0, BA1) Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) Column address 1K (A0–A9) 2K (A0–A9, A11) Module rank address 2 (S0#, S1#) 2 (S0#, S1#) Table 3: Part Numbers and Timing Parameters – 512MB Modules Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18VDDT6472AG-40B__ 512MB 64 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT18VDDT6472AY-40B__ 512MB 64 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT18VDDT6472AG-335__ 512MB 64 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 Part Number2 MT18VDDT6472AY-335__ 512MB 64 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT18VDDT6472AG-262__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT18VDDT6472AG-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT18VDDT6472AY-26A__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT18VDDT6472AG-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT18VDDT6472AY-265__ 512MB 64 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Table 4: Part Numbers and Timing Parameters – 1GB Modules Base device: MT46V64M8,1 512Mb DDR SDRAM Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18VDDT12872AG-40B__ 1GB 128 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT18VDDT12872AY-40B__ 1GB 128 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT18VDDT12872AG-335__ 1GB 128 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 Part Number2 MT18VDDT12872AY-335__ 1GB 128 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT18VDDT12872AG-262__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT18VDDT12872AG-265__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT18VDDT12872AY-265__ 1GB 128 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Notes: PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT12872AY-335F1. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Base device: MT46V32M8,1 256Mb DDR SDRAM 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Pin Assignments 184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 Vref 24 DQ17 47 DQS8 70 Vdd 93 Vss 116 Vss 139 Vss 162 DQ47 2 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DM8 163 NC 3 Vss 26 Vss 49 CB2 72 DQ48 95 DQ5 118 A11 141 A10 164 VddQ 4 DQ1 27 A9 50 Vss 73 DQ49 96 VddQ 119 DM2 142 CB6 165 DQ52 5 DQS0 28 DQ18 51 CB3 74 Vss 97 DM0 120 Vdd 143 VddQ 166 DQ53 6 DQ2 29 A7 52 BA1 75 CK2# 98 DQ6 121 DQ22 144 CB7 167 NC 7 Vdd 30 VddQ 53 DQ32 76 CK2 99 DQ7 122 A8 145 Vss 168 Vdd 8 DQ3 31 DQ19 54 VddQ 77 VddQ 100 VSS 123 DQ23 146 DQ36 169 DM6 9 NC 32 A5 55 DQ33 78 DQS6 101 NC 124 Vss 147 DQ37 170 DQ54 10 NC 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 Vdd 171 DQ55 11 Vss 34 Vss 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4 172 VddQ 12 DQ8 35 DQ25 58 Vss 81 Vss 104 VddQ 127 DQ29 150 DQ38 173 NC 13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 VddQ 151 DQ39 174 DQ60 14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3 152 Vss 175 DQ61 15 VddQ 38 Vdd 61 DQ40 84 DQ57 107 DM1 130 A3 153 DQ44 176 Vss 16 CK1 39 DQ26 62 VddQ 85 Vdd 108 Vdd 131 DQ30 154 RAS# 177 DM7 17 CK1# 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 Vss 155 DQ45 178 DQ62 18 Vss 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 VddQ 179 DQ63 19 DQ10 42 Vss 65 CAS# 88 DQ59 111 CKE1 134 CB4 157 S0# 180 VddQ 20 DQ11 43 A1 66 Vss 89 Vss 112 VddQ 135 CB5 158 S1# 181 SA0 21 CKE0 44 CB0 67 DQS5 90 NC 113 NC 136 VddQ 159 DM5 182 SA1 22 VddQ 45 CB1 68 DQ42 91 SDA 114 DQ20 137 CK0 160 Vss 183 SA2 23 DQ16 46 Vdd 69 DQ43 92 SCL 115 A12 138 CK0# 161 DQ46 184 Vddspd PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Table 5: 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Pin Descriptions Symbol Type Description A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. CK0, CK0#, CK1, CK1#, CK2, CK2# Input Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the internal clock, input buffers, and output drivers. DM0–DM8 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. S0#, S1# Input Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the SPD EDPROM address range on the I2C bus. SCL Input Serial clock for presence-detect: SCL is used to synchronize the presencedetect data transfer to and from the module. CB0–CB7 I/O Check bits. DQ0–DQ63 I/O Data input/output: Data bus. DQS0–DQS8 I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data. SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. Vdd/VddQ Supply Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V). Vddspd Supply SPD EEPROM power supply: +2.3V to +3.6V. Vref Supply SSTL_2 reference voltage (Vdd/2). Vss Supply Ground. NC – PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN No connect: These pins are not connected on the module. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Table 6: 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0 DQS4 DM0 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U18 DQ DQ DQ DQ DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ U9 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DQS5 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DQS2 Draft 9/ 9/ 2008 DM5 DM CS# DQS DQ DQ DQ DQ U17 DQ DQ DQ DQ DQS6 DM2 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ U3 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ DQS3 DQS7 DM3 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U4 DQ DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DQS8 DM8 BA0, BA1 A0–A12 CK0 CK0# U4–U6, U13–U15 CK2 CK2# U7–U12 U1–U3, U16–U18 U19 SCL SPD EEPROM WP A0 A1 A2 SDA VSS SA0 SA1 SA2 BA0, BA1: DDR SDRAM A0–A12: DDR SDRAM RAS# CAS# RAS#: DDR SDRAM WE# WE#: DDR SDRAM CKE0 CKE0: DDR SDRAM U1, U3, U5, U7, U9, U11, U13, U15, U17 CKE1 CKE1: DDR SDRAM U2, U4, U6, U8, U10, U12, U14, U16, U18 PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN CK1 CK1# CAS#: DDR SDRAM 5 Vddspd SPD EEPROM Vdd/VddQ DDR SDRAM Vref DDR SDRAM Vss DDR SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM General Description General Description The MT18VDDT6472A and MT18VDDT12872A are high-speed CMOS dynamic random access 512MB and 1GB memory modules are organized in a x72 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Vdd/VddQ Vin, Vout Ii Absolute Maximum Ratings Parameter Min Max Units Vdd/VddQ supply voltage relative to Vss –1.0 +3.6 V Voltage on any pin relative to Vss –0.5 +3.2 V Input leakage current; Any input 0V ≤ Vin ≤ Vdd; Address inputs, Vref input 0V ≤ Vin ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA test = 0V) S#, CKE –36 +36 µA CK, CK# –18 +18 –12 +12 DM –4 +4 Ioz Output leakage current; 0V ≤ Vout ≤ VddQ; DQ are disabled DQ, DQS –10 +10 µA Ta DRAM ambient operating temperature1 Commercial 0 +70 °C –40 +85 °C Industrial Notes: PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Table 7: 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades DDR components may exceed the listed module speed grades Module Speed Grade Component Speed Grade -40B -5B -335 -6 -262 -75E -26A -75Z -265 -75 Design Considerations Micron® memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Simulations 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Idd Specifications Table 9: Idd Specifications and Conditions – 512MB (Die Revision K) Parameter/Condition Symbol t t t t 1 -40B -335 Units Operating one bank active-precharge current: RC = RC (MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Idd0 936 846 mA Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); t CK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle Idd11 1,116 1,071 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idd2P2 72 72 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS, and DM Idd2F2 900 900 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Idd3P2 630 540 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Idd3N2 1,080 990 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); Iout = 0mA Idd4R1 1,656 1,476 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle Idd4W1 1,656 1,476 mA Idd52 2,880 2,880 mA Idd5A2 72 72 mA Auto refresh current tREFC = tRFC (MIN) tREFC = 15.625µs Self refresh current: CKE ≤ 0.2V Idd62 36 36 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Idd71 2,646 2,466 mA Notes: PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks are in Idd2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Values shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 10: Idd Specifications and Conditions – 512MB (All Other Die Revisions) Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Symbol -40B -335 -262 -26A/ -265 Units Operating one bank active-precharge current: tRC = tRC (MIN); t CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Idd01 1,251 1,161 1,161 1,116 mA Operating one bank active-read-precharge current: BL = 2; t RC = tRC (MIN); tCK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle Idd11 1,566 1,566 1,476 1,341 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idd2P2 72 72 72 72 mA Idle standby current: CS# = HIGH; All device banks idle; = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS, and DM Idd2F2 1,080 900 810 810 mA Active power-down standby current: One device bank active; Powerdown mode; tCK = tCK (MIN); CKE = LOW Idd3P2 720 540 450 450/ 540 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Idd3N2 1,260 1,080 900 900 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); Iout = 0mA Idd4R1 1,836 1,611 1,386 1,386 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle Idd4W1 1,791 1,611 1,386 1,386 mA Idd52 4,680 4,590 4,230 4,230/ 4,410 mA Idd5A2 108 108 108 108 mA Self refresh current: CKE ≤ 0.2V Idd62 72 72 72 72 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Idd71 4,266 3,726 3,186 3,186/ 3,321 mA Parameter/Condition Auto refresh current Notes: PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN tREFC = tRFC (MIN) tREFC = 7.8125µs 1. Value calculated as one module rank in this operating condition; all other module ranks are in Idd2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 tCK 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 11: Idd Specifications and Conditions – 1GB Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet -40B -335 -262 -26A/ -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Idd0 1 1,440 1,215 1,215 1,080 mA Operating one bank active-read-precharge current: BL = 2; RC = tRC (MIN); tCK = tCK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle Idd11 1,710 1,485 1,485 1,350 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW Idd2P2 90 90 90 90 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; Vin = Vref for DQ, DQS, and DM Idd2F2 990 810 810 720 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW Idd3P2 810 630 630 540 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Idd3N2 1,080 900 900 810 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA Idd4R1 1,755 1,530 1,530 1,350 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle Idd4W1 1,800 1,620 1,440 1,260 mA Idd52 6,210 5,220 5,220 5,040 mA Idd5A2 198 180 180 180 mA Self refresh current: CKE ≤ 0.2V Idd62 90 90 90 90 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Idd71 4,095 3,690 3,645 3,195 mA Parameter/Condition Symbol t t t tREFC Auto refresh current tREFC Notes: PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN = tRFC (MIN) = 7.8125µs 1. Value calculated as one module rank in this operating condition; all other module ranks are in Idd2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 t 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage Vddspd 2.3 3.6 V Input high voltage: Logic 1; All inputs Vih Vddspd × 0.7 Vddspd + 0.5 V Input low voltage: Logic 0; All inputs Vil –1.0 Vddspd × 0.3 V Output low voltage: Iout = 3mA Vol – 0.4 V Input leakage current: VIN = GND to Vdd Ili – 10 µA Output leakage current: VOUT = GND to Vdd Ilo – 10 µA Standby current: SCL = SDA = Vdd - 0.3V; All other inputs = Vss or Vdd Isb – 30 µA Power supply current: SCL clock frequency = 100 kHz Icc – 2.0 mA Table 13: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs tHD:DAT 200 – ns Data-out hold time SDA fall time tF – 300 ns 2 SDA rise time tR – 300 ns 2 tHD:DI 0 – µs tHD:STA 0.6 – µs Data-in hold time Start condition hold time Clock HIGH period tHIGH 0.6 – µs Clock LOW period tLOW 1.3 – µs fSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs Stop condition setup time tSU:STO 0.6 – µs tWRC – 5 ms SCL clock frequency WRITE cycle time Notes: 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/SPD. PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved Draft 9/ 9/ 2008 Table 12: 512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM UDIMM Module Dimensions Module Dimensions Figure 3: 184-Pin DDR UDIMM 4.0 (0.157) MAX Front view 133.50 (5.256) 133.20 (5.244) 2.0 (0.079) R (4X) U1 U2 U3 U4 U5 U6 U7 U8 U9 31.9 (1.256) 31.6 (1.244) 17.78 (0.70) TYP 2.5 (0.098) D (2X) 2.3 (0.091) TYP 0.90 (0.035) R Pin 1 2.21 (0.087) TYP 1.27 (0.05) TYP 1.0 (0.039) TYP 1.37 (0.054) 1.17 (0.046) Pin 92 6.35 (0.25) TYP 1.02 (0.04) TYP Back view U19 U10 U11 U12 U13 U14 U15 U16 U17 U18 10.0 (0.394) TYP Pin 93 Pin 184 49.53 (1.95) TYP 3.8 (0.15) TYP 64.77 (2.55) TYP 73.41 (2.89) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80814e61/Source: 09005aef807f8acb DD18C64_128x72A.fm - Rev. D 9/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. Draft 9/ 9/ 2008 120.65 (4.75) TYP