Circuit Note CN-0239 Devices Connected/Referenced 3 5MHz to 4400 MHz, Wideband ADF4351 Synthesizer with Integrated VCO ADL5801 10 MHz to 6 GHz, Wideband Active Mixer Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0239. Broadband 6 GHz Active Mixer with a Glueless Local Oscillator Interface This circuit offers an optimum solution that is attractive in wideband applications that require frequency conversion to higher or lower frequencies. The two-chip circuit covers a broad LO frequency range from 35 MHz to 4400 MHz. The LO interface is simple and glueless, eliminating the need for a balun, matching network, and LO buffer. In addition, the mixer bias adjust function allows optimization of IP3, noise figure, and supply current based on the application requirements or on the size of the input signal. EVALUATION AND DESIGN SUPPORT Circuit Evaluation Boards ADL5801 Evaluation Board (ADL5801-EVALZ) ADF4351 Evaluation Board (EVAL-ADF4351EB1Z) Design and Integration Files Schematics, Layout Files, Bill of Materials CIRCUIT FUNCTION AND BENEFITS The circuit shown in Figure 1 is a 10 MHz to 6 GHz wideband active mixer with a direct interface to a frequency synthesizerbased low phase noise local oscillator (LO). RF INPUT Mini-Circuits TCM1-63AX+ 3.3V C8 1nF C9 1nF RFIP RFIN 5V (L2) 50Ω C5 RFOUTA+ (L3) 50Ω ADF4351 LOIP 1nF C4 RFOUTA– 5V LOIN 1nF LO INPUT IFON ADL5801 WIDEBAND ACTIVE MIXER 10147-001 WIDE BAND SYNTHESIZER Mini-Circuits TC4-1W+ IF OUTPUT 4:1 IFOP Figure 1. Broadband Interface Between ADF4351 PLL with Integrated VCO and ADL5801 Broadband Active Mixer (Simplified Schematic Showing Only Interface Details) Rev. 0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. CN-0239 Circuit Note The ADL5801 is a high linearity, double balanced, active mixer with an integrated LO buffer amplifier that supports RF frequencies from 10 MHz to 6000 MHz. The mixer has a bias adjust feature to optimize the input linearity, noise figure and dc operating current. The circuit shown in Figure 1 has a simple LO interface for applications that require broadband up or down conversion. The interface provides coverage for RF frequencies ranging from 35 MHz to 4400 MHz. The PLL-mixer interface described above exhibits excellent broadband performance as shown in Figure 3 and Figure 4. The circuit maintains an input IP3 of more than 25 dBm at frequencies below 3500 MHz, and 23 dBm up to 4400 MHz. The circuit exhibits conversion gain of more than −0.7 dB and noise figure less than 12.2 dB across the operating frequency band. The ADF4351 PLL has a differential LO output interface, and the ADL5801 is optimized for differential LO drive. Differential interfaces provide common-mode noise rejection and cancellation of even order harmonics. Normally, pull-up bias inductors are recommended at the output port of the ADF4351. This solution delivers higher output power but limits the frequency range of the device. The standard evaluation board is equipped with two 7.5 nH pull-up inductors, which is optimal for frequencies above 500 MHz. In the Figure 1 circuit, the bias inductors are replaced with two-50 Ω pull-up resistors to reduce the frequency dependence of the output interface. This change results in lower power delivered at the output; however, the ADL5801 can tolerate this limitation since the device is specified to operate at LO drive levels as low as −10 dBm. Figure 2 is a comparison of the output power delivered by the device with resistive and inductive pull-up networks. 7.5nH PULL-UP INDUCTORS 5 0 50Ω PULL-UP RESISTORS PRF = −10dBm, PLO = 0dBm IIP3: 1MHz TONE SPACING BETWEEN CHANNELS IIP2: 15MHz TONE SPACING BETWEEN CHANNELS 60 50 INPUT IP2 40 INPUT IP3 30 20 10 CONVERSION GAIN 0 -10 0 500 1000 1500 2000 2500 3000 3500 4000 RF FREQUENCY (MHz) Figure 3. Conversion Gain, Input IP2, Input IP3 vs. RF Frequency 20 18 fIF = 153MHz, fLO: 188MHz TO 4400MHz (HIGH SIDE LO) PRF = −10dBm, PLO = 0dBm 16 VSET = 3.6V 14 12 VSET = 2.0V 10 8 6 4 –5 2 –10 0 500 –15 1500 2500 3500 RF FREQUENCY (MHz) –20 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) 3500 4000 4500 10147-002 Figure 4. Noise Figure vs. RF Frequency Figure 2. Comparison of the Power Level at the Output of the ADF4351 with Resistive and Inductive Pull-up Networks Rev. 0 | Page 2 of 6 4500 10147-004 OUTPUT POWER LEVEL (dBm) fIF = 153 MHz, fLO: 188MHz TO 4400MHz (HIGH SIDE LO) 70 NOISE FIGURE (dB) 10 80 10147-003 The ADF4351 is a wideband fractional-N and integer-N phaselocked loop PLL that covers frequencies from 35 MHz to 4400 MHz. The device has an integrated voltage controlled oscillator (VCO) with a fundamental frequency range from 2200 MHz to 4400 MHz. Multi-octave operation is achieved through the use of a bank of frequency dividers. The resistive pull-up network presents a nominal differential impedance of 100 Ω at the output, and the differential input impedance of the LO port of the ADL5801 is 50 Ω. The impedance mismatch in the LO path of the mixer does not degrade the circuit performance. However, it is suggested that the length of the traces connecting the devices be kept as short as possible to minimize effects of the impedance mismatch. GAIN, IIP3, IIP2 (dB, dBm) CIRCUIT DESCRIPTION Circuit Note CN-0239 The power consumed by the circuit depends on the frequency of operation and the mixer’s bias point. The ADF4351 activates a combination of sections in its divider network to generate output frequencies that span multiple octaves. This combination dictates the power consumption of the PLL. For example, when the PLL is programmed to output a frequency of 35 MHz, the device activates all six divider networks and consumes 132 mA of current. This point represents the worst-case power consumption point for the device. Similarly, the bias level of the ADL5801, which can be used to adjust IP3 and noise figure, determines the power consumed by the mixer. The VSET pin is used to adjust the bias level of the device. Figure 5 and Figure 6 show the dc current, input IP3, and noise figure performance of the mixer as a function of the VSET voltage. GAIN = 900MHz GAIN = 1900MHz IPOS = 900MHz IPOS = 1900MHz 0.16 CIRCUIT EVALUATION AND TEST 0.14 1.5 0.12 1.0 0.10 0.5 0.08 0 0.06 Table 1 and Table 2 list components modified on the evaluation boards to implement this applications circuit. –0.5 0.04 Table 1. Component Modifications on EVAL-ADF4351EB1Z –1.0 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY CURRENT (A) 2.0 0.02 5.0 10147-005 GAIN (dB) 2.5 The interface discussed above is applicable to other PLLs with an integrated VCO and differential outputs such as the ADF4350 or the ADF4360 family of products. The ADF4350, which operates from 135 MHz to 4.4 GHz is pin-compatible with the ADF4351 and exhibits a slightly higher noise figure. The ADF4360 family of integer-N PLLs with integrated VCO is a good fit for applications that require a fixed or narrow range of LO frequencies. These devices help to reduce power consumed by the circuit at the expense of higher phase noise. For applications that require more than one output mixer, the ADL5801 can be replaced with the ADL5802, which is a dual channel active mixer. The circuit described was implemented using the standard evaluation boards for ADF4351 (EVAL-ADF4351EB1Z) and ADL5801 (ADL5801-EVALZ).The ADF4351 evaluation board kit includes a reference crystal oscillator, control software and the programming interface cable required to operate the device. The control software provides options to set the output frequency, power level, reference frequency, and variety of other features. 0.18 3.0 COMMON VARIATIONS VSET (V) Placeholder L2, L3 L1, L4 Default Value 7.5 nH 1.9 nH New Value 50 Ω 0Ω 25 18 20 16 15 14 10 12 INPUT IP3 = 900MHz INPUT IP3 = 1900MHz NF = 900MHz NF = 1900MHz 5 Table 2. Component Modifications on ADL5801-EVALZ Placeholder T2/T4/T7 C4, C5 NOISE FIGURE (dB) 20 8 2.0 2.5 3.0 3.5 4.0 4.5 VSET (V) 5.0 New Value 0Ω 1 nF Figure 8 shows a block diagram of the test setup. The output of the PLL and the LO port of the mixer were bridged using a coaxial thru connector for evaluation. Figure 7 shows a photo of the two connected evaluation boards. The following is a list of equipment used to evaluate the circuit. 10 0 Default Value Mini-Circuits TCM1-1-13M+ 100 pF Test 10147-006 INPUT IP3 (dBm) Figure 5. Power Conversion Gain and Supply Current vs. VSET 30 Figure 6. Input IP3 and Noise Figure vs. VSET The VSET level is directly proportional to the dc operating current and input IP3, while the noise figure is inversely proportional to the VSET voltage. The mixer exhibits the best linearity at a VSET voltage of 3.6 V. At a mixer bias level of 3.6 V and the worst-case power consumption point for the PLL (all dividers on), the circuit consumes approximately 1.14 W. Rev. 0 | Page 3 of 6 CN-0239 Circuit Note Equipment Needed • Windows® XP, Windows® Vista (32-bit), or Windows® 7 (32-bit) PC with USB port • ADF4351 evaluation board (EVAL-ADF4351EB1Z) • ADL5801 evaluation board (ADL5801-EVALZ) • RF Signal generator (Rohde & Schwarz SMT06 or equivalent) • Spectrum analyzer (Rohde & Schwarz FSEA30 or equivalent) • Power supplies: Agilent E3631 or equivalent The ADL5801 was biased with a VSET voltage of 3.6 V using an external power supply. This external bias connection can be replaced with an on-board connection routed through the supply pin using a resistive divider network. Populating placeholder R10 and leaving R7 and R8 open enables this resistive divider network. Table 3 provides the value of R10 required to achieve desired mixer bias level. For additional information, refer to the “RF Voltage-to-Current (V-to-I) Converter” section in the ADL5801 datasheet. Table 3. Suggested Values of R10 to Achieve the Desired Mixer Bias Level (IPOS is the CorrespondingADL5801 Supply Current) R10 (Ω) 226 562 568 659 665 694 760 768 1000 1100 1150 1200 1300 1400 1500 1600 1700 1800 1900 2000 2300 5900 Open EVAL-ADF4351EB1Z: +5.5 V ADL5801-EVALZ: +5 V (VPOS), +3.6V (VSET) VSET (V) 4.5 4.01 4 3.9 3.89 3.85 3.8 3.79 3.6 3.53 3.5 3.47 3.4 3.35 3.3 3.26 3.21 3.17 3.14 3.1 3 2.5 2.03 IPOS (mA) 160 146 145 142 142 142 139 139 133 131 130 129 127 126 124 122 121 120 119 118 114 98 82 10147-007 To demonstrate the circuit’s capability to support RF frequencies from 35 MHz to 4400 MHz, the device was operated in a high side LO configuration with an IF frequency of 153 MHz. Figure 7. Board Setup Used to Interface the ADF4351 with the ADL5801 The control software was used to program the desired LO frequency and the output power. Figure 9 is a sample screen shot of the software configuration used to drive the ADF4351. See UG-435 User Guide, Evaluation Board for the ADF4351 Fractional-N PLL Frequency Synthesizer and UG-476 User Guide, PLL Software Installation Guide for further information on setting up the ADF4351. Rev. 0 | Page 4 of 6 Circuit Note CN-0239 SIGNAL GENERATOR (EVAL-ADF4351EB1Z) RF OUTA– VSUPPLY +5.5V ADL5801 EVALUATION BOARD (ADL5801-EVALZ) IFOP LOIN VPOS +5.0V VSET SPECTRUM ANALYZER +3.6V AGILENT E3631 POWER SUPPLY Figure 8. Circuit Evaluation Test Setup Block Diagram 10147-009 PC CONTROLLER RFIN LOIP 10147-008 RF OUTA+ USB ADF4351 EVALUATION BOARD Figure 9. Screenshot of the Software Configuration Used to Drive the ADF4351 Rev. 0 | Page 5 of 6 CN-0239 Circuit Note LEARN MORE Data Sheets and Evaluation Boards CN-0239 Design Support Package: http://www.analog.com/CN0239-DesignSupport ADF4351 Data Sheet and Evaluation Board ADL5801 Data Sheet and Evaluation Board UG-435 User Guide, Evaluation Board for the ADF4351 Fractional-N PLL Frequency Synthesizer. REVISION HISTORY UG-476 User Guide, PLL Software Installation Guide. 8/13—Revision 0: Initial Version ADIsimRF Design Tool ADIsimPLL Design Tool MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of “AGND” and “DGND”, Analog Devices. MT-086 Tutorial, Fundamentals of Phase Locked Loops (PLLs), Analog Devices. MT-101 Tutorial, Decoupling Techniques, Analog Devices. AN-30 Application Note, Ask the Application Engineer—PLL Synthesizers, Analog Devices (Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN10147-0-8/13(0) Rev. 0 | Page 6 of 6