AN-1253 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Layout Considerations for Digital Power Management (ADP1046A) By Subodh Madiwale INTRODUCTION Capacitive Coupling The ADP1046A is a digital power controller. It is a secondary side controller featuring several analog-to-digital converters (ADCs) with different data conversion rates. It also has integrated I2C communication, analog comparators, and digital compensation. For such complicated mixed signal devices where several input and output functions are present in a small 5 mm × 5 mm area, layout is crucial, and proper care must be taken to avoid layout hazards. Noise from capacitive coupling is introduced when the signal traces are routed close to each other. Whenever a trace is routed close to another with high frequency dv/dt changes, noise is capacitively coupled due to stray capacitances between the two traces. This type of noise is modeled as a current source with high input impedance and affects low impedance nodes. Rerouting the signal traces is the only option available to reduce noise without adding external filtering components. It is better to address layout issues from the beginning to avoid complications and failures at a later stage in the design cycle or, much worse, in the field. This application note provides critical layout guidelines to avoid noise coupling as well as proper grounding techniques for the ADP1046A. Inductive Coupling MODES OF NOISE COUPLING AND HOW TO MINIMIZE THEM Radiation Noise is predominantly a high frequency phenomenon. In the case of a switching power supply, high frequency denotes any frequency above 100 kHz where the higher order harmonics of significant amplitude can be as high as 1 MHz to 10 MHz. A low frequency noise is generally not considered detrimental to the proper functioning of the circuit and is characterized in the order of a few hertz (Hz), for example, the output ripple of the boost power factor correction stage. In an electromagnetic circuit, there are four main causes of noise injection: common impedance coupling, capacitive coupling, inductive coupling, and radiation. Common Impedance Coupling Noise from common impedance coupling is introduced when the return trace of one loop connects to the trace of another loop and a common path is shared for the signal. For example, if one loop contains a high frequency (HF) signal (a noisy switching waveform), the other is a low frequency signal (quiet VDD signal), and both loops share the same return, noise can very easily be injected into the low frequency (LF) path due to the sharing of the common return. The voltage drop caused by the HF signal on the shared impedance is also seen by the LF loop. A star connection is the safest way to avoid this type of noise. Inductive coupling can be considered the opposite of capacitive coupling. Mutual inductance is the coupling mechanism for this type of noise. Reducing the loop area of high di/dt traces is crucial to reduce noise pickup. Noise from radiation is at very high frequencies (above 30 MHz). The switching nodes of a power supply where high di/dt transitions occur act as antennas, radiating noise, and can affect far fields and remote parts of the circuit. Using a six-frame Faraday shield or reducing the antenna effect is the best option (reducing copper area at noisy nodes). PLACEMENT OF THE ADP1046A The ADP1046A is a secondary side controller. It must be placed in a location that is close to the output because the majority of the ADCs for sensing output voltage and current, as well as the PWM outputs that control the synchronous rectifiers, are present at the secondary side. However, the IC also provides PWM pulses for driving power switches placed on the primary side of the power supply. It also monitors and provides protection for primary signals, such as primary current. Therefore, it cannot be placed too far away from the MOSFET drivers and the primary current sense transformer. In a power supply layout, the switching elements (for example, MOSFETs, IGBTs) and their respective gate drivers must be close together. Placement of the ADP1046A should be done in a manner that does not degrade the PWM outputs or the sensing/ measuring of the current and output voltages. For prototyping and bench testing, it is highly recommended that the user lay out the ADP1046A on a small daughter card and connect it to the power board using external connectors (see the PRD1274). This layout allows easy monitoring of signals because the pins of the ADP1046A are easily accessible on the daughter card. Rev. 0 | Page 1 of 8 AN-1253 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Power Traces (VDD and VCORE Pins) .....................................5 Modes of Noise Coupling and How to Minimize Them ............. 1 Decoupling Capacitors .................................................................5 Placement of the ADP1046A .......................................................... 1 OUTA to OUTD, SR1, and SR2 PWM Outputs .......................6 Revision History ............................................................................... 2 GATE Pin .......................................................................................6 ADP1046A Layout and Grounding ............................................... 3 RTD Pin ..........................................................................................6 Location of PGND........................................................................ 4 PGOOD1, PGOOD2, and FLAGIN Pins ...................................7 VS3 and CS2 Differential Sensing .............................................. 4 SHAREo and SHAREi Pins ..........................................................7 VS1, VS2, and VS3− Sensing....................................................... 4 SDA and SCL Pins (I2C Clock and Data) ...................................7 RES Pin .......................................................................................... 4 Clearance and Creepage Requirements......................................7 CS1 Pin........................................................................................... 4 Conclusion .....................................................................................7 ACSNS Pin .................................................................................... 5 References.......................................................................................7 PSON Pin....................................................................................... 5 REVISION HISTORY 8/13—Revision 0: Initial Version Rev. 0 | Page 2 of 8 Application Note AN-1253 PGND 0R VS31 J20 J18 CS2R38 & R39 are not populated for low-side current sensing R26 & R16 are not populated for high-side current sensing CS2+ C12 0.1u 2 2 R16 4.99k C19 1nF 25V 2RSHUNT1 GATE AGND 3 ORFET R39 5.5k 3 Q15 DMN5L06K 1 VS2 R26 4.99k 1R Layout engineers who prefer to use separate DGND planes must ensure that the AGND and DGND planes do not overlap because the analog and digital noise can easily couple from one ground plane to another. Instead, the AGND and DGND planes should be connected at a single point, and the planes must be separated by at least 3 mm to 6 mm using a 0 Ω resistor. This layout eliminates any ground bouncing and provides the IC with a clean ground reference. J18 & J20 for remote sensing 1 TP38 VS3- TP37 VS3+ C65 10uF 25V VS3+ AGND PGND J4 VOUT- 1 1 In mixed signal systems, the first step is to separate the analog and digital signals to reduce interference. Noise in the digital side can couple with the analog circuitry and severely interfere with the signal integrity. Grounding is very important in mixed signal systems and can be the major source of radiated noise in systems where several multipoint grounds are present. In the case of a power supply using the ADP1046A, the system has three grounds: the power ground (PGND), the analog ground (AGND), and the digital ground (DGND). The proper grounding technique for the ADP1046A is to place a ceramic capacitor (330 nF/X7R) from VCORE to DGND. DGND must be connected to AGND with a star connection. An AGND plane can be created on the second layer of the PCB to prevent noise caused by the high speed ADCs and other digital circuitry from appearing on the analog side. A ground plane acts as a Faraday shield and terminates the noise signal to ground. 11732-003 J3 VOUT+ ADP1046A LAYOUT AND GROUNDING 2 R38 5.5k C8 1000uF 16V R58 10K Q11 1 OUT V+ 2 4 1 3 10uH 10A SR1/SR2 VSS C23 0.1uF D15 2 1 1 SMAZ16 D6 C13 1uF 2 2 D7 1N4148 1 R11 500 R35 12K 2 1 2 1 6 7 8 TRANSFORMER PRIMARY 2 T7 3 4 5 11732-001 2 1 Q10 3 3 Figure 1. ADP1046A Daughter Card Layout Figure 3. Typical PSU Secondary Side with Synchronous Rectifiers 11732-002 The exposed pad of the IC must be connected to AGND. VCORE is referenced to DGND and VDD is referenced to AGND. All signals referenced to AGND and DGND must be connected to their respective grounds with vias to the second layer. Additionally, PGND and AGND must be tied together at a single point with a 0 Ω resistor (see Figure 2). The return point of the synchronous rectifier drivers must be tied to VSS (see Figure 3) to minimize any inductance along its path. Figure 2. Single Point Connection Between PGND and AGND Using 0 Ω Rev. 0 | Page 3 of 8 AN-1253 Application Note Instead of following general guidelines, it is necessary to understand how a signal traces its path back to the source and then decide how to keep this loop area small. LOCATION OF PGND The location of PGND must be selected as the return point of the load (see Figure 3). VS3 AND CS2 DIFFERENTIAL SENSING RES PIN Connect a 10 kΩ/0.1% resistor from the RES pin to AGND with a via close to the IC. The tolerance of the internal clock frequency is directly proportional to the accuracy of the RES pin resistor and, therefore, a 0.1% resistor is recommended. 11732-004 11732-006 VS3± and CS2± are the two differential inputs of the ADP1046A. The recommended trace width is 15 mils to 20 mils. superior noise cancellation at lower frequencies due to their internal oversampling architecture. However, the traces for VS1 and VS2 must still be routed as far as possible from any dv/dt or di/dt traces or nodes that have high transients present on them. Figure 4. Parallel Traces of CS2+ and CS2− From Sense Resistor The layout of these traces is not as critical as the layout of other signal traces because the same common-mode noise is seen across both the pins by virtue of differential sensing. VS3− is connected to PGND. The level shifting resistors for CS2 must be kept close to the IC (preferably on a daughter card if a daughter card is used). It is recommended that the traces for the differential VS3± inputs be run parallel to each other. 11732-005 It is recommended that a 100 nF/X7R capacitor be placed between VS3− and AGND to reduce common-mode noise. The recommended location of this capacitor is on a daughter card close to the IC rather than on the PCB. Figure 5. VS3+ and VS3− Traces VS1, VS2, AND VS3− SENSING VS1, VS2, and VS3− must be referenced to PGND. The ADCs connected at the output of the PSU are generally far from the switching nodes of a power supply. The only way they are affected is due to the switching ripple. The ADP1046A uses sigma-delta (Σ-Δ) ADCs at 1.6 MHz and 25 MHz, which have Figure 6. RES Pin, R20 = 10 kΩ CS1 PIN The CS1 pin (referenced to PGND), which monitors the primary current, has a fast and accurate form of protection. An internal comparator provides fast overcurrent protection (OCP), and this analog signal must be routed away from the MOSFET drivers or PWMs that have high frequency pulses. A 1 nF capacitor is recommended to be placed between the CS1 pin and PGND, as shown in Figure 8. The primary current is sensed by converting it into a voltage across a termination resistor on the secondary side of the current transformer (CT). The trace from the CT secondary to the CS1 pin is long due to the placement of the IC. Placing the termination resistor close to the CT automatically degrades the voltage across the trace (but the loop area is shorter and inductive noise is suppressed). A damping resistor of much higher value can be placed across the secondary side of the CT to shorten the loop, and the termination resistor can be placed as close to the CS1 pin as possible. There is no signal degradation due to the signal being a current signal. Due to the distance from the primary to the CS1 pin, the recommended trace width is 30 mils. Because the absolute maximum rating of the CS1 pin is 3.3 V (cycle by cycle OCP limit at 1.2 V), it is recommended that a 2.5 V Zener diode be connected in parallel with the termination resistor. An additional diode with low forward voltage drop can also be placed in parallel to prevent the pin from being pulled to less than −0.3 V. Rev. 0 | Page 4 of 8 Application Note PRIMARY SIDE OF CURRENT TRANSFORMER D8 IN4148 1 2 T3 1 2 It is best, when possible, to shorten the length of the power traces rather than increasing their width to reduce the inductance. CS1 R13 22kΩ 2.5V ZENER 20Ω C32 1nF 11732-007 4 AN-1253 3 PGND Preferably, the ground plane should be directly below the power traces so that the return path is shortened (loop is small). Figure 7. Typical Circuit for Primary Current Sensing with 1 nF Placed Close to the IC (Preferably on Daughter Card) C15 1000pF 8 CS1 PGND 11732-008 7 CS1 PGND Figure 8. CS1 Filtering Capacitor Placed Close to the Pins of the IC ACSNS PIN 1 DECOUPLING CAPACITORS R55 100Ω The use of bypass or decoupling capacitors is a common and proven technique for reducing noise on a pin. The supply pins, VDD and VCORE, are especially prone to noise because they are low impedance nodes. The recommended capacitor values for VDD and VCORE are 4.7 µF and 300 nF, respectively (X7R). Additionally, note that inductive noise can severely affect these pins, and the capacitor must be placed very close to the pin with minimal loop area. R57 27kΩ SWITCH NODE C35 2.2nF ACSNS PGND 11732-009 R58 1kΩ 11732-010 Figure 9. Typical Application Circuit for Line Feedforward Figure 12. 330 nF Capacitor Connected Close to VCORE and DGND Figure 10. ACSNS Trace from Switch Node VDD PSON PIN VCORE PSON is referenced to AGND. A 1 nF capacitor is recommended from PSON to AGND. 27 26 330nF ADP1046A DGND POWER TRACES (VDD AND VCORE PINS) AGND The VDD pin of the ADP1046A has a maximum input voltage of 3.6 V (typically 3.3 V), and the digital core 2.5 V is fed through an internal regulator. Although the IC consumes ~20 mA, the power traces to the VDD pin must be as short as possible. This is done to avoid any degradation due to the inductance of the trace that may cause noise on the rail. Rev. 0 | Page 5 of 8 FROM 3.3V LDO PAD 4.7µF 25 2 33 AGND 11732-013 D10 Figure 11. Power VDD Trace 11732-012 2 11732-011 The ACSNS pin is referenced to PGND. The pickup point for ACSNS is the switching node on the secondary side of the power transformer. This pin is used to detect the presence of switching (short D10 and R55, and open C25) or for line feedforward. Figure 13. Small Loop Areas for Bypass Capacitors on VDD and VCORE AN-1253 Application Note 11732-014 OUTA TO OUTD, SR1, AND SR2 PWM OUTPUTS GATE PIN The GATE pin (referenced to AGND) is a totem pole output (configurable polarity using the GUI) without any pull-up resistor. The GATE pin provides the signal for turning on/off the OrFET for reverse current protection. This trace must be kept as short as possible and routed away from the synchronous driver switch nodes. RTD PIN The RTD pin sources a constant current and is an analog signal. This signal is difficult to route because the power transistors are the parts under the greatest thermal stress. Do not terminate the thermistor with a via to the AGND plane; instead, use a dedicated trace back to the AGND pin. The recommended trace width is 30 mils. The 16.5 kΩ in parallel with the thermistor allows the ADP1046A to read the temperature in °C. 11732-015 The PWM traces are the controlling signals of a PSU, and because they contain high frequency information, it is best to keep the traces short to avoid degradation due to trace inductance and spikes. It is critical to choose the proper location of the ADP1046A initially to make sure that these critical signals are not compromised. Figure 15 shows a noise-affected PWM pulse due to improper layout that can be detrimental to the overall functionality of the system. Figure 16. SR1 and SR2 Parallel Running Traces Separated by 15 mils to SR Driver ADP1046A RTD 28 100kΩ THERMISTOR Figure 15. Noise-Affected PWM Pulse (2 V/DIV) AGND 2 11732-017 The SR driver must be referenced to the true floating output of the PSU, that is, the return of the transformer (VSS in Figure 3) and not to PGND. This is important because SR drivers are typically powered from the output rail (for 12 V applications or from an auxiliary power supply). This prevents the return path from including the current sense resistor. In addition, such placement of the driver IC ensures that the complete gate-source drive capability of the driver IC appears across the gate-source terminals of the FET with minimal loop area. 16.5kΩ AGND Figure 17. Correct: Dedicated Trace to AGND ADP1046A RTD 28 100kΩ THERMISTOR AGND 16.5kΩ 2 AGND AGND 11732-018 All the PWM outputs (OUTA to OUTD, SR1, SR2, and OUTAUX) are referenced to AGND. Like the differential traces, the PWM and SR traces must also be run parallel to each other (recommended trace width of 15 mils), and the spacing must be kept uniform to ensure a constant differential impedance to avoid crosstalk (capacitive coupling) and signal integrity. The spacing between traces should be equal to or greater than the trace width. 11732-016 Figure 14. OUTA to OUTD Traces to MOSFET Drivers Figure 18. Incorrect: Thermistor Terminated to AGND Through AGND Plane Rev. 0 | Page 6 of 8 Application Note AN-1253 PGOOD1, PGOOD2, AND FLAGIN PINS 11732-022 PGOOD1, PGOOD 2, and FLAGIN are all referenced to AGND. PGOOD1 and PGOOD2 are small signal traces for visual monitoring through LEDs. They should be routed after all the other important traces are finalized. FLAGIN can be routed along with the PGOOD signals. Figure 22. Example of I2C Communication Traces CLEARANCE AND CREEPAGE REQUIREMENTS SHAREo AND SHAREi PINS The ADP1046A is located on the secondary (isolated) side of the power supply. The primary signals (OUTx and CS1) are fed either to an isolated driver or to a current transformer (CT). These components by themselves are designed to meet the required creepage and clearance isolation requirements. Additional safety requirements are not required while routing. The SHAREo and SHAREi pins are open drain. The pull-up resistors (2.2 kΩ) for analog and digital current sharing must be kept close to the IC. 3.3V R33 2.2kΩ SHAREo PGOOD1 PGOOD2 FLAGIN R15 2.2kΩ CONCLUSION R14 2.2kΩ 24 Using the autorouting feature may not produce the optimal layout, but other tools that layout programs provide, such as a transmission line calculator and router checks, can be useful as a final check. SHAREi 23 SHAREo 22 PGOOD1 21 Identify the sources of noise, type of noise, and effective coupling method, and separate analog and digital signals. PGOOD2 20 FLAGIN 11732-019 SHAREi R32 2.2kΩ Proper routing can eliminate the need for external shielding. It is better to minimize the noise at the source than to use corrective measures to fix layout issues later. Figure 19. Pull-Up Resistors Close to IC 11732-020 Use small loop areas and avoid routing through high dv/dt lines. The recommended trace widths can be scaled for high power density power supplies in the case of modules (dc-to-dc bricks). Use the recommended resistor values (RES pin) and capacitor values (VDD and VCORE pins). Figure 20. Pull-Up Resistors Close to IC Long traces can act as antennas; therefore, terminate to AGND plane wherever possible (except for RTD traces) SDA AND SCL PINS (I2C CLOCK AND DATA) The SDA and SCL pins are referenced to AGND. Because SDA and SCL are communication lines, extra effort must be taken to route them so that the shortest possible length is achieved to eliminate noise pickup from surrounding traces (long traces act as antennas). It is recommended that these traces be surrounded by the ground plane. In addition, a filtering circuit (see Figure 21) is used to prevent communication errors. A minimum trace width of 30 mils is good practice. REFERENCES Intel Corporation. High Speed USB Platform Design Guidelines, Rev. 1.0, 2000-01. Kester, Walt. MT-022. ADC Architectures III: Sigma-Delta ADC Basics. Analog Devices, Inc., 2009. Maniktala, Sanjaya. Switching Power Supplies A to Z. Burlington: Newnes, 2006. 3 3.3V 2 SCL R68 2.2kΩ C44 33pF C36 33pF R71 100Ω C42 33pF D22 BAW56 C43 33pF 3.3V SCL SDA AGND 2 2.2kΩ 1 3.3V R64 3 SDA J10 1 2 3 4 R70 100Ω AGND COM1 11732-021 1 D21 BAV70 Figure 21. Filtering Circuit for I2C Communication Rev. 0 | Page 7 of 8 AN-1253 Application Note NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN11732-0-8/13(0) Rev. 0 | Page 8 of 8