Freescale Semiconductor Users Guide Documentation Number: KT34712UG Rev. 4.0, 1/2009 Using the 3.0 A 1.0 MHz Fully Integrated DDR Switch-Mode Power Supply (KIT34712EPEVBE) 1 Introduction This User’s Guide will help the designer get better acquainted with the 34712 IC and Evaluation board. It contains a procedure to configure each block of the 34712 in a practical way, which is based on a working Evaluation Board designed by Freescale (KIT34712EPEVBE). 2 34712 Specification The 34712 is a highly integrated, space-efficient, low cost, single synchronous buck-switching regulator with integrated N-channel power MOSFETs. It is a high performance point-of-load (PoL) power supply with the ability to track an external reference voltage. Its high efficient 3.0 A sink and source capability combined with its voltage tracking/sequencing ability and tight output regulation, makes it ideal to provide the termination voltage (VTT) for modern data buses such as Double-Data-Rate (DDR) memory buses. It also provides a buffered output reference voltage (VREF) to the memory chipset © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. Contents 1 2 3 4 5 6 7 8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 34712 Specification. . . . . . . . . . . . . . . . . . . . . 1 Application Diagram . . . . . . . . . . . . . . . . . . . . 2 Board’s Specifications . . . . . . . . . . . . . . . . . . 2 Component Selection for 34712 Eval Board. 3 Layout Design . . . . . . . . . . . . . . . . . . . . . . . . 10 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application Diagram 3 Application Diagram Figure 1. Application diagram for 34712 4 Board’s Specifications The Board was designed to have an operating range defined by: PVIN_MIN = 3.0 V PVIN_MAX = 6.0 V VOUT_MIN = 0.7 V VOUT_MAX = 1.35 V IOUT_MIN = -3.0A IOUT_MAX = 3A Using the 34712, Rev. 4.0 2 Freescale Semiconductor Component Selection for 34712 Eval Board 5 Component Selection for 34712 Eval Board 5.1 I/O Parameters: VIN = 3.3V PVIN = VREFIN = VDDQ =1.5 V (DDR III Standard) VO =VTT = 0.750 V IO = 3 A FSW = 1 MHz 5.2 Configuring the Output Voltage: The output voltage is given by the equation: VTT = VREFIN 2 Using the 34712, Rev. 4.0 Freescale Semiconductor 3 Component Selection for 34712 Eval Board 5.3 Switching Frequency Configuration The switching frequency will have a default value of 1.0 MHz by connecting the FREQ terminal to the GND terminal. If the smallest frequency value of 200 KHz is desired, then connect the FREQ terminal to VDDI. To program the switching frequency to another value, an external resistor divider will be connected to the FREQ terminal to achieve the voltages given by the Frequency Selection Table. Frequency Khz Voltage applied to pin FREQ [V] 200 2.341 – 2.500 253 2.185 - 2.340 307 2.029 - 2.184 360 1.873 - 2.028 413 1.717 – 1.872 466 1.561 – 1.716 520 1.405 - 1.560 573 1.249 - 1.404 627 1.093 - 1.248 680 0.936 - 1.092 733 0.781 - 0.936 787 0.625 - 0.780 840 0.469 - 0.624 893 0.313 - 0.468 947 0.157 - 0.312 1000 0.000 - 0.156 Table 1. Frequency Selection Table For the EVB the frequency was set to 1 MHz connecting the FREQ terminal directly to GND. Using the 34712, Rev. 4.0 4 Freescale Semiconductor Component Selection for 34712 Eval Board 5.4 Selecting Inductor Inductor calculation is as follows: L = D ' MAX ∗T ∗ (Vo + I 0 * ( Rds (on) _ ls + r _ w)) ΔI o Maximum Off time percentage T = 1μs Switching period Rds (on) _ ls = 45mΩ Drain – to – source resistance of FET Winding resistance of Inductor ΔIo = 0.4 * Io Output current ripple L = 0 .67 μ H We have selected L = 1 .5 μ H to allow some operating margin. 5.5 Input Capacitors Input capacitor selection should be based on the current ripple allowed on the input line. The input capacitor should provide the ripple current generated during the inductor charge time. This ripple is dependent on the output current sourced by 34712 so that: I RMS = Io d (1 − d ) Where: IRMS is the RMS value of the input capacitor current I0 is the output current d= Vo/Vin is the duty cycle For a buck converter, IRMS has its maximum at Vin = 2Vo Since I RMS_MAX = PMAX ESR Using the 34712, Rev. 4.0 Freescale Semiconductor 5 Component Selection for 34712 Eval Board Where PMAX is the maximum power dissipation of the capacitor and is a constant based on physical size (generally given in the datasheets under the heading AC power dissipation). We derive that the lower the ESR, the higher would be the ripple current capability. In other words, a low ESR capacitor (i.e., with high ripple current capability) can withstand high ripple current levels without overheating. Therefore, for greater efficiency and because the overall voltage ripple on the input line also depends on the input capacitor ESR, we recommend using low ESR capacitors. Cin MIN = 0.5 * L * ( I RMS ) 2 ΔVo * Vin For a ΔVo = 0.5*Vin, Then CinMIN = 30.4μF On the EVB there was selected an input capacitor of 300μF to assure less input voltage ripple and have better regulation. 5.6 Selecting the Output Filter Capacitor For the output capacitor, the following considerations are most important and not the actual Farad value: the physical size, the ESR of the capacitor, and the voltage rating. Calculate the minimum output capacitor using the following formula: ΔI 0 C 0 = ------------------------------8 ⋅ F SW ⋅ ΔV 0 However, a more significative calculation is to include the transient response in order to calculate the real minimum capacitor value to assure a good performance. Transient Response percentage Maximum Transient Voltage TR_% = 3% TR_V_dip = Vo*TR_% = 0.75*0.03 = 0.0225V Maximum current step ΔIo _ step = Inductor Current rise time dt _ I _ rise = (Vin _ min − Vo ) * D _ max =1.35A Fsw * L T * Io ΔIo _ step = 2.2μs Io * dt _ I _ rise = 296.3μF TR _ V _ dip To find the Maximum allowed ESR, the following formula was used: Co = ESRmax = ΔVo * Fsw * L = 3mΩ Vo(1 − D min) Using the 34712, Rev. 4.0 6 Freescale Semiconductor Component Selection for 34712 Eval Board As a DDR specification, the ESR should be around 2 mΩ, to achieve this, an array of capacitors in parallel where used, with 3 Low ESR Ceramic capacitor of 100 μF. 5.7 Bootstrap Capacitor Freescale recommends a 0.1 μF for this capacitor. 5.8 Compensation Network 1. Choose a value for R1 = 20KΩ 2. Using a Crossover frequency of 50 kHz, set the Zero pole frequency to Fcross/10 FP 0 = 1 1 = 5.0kHz Fcross = 10 2π * R1C F 3. Knowing the LC frequency, the Frequency of Zero 1 and Zero 2 in the compensation network are equal to FLC FZ 1 = RF = 1 = 14.66 KΩ 2π * C F FZ 1 1 2π * RF C F CS = FZ 2 = 1 2π * R1C S 1 = 1.06 nF 2π * R1 FZ 2 4. Calculate Rs by placing the first pole at the ESR zero frequency: FP1 = RS = FP 2 = 1 2π * RS C S 1 = 570Ω 2π * FP1C S 1 C F Cx 2π * R F CF + Cx = 500 kHz Using the 34712, Rev. 4.0 Freescale Semiconductor 7 Component Selection for 34712 Eval Board 5. Set the second pole at ten times the Crossover Frequency to achieve a faster response and a proper phase margin. FP 2 = 1 C F Cx 2π * RF CF + Cx = 500kHz CX = CF = 24 pF 2π * R F C F FP 2 − 1 The Actual values used on the EVB might change due to precision of L and C components thus, on EVB where selected as follows. CF = 1.9 nf RF = 15 kΩ 1 10 Rs = 300 Ω Cs = 1 nf 100 1000 Hz 10000 100000 1000000 Cx = 20 pf 10000000 100000000 120 100 80 60 40 20 dB/Deg 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 Open Loop Gain and phase User Values Gain (dB) Phase (Degrees) Figure 2. Compensated Open Loop Bode Plot Using the 34712, Rev. 4.0 8 Freescale Semiconductor Component Selection for 34712 Eval Board 5.9 EVB Schematic Design VIN I/O SIGNALS BOOT VIN BOOT VDDI C15 SW 4.7_nopop VDDI J2 0.1uF PVIN R16 PVIN R10 10k_nopop 3 2 1 ILIM R11 10k R13 10k_nopop FREQ ILIM 21 19 PVIN PVIN BOOT VIN VIN VDDI R12 10k_nopop FREQ J3 GND VMASTER VOUT 20 U1 22 C14 0.1uF 24 GND PVIN 3 2 1 23 VIN 1 SGND PVIN 18 2 FREQ SW 17 3 N/C SW 16 SW SW MC34712 PG VMASTER PGOOD LED PG 4 PG STBY 5 STBY SD 6 SD SW 15 GND 14 GND 13 STBY GND GND 12 INV COMP VREFOUT VOUT 11 10 7 R7 1k R8 10k_nopop 9 VIN 8 VMASTER VREFIN SD VREFIN VREFIN D1 LED VREFIN R9 10k_nopop C11 C13 0.1uF 0.1uF LED VOUT VOUT VREFOUT VREFOUT INV C12 0.1uF COMP JUMPERS BUCK CONVERTER VOUT1 INV COMP VOUT2 J1 L1 SW 1 VOUT 2 D2 PVIN VMASTER STBY 1.5uH LED R3 4.7_nopop C6 100uF C7 100uF 1 2 1 2 C8 100uF 1 3 5 7 9 2 4 6 8 10 VREFIN PG STBY SD PMEG2010EA_nopop C9 1nF_nopop CON10A SD COMPENSATION NETWORK PVIN CAPACITORS VOUT OPTIONAL nopop VDDI PVIN ILIM C20 1nF C18 C3 100uF C4 100uF C5 100uF R14 300 0.02nF FREQ R6 POT_50K_nopop R5 POT_50K_nopop VIN CAPACITORS VIN R15 15k C2 1uF R1 20k INV COMP C1 0.1uF C19 R2 12.7k_nopop C17 10uF 1.9nF C16 0.1uF Figure 3. 34712 Schematic Using the 34712, Rev. 4.0 Freescale Semiconductor 9 Layout Design 6 Layout Design Figure 4. PCB Layout Top View Using the 34712, Rev. 4.0 10 Freescale Semiconductor Layout Design Figure 5. PCB Layout Inner Layer Using the 34712, Rev. 4.0 Freescale Semiconductor 11 Layout Design Figure 6. PCB Layout Bottom Layer 6.1 • • • • • • • • • • • PCB Layout Recommendations Place decoupling capacitors as close as possible to their corresponding pad(s) Try to place all components on just one Layer Do not place a Ground Plane on component and routing side Create a Ground plane layer and tie it to ground signals with vias To effectively transfer heat from the center thermal pad on the top layer to the ground plane, vias need to be used in the center pad. Use 5 to 9 vias spaced evenly with a finished diameter of 0.3mm. Place Test vias as close as possible to the IC to ensure a good measurement value PVIN, VIN, VOUT signals have to be tracked with a widely and straight copper area Never trace the Feedback signal in parallel to the SW signal Ensure the SW Inductor is placed as close as possible to its pads SW track has to be as thin and short as possible Make sure the I/O connectors are capable to manage the Load current Note: Freescale does not recommend connecting the PGND pins to the thermal pad. The thermal pad is connected to the signal ground and should not be used to make the connection from the PGND pins to the ground plane. Doing so can cause ground bounce on the signal ground from the high di/dt switch current and parasitic trace inductance. Using the 34712, Rev. 4.0 12 Freescale Semiconductor Layout Design 6.2 Bill of Materials Item Quantity Reference Value Description Footprint 1 16 VREFOUT, VREFIN, VOUT, VIN, VDDI, SW, STBY, SD, PVIN, PG, INV, ILIM, GND, FREQ, COMP, BOOT not populated PC test point miniature SMT TP1 2 1 C2 1μF Cap Cer 1.0μF 6.3V 10% X5R 0603 SM/C_0603 3 6 C3, C4, C5, C6, C7, C8 100μF Cap Cer 100μF 10% X5R 1210 SM/C_1210 4 1 C9 not populated 5 7 C1, C11, C12, C13 , C14 C15, C16 0.1μF Cap Cer 0.1μF 50V 10% X7R 0603 SM/C_0603 6 1 C17 10μF Cap Cer 10μF 6.3V 20% X5R 0603 SM/C_0603 7 1 C18 20pF Cap Cer 20pF50V 5% C0G 0603 SM/C_0603 8 1 C19 1.8nF Cap Cer 1800pF 50V 5% C0G 0603 SM/C_0603 9 1 C20 1nF Cap Cer 1000pF 25V 5% C0G CC0603 SM/C_0603 10 1 D1 LED LED Green 0603 SM/C_0603 11 1 D2 not populated 12 1 J1 Pin Header (2X5) 13 2 100mils jumpers Jumpers 14 1 J2 not populated 15 1 J3 not populated 16 1 L1 1.5μH Inductor Power 1.5μH 7.0A SMD B82464G 17 1 R1 20k Res MPF 20k ohm 1/10W 5% 0603 SM/C_0603 18 1 R2 12.7k Res 12.7k ohm 1/10W 1% 0603 SMD SM/C_0603 19 2 R3,R16 not populated SM/C_0603 20 2 R5,R6 not populated TRIMPOT 21 1 R7 1k SMC HDR 2X5 TH 100MIL CTR 330H AU 0.1” (2.54mm) 100 mils Res MF 1.0k 1/10W 1%0603 SM/C_0603 Using the 34712, Rev. 4.0 Freescale Semiconductor 13 Layout Design 22 2 R12,R13 not populated SM/C_0603 23 3 R8, R9, R10 10k Res MF 10.0k 1/10W 1% 0603 SM/C_0603 24 1 R11 10k Res MF 10.0k 1/10W 1% 0603 SM/C_0603 25 1 R14 300 Res MF 300 Ohm 1/10W 5% 0603 SM/C_0603 26 1 R15 15k Res MF 15.0k 1/10W 1% 0603 SM/C_0603 27 1 SD Push_button Switch tact mini 200GF SLV GWING 28 1 U1 MC34712 29 1 STBY not populated QFN_24 Switch tact mini 200GF SLV GWING Notes: Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application. Using the 34712, Rev. 4.0 14 Freescale Semiconductor Conclusion 7 Conclusion With this User’s Guide, the user will be perfectly capable of configuring the 34712 as power supply for DDR memory chips as well as other devices that can make use of some of the capabilities the 34712 offers. The board is fully configured to work at any desirable reference voltage within 0 and 2.5 V. However, it is widely recommended to calculate all components for the specific application situation in order to assure a better efficiency and stability of the IC 8 References • • • MC34712 Datasheet, “3 A, 1MHz Fully Integrated, Single Switch-mode, Power Supply”; Freescale semiconductor, Inc. Similar network compensation calculations are available in Application Note “AN1989 MC34701 and MC34702 Component Selection Guide”, Freescale Semiconductor, Inc. Sanjaya Maniktala, “Switching Power Supplies A to Z”, Newnes, 2006. Using the 34712, Rev. 4.0 Freescale Semiconductor 15 How to Reach Us: Home Page: www.freescale.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. Web Support: http://www.freescale.com/support For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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