LC Selection Guide for the DC-DC Synchronous Buck Converter

AND9135/D
LC Selection Guide for the
DC-DC Synchronous Buck
Converter
Introduction
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Switched mode power converters are very prominent in
industry today, and provide high efficiency solutions for a
wide range of applications. Switched mode converters can
be found in power supplies and battery charging circuitry for
computers, electric tools, televisions, media tablets, smart
phones, automobiles, and countless other electronic devices.
One of the most popular converters for the consumer
electronics industry is the DC:DC step−down converter, also
known as the buck converter.
The synchronous buck converter is used to step a voltage
down from a higher level to a lower level. With industry
moving to higher performance platforms, efficiency of the
power converter is critical. The design of the power
converter must be optimized to maximize performance and
to meet customer requirements. Because of this, it is
important to understand the fundamentals of the
synchronous buck converter and how to appropriately select
the circuit components.
APPLICATION NOTE
this time, Q2 is off and the current through the inductor
increases, charging the LC filter. When Q1 turns off, Q2
turns on and current is supplied to the load through the low
side MOSFET. During this time, the current through the
inductor decreases, discharging the LC filter. The low side
MOSFET provides an additional function when both
MOSFETs are off. It clamps the switch node voltage via the
body diode to prevent VSW from going too far negative
when the high side transistor first turns off.
Synchronous Buck Converter Basics
The synchronous buck converter is straightforward in
concept, and is used heavily in consumer electronics. A
synchronous buck converter produces a regulated voltage
that is lower than its input voltage, and can deliver high
currents while minimizing power loss. As shown in
Figure 1, the synchronous buck converter is comprised of
two power MOSFETs, an output inductor and an output
capacitor. This specific buck topology derives its name from
the control method of the two power MOSFETs; the on / off
control is synchronized in order to provide a regulated
output voltage and to prevent the MOSFETs from turning on
at the same time.
Figure 2. Synchronous Buck Converter
Waveforms
Figure 2 shows the basic waveforms for the synchronous
buck converter in continuous conduction mode. The total
change in inductor current is known as the peak−to−peak
inductor current, DIL. The switch node voltage is smoothed
out by the LC output stage in order to produce a regulated
DC voltage at the output. The MOSFETs are controlled
synchronously to prevent shoot−through. Shoot−through
occurs when the high side and low side MOSFET are both
on at the same time, providing a direct short to ground.
Figure 1. Synchronous Buck Converter
Q1, the high side MOSFET, is connected directly to the
input voltage of the circuit. When Q1 turns on, current is
supplied to the load through the high side MOSFET. During
© Semiconductor Components Industries, LLC, 2013
April, 2013 − Rev. 0
1
Publication Order Number:
AND9135/D
AND9135/D
and output voltage overshoot, but increases the time it takes
the output voltage feedback loop to respond to changes in
load. Therefore, a minimum capacitance must be considered,
in order to meet the ripple voltage and voltage overshoot
requirements of the converter, while maintaining a feedback
loop that can respond quickly enough to load changes.
Capacitors also have a parasitic series resistance, known
as the equivalent series resistance (ESR). The ESR impacts
the output voltage ripple and the overall efficiency of the
converter. Because of this, designers are moving to low ESR
designs. Surface mount ceramic capacitors are becoming
prevalent in systems that require high performance in a
small form factor. The use of multiple capacitors in parallel
allows designers to achieve the necessary capacitance for
the system while greatly reducing the equivalent ESR.
The high side MOSFET on−time determines the duty
cycle of the circuit, and is defined in Equation 1.
D+
t ON,HS
V
^ OUT
t ON,HS ) t OFF,HS
V IN
(eq. 1)
If the duty cycle, D, is equal to 1 then the high side
MOSFET is on 100% of the time and the output voltage
equals the input voltage. A duty cycle of 0.1 means that the
high side MOSFET is on 10% of the time, producing an
output voltage that is approximately 10% of the input voltage.
Buck Converter Power Loss
The buck converter power losses are influenced by
multiple factors, including the power MOSFETs, output
stage, controller / driver, feedback loop, and layout of the
converter itself. The duty cycle is less than 0.5 for most buck
converter designs, with a standard duty cycle of 0.1 to 0.2 in
the computing and server market. Design platforms are
moving to higher switching frequencies, providing the
ability to reduce converter size and form factors. At the same
time, converters must deliver greater performance and have
higher efficiency. The output stage performance greatly
impacts the overall performance of the buck converter. For
this reason, it is important to optimize the inductor and
capacitor selection for the specific application. The rest of
this application note focuses on the output stage design.
Basic LC Design
When designing the buck converter output stage, it is
recommended to begin with the inductor. The minimum
inductance is calculated based on the target ripple current and
other application circuit specifications. Once the inductor has
been selected, the minimum capacitance can be determined.
Calculating Minimum Inductance
Let’s begin with the basic inductor current / voltage
relationship, seen in Equation 2.
VL + L @
The LC Output Stage
dI L
dt
(eq. 2)
Inductor current ripple is defined as the peak−to−peak
change in current during the converter on time. For the
synchronous buck converter, the change in inductor current
during the high side MOSFET on−time is equal to the
change during the high side MOSFET off−time. In other
words, the inductor current increase is equal to the inductor
current decrease (refer to Figure 2).
The output stage of the synchronous buck converter is
comprised of an inductor and capacitor. The output stage
stores and delivers energy to the load, and smoothes out the
switch node voltage to produce a constant output voltage.
Inductor selection directly influences the amount of
current ripple seen on the inductor current, as well as the
current capability of the buck converter itself. Inductors
vary from manufacturer to manufacturer in both material
and value, and typically have a tolerance of ±20%.
Inductors have an inherent DC resistance (known as the
DCR) that impacts the performance of the output stage.
Minimizing the DCR improves the overall performance of
the converter. For applications that require a high load
current, it is recommended to select an inductor with a low
DCR. The DCR is smaller for lower inductor values, but
there is a trade−off between inductance and ripple current;
the lower the inductance, the higher the ripple current
through the inductor. A minimum inductance must be met in
order to meet the ripple current requirements of the specific
application circuit.
The output capacitance directly affects the output voltage
of the converter, the response time of the output feedback
loop, and the amount of output voltage overshoot that occurs
during changes in load current. A ripple voltage exists on the
DC output as the current through the inductor and capacitor
increases and decreases. Increasing the capacitance reduces
the amount of ripple voltage present. However, there is a
tradeoff between capacitance and the output response.
Increasing the capacitance reduces the output voltage ripple
DI L()) + DI L(*)
(eq. 3)
For this reason, the inductor current ripple can simply be
defined as DIL and units are Amperes. The dIL/dt term
during the converter on time can be written as:
dI L
DI L
+
t
dt
ON,HS
(eq. 4)
Combining Equation 2 and Equation 4 and solving for the
inductance yields Equation 5.
L MIN +
V L(ON) @ t ON,HS
DI L
(eq. 5)
In order to solve for inductance in terms of the application
circuit parameters, some additional terms must be defined first.
During the converter on time, the high side MOSFET is
conducting and the low side MOSFET is off. Using
Kirkhoff’s voltage law, VL(ON) is defined as
V L(ON) + V IN * V HS * V OUT
(eq. 6)
where VHS is the voltage drop across the high side MOSFET
and is defined as:
V HS + R DS(on)HS @ D @ I OUT,MAX
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(eq. 7)
AND9135/D
The duty cycle is defined as the ratio of high side
MOSFET on time to the switching period of the converter.
In other words,
D+
t ON,HS
T SW
+ t ON,HS @ f SW
As can be seen, there is a tradeoff between inductance and
ripple current. Lower target ripple current equates to higher
minimum inductance. To optimize the output filter
performance it is recommended to target 20% − 40%
inductor ripple current, which translates to an LIR of 0.2 – 0.4.
Calculating Maximum ESR and Minimum Capacitance
Capacitance is required to maintain a regulated output
voltage while the high side MOSFET is off, and is necessary
to minimize the amount of ripple present on the output
voltage. The output voltage ripple, DVPP, can be expressed
as a peak−to−peak voltage or in terms of the Capacitor
Voltage Ratio, or CVR.
(eq. 8)
And Equation 5 becomes:
L MIN +
ǒV IN * VHS * VOUTǓ @ D
(eq. 9)
DI L @ f SW
The ripple current can also be expressed in terms of the
inductor current ripple ratio, or LIR.
DI L + LIR @ I OUT,MAX
(eq. 10)
DV PP + CVR @ V OUT
Substituting Equation 10 into Equation 9, the minimum
inductance, LMIN, becomes:
L MIN +
ǒV IN * VHS * VOUTǓ @ D
LIR @ I OUT,MAX @ f SW
A CVR of 0.05, for example, equates to an output ripple
voltage that is 5% of the DC output voltage.
ESR and capacitance influence the response time of the
output feedback loop. The larger the output capacitance
value and ESR, the longer it takes for the output to respond
to changes in load. ESR also influences the output voltage
ripple. The maximum ESR can be calculated using the
specified maximum voltage ripple, DVPP, and the maximum
load current, as shown in Equation 23.
(eq. 11)
Equation 3 can be used to calculate the duty cycle, D using
DIL(+) and DIL(−) as defined in Equation 12 and 13 below.
DI L()) +
DI L(*) +
V L_ON,HS
L
V L_OFF,HS
L
@ t ON,HS
(eq. 12)
@ t OFF,HS
(eq. 13)
ESR MAX +
where VL(ON) is defined in Equation 6 and VL(OFF) is:
V L(OFF) + V OUT ) V LS
The high side MOSFET tON and tOFF can also be written
in terms of duty cycle.
(eq. 15)
t OFF,HS + 1 * D
f SW
(eq. 16)
Setting DIL(+) equal to DIL(−) and substituting Equations
14, 15 and 16, the duty cycle becomes:
D+
V OUT ) V LS
V IN * V HS ) V LS
CVR @ V OUT
DV PP
+
I OUT,MAX
I OUT,MAX
(eq. 23)
Therefore, in order to have an output voltage ripple below
the specified maximum, the ESR of the output capacitance
must be less than the value calculated using Equation 23.
When the high side MOSFET is on, current through the
inductor and capacitor is increasing, and the output voltage
increases. When the high side MOSFET is off, current
through the inductor and capacitor are decreasing, and the
output voltage decreases. In order to achieve a constant
output voltage, the amount of capacitor current increase
must be equal to the amount of capacitor current decrease.
Therefore, the steady state current through the capacitor is
0 A (Figure 3).
(eq. 14)
t ON,HS + D
f SW
(eq. 22)
(eq. 17)
where VLS the voltage drop across the low side MOSFET
when it is conducting, and is defined as:
V LS + R DS(on)LS @ (1 * D) @ I OUT,MAX
(eq. 18)
Therefore, the final inductance equation, LMIN, becomes:
ǒ
L MIN+
Ǔǒ
Ǔ
(eq. 19)
V IN * V HS * V OUT
V OUT ) V LS
@
LIR @ I OUT,MAX @ f SW
V IN * V HS ) V LS
Equation 19 can be simplified by neglecting the high side
and low side MOSFET voltage drops, producing a minimum
inductance of
L MIN ^
(V IN * V OUT) @ D
LIR @ I OUT,MAX @ f SW
(eq. 20)
where the duty cycle is estimated to be
D^
V OUT
V IN
Figure 3. Inductor and Capacitor Current
(eq. 21)
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The current through the capacitor is defined as:
DV C
IC + C @
Dt
(eq. 24)
Dt @ I C + C @ DV C + DQ C
(eq. 25)
Both Equations 31 and 34 must be taken into
consideration when selecting the output capacitance. There
is a tradeoff between the output voltage transient response
and output voltage ripple. These two must be balanced for
the needs of the specific application.
and can be re−written as:
The area under the curve (shown in red in Figure 3) is the
capacitor charge, DQC, and is defined as:
where
DQ C + ǒ1Ǔ @ DI C @ Dt
2
1
ǒ
Ǔ
Dt +
@ t ON ) ǒ1Ǔ @ t OFF
2
2
1
D
Ǔ ) ǒ12Ǔ @ ǒ1f* DǓ
+ǒ Ǔ@ǒ
f
2
1
2 @ f SW
+
SW
This section walks through a design example applying the
equations defined in the previous section. Table 1 lists the
target application requirements for this example that must be
met by the converter design.
(eq. 26)
(eq. 27)
Table 1. DESIGN EXAMPLE CIRCUIT REQUIREMENTS
SW
Parameter
ǒ Ǔǒ
Ǔ
DI L
DI L
1
DQ C + 1 @
@
+
2
8 @ f SW
2
2 @ f SW
DI L
+ C MIN @ DV PP
8 @ f SW
(eq. 29)
LIR @ I OUT,MAX
8 @ f SW @ CVR @ V OUT
ǒǓ
DI L
2
(eq. 35)
0.3
Capacitor Voltage Ripple Ratio
CVR
0.04
Output Voltage Max Overshoot
VOV
96 mV
IOUT,MAX
25 A
1.2 V
+ 0.1
12 V
(eq. 36)
(12 V * 1.2 V) @ 0.1
+ 0.206 mH (eq. 37)
0.3 @ 25 A @ (700 @ 10 3)Hz
0.3 @ 25 A
+ 28.75 A
2
(eq. 38)
The saturation current of the inductor must be greater than
28.75 A. A good rule of thumb is to select an inductor with
a saturation current at least 20% higher than the
application’s peak current.
The minimum output capacitance is calculated using
Equations 31 and 34. The minimum capacitance needed to
meet the output voltage ripple ratio is:
C MIN+
0.3 @ 25 A
+27.9 mF(eq. 39)
8 @ (700 @ 10 3 Hz) @ (0.04 @ 1.2 V)
The minimum output capacitance needed to achieve a
maximum output voltage overshoot of 96 mV for the
worst−case load transient condition is:
Solving for C, the equation becomes:
I PEAK + I OUT,MAX @
LIR
I PK + 25 A )
ǒǓ
where IPK is defined as:
Inductor Current Ripple Ratio
Therefore, to obtain a ripple current that is less than 30%
of the maximum output current, the inductor selected must
have an inductance value higher than 0.206 mH. The
inductor selected for this application must have a saturation
current that is higher than the peak current requirements of
the application. For this example, IPK is
2
) 1 @ L@ I PK 2 + 1 @ C@ ǒV OV ) V OUTǓ
2
2
(eq. 34)
700 kHz
L MIN ^
ǒǓ
L @ I PK 2
(V OV ) V OUT) 2 * V OUT 2
1.2 V
fSW
Next, the minimum inductance is calculated using
Equation 20. For this example, LMIN is:
(eq. 31)
The total energy prior to the load transition must be equal
to the total energy after the load transition. Therefore, (eq. 33)
C MIN +
VOUT
D^
E TOT + E C ) E L + 1 @ C @ V C 2 ) 1 @ L @ I L 2 (eq. 32)
2
2
ǒǓ
12 V
First, the duty cycle can be estimated, using Equation 21.
For this example, the duty cycle is:
The above equation only considers the affect of output
ripple voltage and inductor ripple current on the output
capacitance. The transient load response capability of the
output stage must also be considered. The synchronous buck
converter must be able to respond to changes in load current
while maintaining a regulated output voltage. When the load
current changes from a higher value to a lower value, the
output voltage will temporarily increase until the converter
is able to adjust the duty cycle to return the output voltage
to its regulated value. This temporary output voltage
increase is known as output voltage overshoot, VOV. The
worst−case overshoot will occur when the load transitions
from maximum load to no load. The output capacitor must
be able to handle this transient condition.
The total energy of the output stage is defined as:
2
VIN
Switching Frequency
Maximum Output Current
(eq. 30)
The minimum output capacitance due to the output
ripplve voltage can be derived by combining Equations 10,
22 and 30 and solving for capacitance.
ǒ12Ǔ@ C@ VOUT
Target
Output Voltage
(eq. 28)
And Equation 25 becomes:
C MIN +
Symbol
Input Voltage
DI
DI C + L
2
and
Therefore, Equation 26 can be re−written as:
ǒǓ
LC Design Example
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C MIN +
L @ I PK 2
(V OV ) V OUT) 2 * V OUT 2
C MIN +
0.206 mH @ (28.75 A) 2
+ 709.6 mF
(0.096 V ) 1.2 V) 2 * (1.2 V) 2
(eq. 40)
AND9135/D
A good rule of thumb when selecting capacitance is to
choose an out capacitor value that is at least 20% higher than
the minimum calculated capacitance, to account for
capacitor tolerance.
Table 4 lists the output filter parameters tested in the
open−loop configurations. All waveforms were measured at
a load current of 25 A.
Table 4. LC VALUES FOR OPEN−LOOP EXPERIMENTS
LC Experiments
The buck converter output filter design affects the output
current ripple, output voltage ripple, output voltage
overshoot, and the transient response of the feedback loop.
Component selection also impacts the efficiency of the
converter. Open−loop and closed loop experiments were
carried out to examine the effect of capacitance and
inductance on the converter’s performance.
Three inductors were selected for the experiments in order
to examine the impact of inductance value and DCR on
circuit performance. Two inductors with equivalent DCR
but different inductance were selected to examine the impact
of inductance value on circuit performance. They differed in
core size and inductance, but were made from the same
material and by the same manufacturer. A third inductor was
selected to examine the impact of the DCR on circuit
performance. It was selected from the same manufacturer,
but differed in core material.
Test
L−Value (mH)
1
2
L−DCR (mW)
C−Value (mH)
0.30
1
1600
0.82
0.9
3200
Table 2. INDUCTORS USED IN EXPERIMENTS
L (uH)
DCR
ISAT (A)
Core Size (mm)
Figure 4. Ripple Current for 0.3 mH Inductor
0.30
1.0
35
10 x 10
0.82
0.9
35
13 x 13
0.30
0.29
32.5
9.6 x 6.4
Figure 4 shows the ripple current for the 0.30 mH /
1600 mF output filter. As can be seen, the measured output
ripple current was 6 A.
Table 2 lists the inductance, DCR, saturation current and
core size for the three surface mount inductors used in the
experiments.
LC Filter Impact on Ripple Current and Ripple Voltage
A buck converter was tested under the conditions listed in
Table 3, in an open−loop configuration, using a 5 V
MOSFET driver. A signal generator was used to create the
PWM pulse. The inductor current was measured using a
current probe.
Table 3. TEST CONDITIONS FOR EXPERIMENTS
Parameter
Symbol
Value
VIN
12 V
VOUT
1.2 V
fSW
700 kHz
Drive Voltage
VDRIVE
5V
Load Current
ILOAD
0 – 25 A
LIR Maximum
DIL
0.3
CVR Maximum
DVPP
0.04
Input Voltage
Output Voltage
Switching Frequency
Figure 5. Ripple Current for 0.82 mH Inductor
Figure 5 shows the ripple current for the 0.82 mH /
3200 mF output filter. At a 25 A load, the measured ripple
current was 2.5 A. According to the parameters specified in
Table 3, the ripple current could not exceed 30% of the
maximum load current (7 A). For both cases, this
requirement was met. As can be seen from the experiment,
using a higher inductance value reduced the measured ripple
current.
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Table 6. TEST CONDITIONS (Efficiency Experiments)
Parameter
Input Voltage
Output Voltage
Switching Frequency
Symbol
Value
VIN
12 V
VOUT
1.2 V
fSW
700 kHz
Drive Voltage
VDRIVE
5V
Load Current
ILOAD
1 – 25 A
First, the effect of output capacitance was examined. A
0.3 mH inductor with a 1 mW DCR was used for both tests.
The output capacitances used were 1600 mF and 3200 mF. As
can be seen in Figure 8, increasing the output capacitance
slightly lowered the circuit’s efficiency. In this example,
doubling the output capacitance had minimal effect on the
efficiency performance.
Figure 6. Ripple Voltage for 1600 mF Capacitance
Figure 6 and 7 show the output ripple voltage measured
for 1600 mF and 3200 mF capacitance respectively.
As can be seen, the output ripple voltage is less for the
3200 mF capacitance.
Figure 8. Effect of Capacitance on Efficiency
Next, the effect of inductor DCR was examined. Two
0.3 mH inductors, one with 1 mW and the other with
0.29 mW, were paired with 1600 mF output capacitance. As
can be seen in Figure 9, DCR has a significant effect on the
circuit performance, producing a 1.7% efficiency
improvement at maximum load by using the inductor with
0.29 mW DCR.
Figure 7. Ripple Voltage for 3200 mF Capacitance
The specified maximum ripple voltage requirement was
4% (48 mV). For both 1600 mF and 3200 mF capacitances,
the ripple voltage limit was not exceeded.
LC Filter Impact on Efficiency
Next, closed−loop experiments were run to see the effect
of the output filter on efficiency. Table 5 lists the inductor
and capacitor combinations used in the experiments.
Table 5. LC VALUES FOR EFFICIENCY EXPERIMENTS
Test
L−Value (mH)
L−DCR (mW)
C−Value (mF)
1
0.30
1
1600
2
0.30
1
3200
3
0.30
0.29
1600
Each experiment was run under the conditions listed in
Table 6. The efficiency of the test circuit was then compared
between tests to see the effects of output filter on circuit
performance.
Figure 9. Effect of Inductor DCR on Efficiency
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designing for the specific application criteria that it will be
operating in.
From the experiment results, it was found that the inductor
value played a significant role in the output ripple current,
as well as in the converter’s efficiency performance. The
0.82 mH inductor ripple current was a third of the 0.3 mH
inductor ripple current. Similarly, the output voltage ripple
improved with a higher output capacitance.
The efficiency of the converter was greatly impacted by
the DCR of the inductor. Holding the output capacitance and
output inductance constant, the 0.29 mW DCR provided
1.7% higher efficiency at maximum load compared with the
1 mW DCR.
There is a tradeoff between inductance and saturation
current for inductors. Therefore, to meet or exceed a ripple
current requirement, the inductance must be greater than the
minimum calculated inductance, and the saturation current
of the inductor must be greater than the peak current of the
converter at maximum load.
Capacitance also plays a significant role in the
performance of the synchronous buck converter. Output
capacitance directly influences the amount of voltage ripple
and voltage overshoot seen on the output. Experiments
showed that the capacitance had minimal effect on the
efficiency performance.
Inductance and DCR both affect the converter’s
efficiency. Figure 10 shows the efficiency results of four
different inductors. At light load, the efficiency correlates to
inductance value; the higher the inductance, the higher the
light−load efficiency. As the load current increases, the DCR
begins to dominate. At heavy loads, the efficiency correlates
to the DCR value; the 0.29 mW DCR produced the highest
efficiency, and the 1.56 mW DCR produced the lowest
efficiency.
Figure 10. Effect of Inductance on Efficiency
As can be seen from the experiment, the efficiency was
most impacted by the output inductor selection. Both the
inductor value and DCR significantly affected the efficiency
of the converter.
References
1. “Buck−Converter Design Demystified.” Article
from Power Electronics Technology. June 2006.
www.powerelectronics.com.
2. “Understanding the Output Current Capability of
DC−DC Buck Converters”. Application note #
AND8117/D. ON Semiconductor.
3. “Basic Calculation of a Buck Converter’s Power
Stage.” Application note # SLVA477A. Texas
Instruments.
4. “Selecting Inductors for Buck Converters.”
Application note # AN−1197. National
Semiconductor. Sanjaya Maniktala
Conclusion
The output stage of the synchronous buck converter plays
a significant role in the performance of the converter. In
order to meet the target ripple current, output ripple voltage,
and output voltage overshoot, a minimum inductance and
capacitance must be exceeded. Additional factors must also
be considered when selecting an inductor and capacitor for
a specific application. The output stage can be optimized by
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