Data Sheet 100 MHz to 4000 MHz RF/IF Digitally Controlled VGA ADL5240 FEATURES GENERAL DESCRIPTION Operating frequency from 100 MHz to 4000 MHz Digitally controlled VGA with serial and parallel interfaces 6-bit, 0.5 dB digital step attenuator 31.5 dB gain control range with ±0.25 dB step accuracy Gain block amplifier specifications Gain: 19.7 dB at 2.14 GHz OIP3: 41.0 dBm at 2.14 GHz P1dB: 19.5 dBm at 2.14 GHz Noise figure: 2.9 dB at 2.14 GHz Gain block or digital step attenuator can be first Single supply operation from 4.75 V to 5.25 V Low quiescent current of 93 mA Thermally efficient, 5 mm × 5 mm, 32-lead LFCSP The companion ADL5243 integrates a ¼ W driver amplifier to the output of the gain block and DSA The ADL5240 is a high performance, digitally controlled variable gain amplifier (VGA) operating from 100 MHz to 4000 MHz. The VGA integrates a high performance, 20 dB gain, internally matched amplifier (AMP) with a 6-bit digital step attenuator (DSA) that has a gain control range of 31.5 dB in 0.5 dB steps with ±0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface. Both the gain block and DSA are internally matched to 50 Ω at their inputs and outputs and are separately biased. The separate bias allows all or part of the ADL5240 to be used, which facilitates easy reuse throughout a design. The pinout of the ADL5240 also enables either the gain block or DSA to be first, giving the VGA maximum flexibility in a signal chain. The ADL5240 consumes just 93 mA and operates from a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully specified for operation from −40°C to +85°C. A fully populated evaluation board is available. APPLICATIONS Wireless infrastructure Automated test equipment RF/IF gain control SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6 FUNCTIONAL BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 VDD NC 2 23 NC NC 3 22 NC 21 DSAOUT 20 NC 19 NC 18 NC 17 NC VDD 1 SERIAL/PARALLEL INTERFACE DSAIN 4 0.5dB 1dB 2dB 4dB 8dB 16dB NC 5 NC 6 ADL5240 AMP NC 7 NC NC 14 15 16 09430-001 AMPOUT/VCC 13 NC 12 AMPIN 11 NC 10 NC 9 NC NC 8 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility isassumed by Analog Devicesfor its use,norfor any infringements of patents or other rights of third parties thatmay resultfrom its use.Specificationssubject to changewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices . Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5240 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 16 Applications ....................................................................................... 1 Basic Layout Connections ......................................................... 16 General Description ......................................................................... 1 SPI Timing................................................................................... 18 Functional Block Diagram .............................................................. 1 Loop Performance ...................................................................... 20 Revision History ............................................................................... 2 Amplifier Drive Level for Optimum ACLR ............................ 22 Specifications..................................................................................... 3 Thermal Considerations............................................................ 22 Absolute Maximum Ratings............................................................ 8 Evaluation Board ............................................................................ 23 ESD Caution .................................................................................. 8 Outline Dimensions ....................................................................... 28 Pin Configuration and Function Descriptions ............................. 9 Ordering Guide .......................................................................... 28 Typical Performance Characteristics ........................................... 10 REVISION HISTORY 6/13—Rev. 0 to Rev. A Changes to Table 1 ............................................................................. 4 Changes to Table 3 ............................................................................. 9 Changes to Figure 3 .........................................................................11 Changes to Figure 16 .......................................................................12 Added Figure 29, Renumbered Sequentially ...............................14 Changes to Table 5, Figure 35, and Figure 36 ..............................18 Added Amplifier Drive Level for Optimum ACLR Section and Figure 39 ....................................................................................22 Changes to Evaluation Board Section ...........................................23 Changes to Figure 41 and Table 8 ..................................................24 Added Figure 42...............................................................................25 Changes to Figure 43 and Figure 44 ..............................................26 Added Figure 45...............................................................................27 7/11—Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet ADL5240 SPECIFICATIONS VDD = 5 V, VCC = 5 V, TA = 25o C Table 1. Parameter OVERALL FUNCTION Frequency Range AMPLIFIER FREQUENCY = 150 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 450 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 748 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 943 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Test Conditions/Comments Min Typ 100 Max Unit 4000 MHz Using the AMPIN and AMPOUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone 17.6 ±1.0 ±0.04 ±0.04 −10.4 −7.7 18.3 30.0 2.8 dB dB dB dB dB dB dBm dBm dB 20.3 ±0.11 ±0.36 ±0.01 −18.3 −15.7 20.2 39.0 2.9 dB dB dB dB dB dB dBm dBm dB 20.6 ±0.01 ±0.31 ±0.01 −25.7 −23.7 20.2 40.0 2.7 dB dB dB dB dB dB dBm dBm dB Using the AMPIN and AMPOUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins ±50 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins 19.0 ±18 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 18.5 ∆f = 1 MHz, POUT = 4 dBm/tone Rev. A | Page 3 of 28 20.5 ±0.01 ±0.27 ±0.01 −30.3 −24.8 20.1 40.0 2.7 22.0 dB dB dB dB dB dB dBm dBm dB ADL5240 Parameter AMPLIFIER FREQUENCY = 1960 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 2140 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 2630 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMPLIFIER FREQUENCY = 3600 MHz Gain vs. Frequency vs. Temperature vs. Supply Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA FREQUENCY = 150 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept Data Sheet Test Conditions/Comments Using the AMPIN and AMPOUT pins Min Typ Max 19.8 ±0.03 ±0.26 ±0.03 −11.9 −12.6 19.8 40.0 2.9 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Unit dB dB dB dB dB dB dBm dBm dB Using the AMPIN and AMPOUT pins 18.0 ±30 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 17.5 ∆f = 1 MHz, POUT = 4 dBm/tone 19.7 ±0.02 ±0.25 ±0.04 −11.0 −12.0 19.5 41.0 2.9 22.0 dB dB dB dB dB dB dBm dBm dB 19.6 ±0.01 ±0.22 ±0.04 −11.0 −13.3 19.9 41.0 2.9 22.0 dB dB dB dB dB dB dBm dBm dB Using the AMPIN and AMPOUT pins 18.0 ±60 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 18.0 ∆f = 1 MHz, POUT = 4 dBm/tone Using the AMPIN and AMPOUT pins ±100 MHz −40°C ≤ TA ≤ +85°C 4.75 V to 5.25 V S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the DSAIN and DSAOUT pins Minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Rev. A | Page 4 of 28 19.6 ±0.03 ±0.05 ±0.10 −15.1 −12.2 18.8 37.0 3.1 dB dB dB dB dB dB dBm dBm dB −1.5 ±0.12 ±0.09 28.8 ±0.18 ±1.35 −13.3 −13.4 47.9 dB dB dB dB dB dB dB dB dBm Data Sheet Parameter DSA FREQUENCY = 450 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 748 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input Third-Order Intercept DSA FREQUENCY = 943 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 1960 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 2140 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept ADL5240 Test Conditions/Comments Using the DSAIN and DSAOUT pins Minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±50 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±18 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±30 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Rev. A | Page 5 of 28 Min Typ Max Unit −1.5 ±0.02 ±0.10 30.7 ±0.14 ±0.42 −17.6 −17.6 45.0 dB dB dB dB dB dB dB dB dBm −1.6 ±0.02 ±0.11 30.9 ±0.15 ±0.32 −17.4 −17.4 43.5 dB dB dB dB dB dB dB dB dBm −1.6 ±0.01 ±0.12 30.9 ±0.13 ±0.30 −16.6 −16.5 30.5 50.9 dB dB dB dB dB dB dB dB dBm dBm −2.4 ±0.02 ±0.16 31.0 ±0.15 ±0.29 −12.0 −11.5 31.5 49.5 dB dB dB dB dB dB dB dB dBm dBm −2.5 ±0.02 ±0.17 31.0 ±0.12 ±0.26 −11.9 −11.2 31.5 49.2 dB dB dB dB dB dB dB dB dBm dBm ADL5240 Parameter DSA FREQUENCY = 2630 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DSA FREQUENCY = 3600 MHz Insertion Loss vs. Frequency vs. Temperature Attenuation Range Attenuation Step Error Attenuation Absolute Error Input Return Loss Output Return Loss Input 1 dB Compression Point Input Third-Order Intercept DIGITAL STEP ATTENUATOR GAIN SETTLING Minimum Attenuation to Maximum Attenuation Maximum Attenuation to Minimum Attenuation AMP-DSA LOOP FREQUENCY = 943 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure AMP-DSA LOOP FREQUENCY = 2140 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure Data Sheet Test Conditions/Comments Using the DSAIN and DSAOUT pins Minimum attenuation ±60 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Using the DSAIN and DSAOUT pins Minimum attenuation ±100 MHz −40°C ≤ TA ≤ +85°C All attenuation states All attenuation states Minimum attenuation Minimum attenuation Minimum attenuation ∆f = 1 MHz, POUT = 4 dBm/tone, minimum attenuation Min Typ Max Unit −2.6 ±0.04 ±0.19 31.2 ±0.16 ±0.19 −13.1 −12.0 31.5 47.6 dB dB dB dB dB dB dB dB dBm dBm −2.8 ±0.03 ±0.21 32.1 ±0.37 ±0.31 −20.2 −18.2 31.0 48.5 dB dB dB dB dB dB dB dB dBm dBm 36 36 ns ns 18.9 ±0.01 30.8 −20.5 −19.7 18.6 36.0 2.7 dB dB dB dB dB dBm dBm dB 18.2 ±0.01 31.3 −14.9 −16.4 17.9 37.5 3.0 dB dB dB dB dB dBm dBm dB Using the AMPIN and DSAOUT pins, DSA at minimum attenuation ±18 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 1 dBm/tone Using the AMPIN and DSAOUT pins, DSA at minimum attenuation ±30 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 1 dBm/tone Rev. A | Page 6 of 28 Data Sheet Parameter AMP-DSA LOOP FREQUENCY = 2630 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA-AMP LOOP FREQUENCY = 943 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA-AMP LOOP Frequency = 2140 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure DSA-AMP LOOP Frequency = 2630 MHz Gain vs. Frequency Gain Range Input Return Loss Output Return Loss Output 1 dB Compression Point Output Third-Order Intercept Noise Figure LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Supply Current Amplifier Digital Step Attenuator ADL5240 Test Conditions/Comments Using the AMPIN and DSAOUT pins, DSA at minimum attenuation Min ±60 MHz S11 S22 ∆f = 1 MHz, POUT = 1 dBm/tone Typ Max Unit 17.7 ±0.11 31.5 −15.2 −9.6 16.9 33.7 3.0 dB dB dB dB dB dBm dBm dB 18.9 ±0.01 30.8 −17.2 −23.7 20.2 40.0 4.4 dB dB dB dB dB dBm dBm dB 18.0 ±0.01 31.1 −13.7 −10.0 19.7 37.5 4.9 dB dB dB dB dB dBm dBm dB 18.2 ±0.01 31.7 −15.7 −16.9 19.8 40.8 5.2 dB dB dB dB dB dBm dBm dB Using the DSAIN and AMPOUT pins, DSA at minimum attenuation ±18 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the DSAIN and AMPOUT pins, DSA at minimum attenuation ±30 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone Using the DSAIN and AMPOUT pins, DSA at minimum attenuation ±60 MHz Between maximum and minimum attenuation states S11 S22 ∆f = 1 MHz, POUT = 4 dBm/tone CLK, DATA, LE, SEL, D0~D6 2.5 0.8 0.1 1.5 V V µA pF Using the VDD and VCC pins 4.75 Rev. A | Page 7 of 28 5.0 5.25 V 93 0.5 120 mA mA ADL5240 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VDD, VCC) Input Power AMPIN DSAIN Internal Power Dissipation θJA (Exposed Pad Soldered Down) θJC (Exposed Pad is the Contact) Maximum Junction Temperature Lead Temperature (Soldering, 60 sec) Operating Temperature Range Storage Temperature Range ESD CAUTION Rating 6.5 V 16 dBm 30 dBm 0.5 W 36.8°C/W 6.9°C/W 150°C 240°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 8 of 28 Data Sheet ADL5240 32 31 30 29 28 27 26 25 SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADL5240 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VDD NC NC DSAOUT NC NC NC NC NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. 09430-002 NC AMPOUT/VCC NC NC NC NC AMPIN NC 9 10 11 12 13 14 15 16 VDD NC NC DSAIN NC NC NC NC Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 24 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 16, 17, 18, 19, 20, 22, 23 4 10 Mnemonic VDD NC Description Supply Voltage for DSA. Connect this pin to a 5 V supply. No Connect. Do not connect to this pin. DSAIN AMPOUT/VCC 15 21 25 26 27 28 29 30 31 32 AMPIN DSAOUT D6 D5 D4 D3 D2/LE D1/DATA D0/CLK SEL RF Input to DSA. RF Output from Amplifier/Supply Voltage for Amplifier. A bias to the amplifier is provided through a choke inductor connected to this pin. RF Input to Amplifier. RF Output from DSA. Data Bit in Parallel Mode (LSB). Connect this pin to the supply in serial mode. Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. Data Bit in Parallel Mode. Connect this pin to ground or leave open in serial mode. Data Bit in Parallel Mode/Latch Enable in Serial Mode. Data Bit in Parallel Mode (MSB)/Data in Serial Mode. Connect this pin to ground in parallel mode. This pin functions as a clock in serial mode. Select Pin. Connect this pin to the supply to select parallel mode operation; connect this pin to ground to select serial mode operation. Exposed Pad. The exposed pad must be connected to ground. EPAD Rev. A | Page 9 of 28 ADL5240 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS OIP3 40 30 45 28 40 26 35 24 30 22 25 20 20 35 GAIN 25 20 OIP3 (dBm) P1dB (dBm) 30 15 5 0 18 NOISE FIGURE 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 FREQUENCY (GHz) 16 Figure 3. AMP: Gain, P1dB, OIP3 at POUT = 4 dBm/Tone and Noise Figure vs. Frequency 15 +85°C +25°C –40°C 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 10 3.6 09430-006 P1dB 10 09430-003 NOISE FIGURE, GAIN, P1dB, OIP3 (dB, dBm) 45 FREQUENCY (GHz) Figure 6. AMP: OIP3 at POUT = 4 dBm/Tone and P1dB vs. Frequency and Temperature 46 21.0 20.5 943MHz 42 –40°C 2140MHz 1960MHz 44 748MHz 40 20.0 OIP3 (dBm) GAIN (dB) 38 19.5 +25°C +85°C 19.0 36 450MHz 34 32 2630MHz 30 18.5 28 150MHz 26 18.0 3600MHz 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 FREQUENCY (GHz) 22 –5 09430-004 0 –3 –1 1 3 5 Figure 4. AMP: Gain vs. Frequency and Temperature 9 11 13 15 17 3.6 4.0 Figure 7. AMP: OIP3 vs. POUT and Frequency 0 4.5 –5 4.0 –10 +85°C S22 NOISE FIGURE (dB) S-PARAMETERS (dB) 7 POUT PER TONE (dBm) 09430-007 24 17.5 –15 –20 S12 –25 3.5 +25°C 3.0 –40°C 2.5 –30 2.0 –35 0.9 1.3 1.7 2.1 2.5 FREQUENCY (GHz) 2.9 3.3 3.7 4.1 Figure 5. AMP: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency Rev. A | Page 10 of 28 1.5 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 FREQUENCY (GHz) Figure 8. AMP: Noise Figure vs. Frequency and Temperature 09430-008 0.5 09430-005 S11 –40 0.1 Data Sheet ADL5240 0 1.0 0dB 0.8 –5 31.5dB 0.6 30.5dB 16dB STEP ERROR (dB) –15 –20 –25 0.4 0.2 0 –0.2 –0.4 –30 31dB –0.6 –35 –0.8 31.5dB 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) –1.0 0.1 09430-009 –40 0.1 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) Figure 9. DSA: Attenuation vs. Frequency –1 0.5 09430-016 ATTENUATION (dB) –10 Figure 12. DSA: Step Error vs. Frequency, All Attenuation States 1.0 0dB 748MHz 0.8 450MHz 4dB 8dB –11 1960MHz 0.6 ABSOLUTE ERROR (dB) ATTENUATION (dB) –6 –16 16dB –21 +85°C +25°C –40°C –26 0.4 0.2 2140MHz 0 943MHz 2630MHz –0.2 –0.4 –0.6 –31 3600MHz –0.8 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) –1.0 09430-010 –36 0.1 0 16 20 24 28 32 0 INPUT RETURN LOSS (dB) –5 0.2 0.1 0 –0.1 –0.2 –10 0dB –15 –20 31.5dB –25 –30 –0.3 –0.5 0 4 8 12 16 20 24 ATTENUATION (dB) 28 32 Figure 11. DSA: Step Error vs. Attenuation –40 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 FREQUENCY (GHz) Figure 14. DSA: Input Return Loss vs. Frequency, All States Rev. A | Page 11 of 28 4.1 09430-013 –35 –0.4 09430-011 STEP ERROR (dB) 0.3 12 Figure 13. DSA: Absolute Error vs. Attenuation 1960MHz 2140MHz 2630MHz 3600MHz 450MHz 748MHz 943MHz 0.4 8 ATTENUATION (dB) Figure 10. DSA: Attenuation vs. Frequency and Temperature 0.5 4 09430-012 31.5dB ADL5240 Data Sheet 0 OUTPUT RETURN LOSS (dB) –5 –10 0dB –15 3 –20 31.5dB –25 4 –30 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) CH3 2.00V 55 35 50 M10ns 10GS/s A CH3 IT 1.0ps/pt 1.24V Figure 18. DSA: Gain Settling Time, 0 dB to 31.5 dB Figure 15. DSA: Output Return Loss vs. Frequency, All States 36 CH4 200mV 09430-018 –40 0.1 09430-014 –35 45 33 40 32 35 IIP3 (dBm) IP1dB (dBm) IIP3 34 3 4 IP1dB 30 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 25 3.6 FREQUENCY (GHz) CH3 2.00V Figure 16. DSA: Input P1dB and Input IP3 vs. Frequency, Minimum Attenuation State M10ns 10GS/s A CH3 IT 1.0ps/pt 1.24V Figure 19. DSA: Gain Settling Time, 31.5 dB to 0 dB 200 22 100 2140MHz 50 2630MHz 20 0 –50 –100 943MHz 4 8 12 16 GAIN 16 14 12 10 8 6 NOISE FIGURE 4 2 –150 0 18 20 24 ATTENUATION (dB) 28 32 Figure 17. DSA: Phase vs. Attenuation 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) Figure 20. AMP-DSA Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State Rev. A | Page 12 of 28 09430-020 1960MHz GAIN AND NOISE FIGURE (dB) 150 09430-017 PHASE (Degrees) CH4 200mV 09430-019 30 09430-015 31 Data Sheet ADL5240 0 22 20 –5 S11 –10 –15 –20 –25 S12 –30 –35 GAIN 16 14 12 10 8 6 4 NOISE FIGURE 2 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) 0 0.1 09430-021 –40 0.1 18 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 FREQUENCY (GHz) Figure 21. AMP-DSA Loop: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State 09430-024 S-PARAMETERS (dB) GAIN AND NOISE FIGURE (dB) S22 Figure 24. DSA-AMP Loop: Gain and Noise Figure vs. Frequency, Minimum Attenuation State 40 0 38 –5 36 S22 S-PARAMETERS (dB) 943MHz OIP3 (dBm) 34 32 2140MHz 30 2630MHz 28 26 –10 S11 –15 –20 –25 S12 24 –30 –4 –2 0 2 4 6 8 10 12 14 16 POUT (dBm) –35 0.1 09430-022 20 –6 Figure 22. AMP-DSA Loop: OIP3 vs. P OUT and Frequency, Minimum Attenuation State 2.1 1.7 1.3 2.5 2.9 3.3 3.7 4.1 Figure 25. DSA-AMP Loop: Input Return Loss (S11), Output Return Loss (S22), and Reverse Isolation (S12) vs. Frequency, Minimum Attenuation State 44 19.5 42 40 943MHz 38 OIP3 (dBm) 18.5 2140MHz 18.0 2630MHz 17.5 943MHz 36 34 32 2140MHz 30 17.0 28 16.5 –2 0 2 4 6 8 10 12 14 16 18 POUT (dBm) 20 Figure 23. AMP-DSA Loop: Gain vs. P OUT and Frequency, Minimum Attenuation State 24 –6 –4 –2 0 2 4 6 8 10 12 14 POUT (dBm) Figure 26. DSA-AMP Loop: OIP3 vs. P OUT and Frequency, Minimum Attenuation State Rev. A | Page 13 of 28 16 09430-026 16.0 –4 2630MHz 26 09430-023 GAIN (dB) 0.9 FREQUENCY (GHz) 20.0 19.0 0.5 09430-025 22 ADL5240 Data Sheet 20.0 35 19.5 30 943MHz 19.0 09430-029 09430-030 0 20.4 20 20.5 18 20.5 16 20.4 14 20.2 12 20.3 10 20.1 8 20.0 6 POUT (dBm) 19.8 4 19.9 2 19.7 0 19.6 –2 19.4 16.0 –4 19.5 5 19.3 16.5 19.2 10 09430-027 17.0 19.1 15 18.9 2630MHz 17.5 20 19.0 GAIN (dB) 2140MHz 18.0 18.8 PERCENTAGE (%) 25 18.5 GAIN (dB) Figure 27. DSA-AMP Loop: Gain vs. P OUT and Frequency, Minimum Attenuation State Figure 30. AMP: Gain Distribution at 2140 MHz 30 110 25 PERCENTAGE (%) SUPPLY CURRENT (mA) 105 5.25V 100 5.00V 95 4.75V 20 15 10 90 5 TEMPERATURE (°C) 20.3 20.2 20.1 20.0 19.9 P1dB (dBm) Figure 31. AMP: P1dB Distribution at 2140 MHz Figure 28. AMP: Supply Current vs. Voltage and Temperature 30 110 25 100 –40°C 95 +25°C PERCENTAGE (%) 105 20 15 10 90 5 +85°C 0 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 POUT PER TONE (dBm) 22 Figure 29. AMP: Supply Current vs. P OUT and Temperature Rev. A | Page 14 of 28 OIP3 (dBm) Figure 32. AMP: OIP3 Distribution at 2140 MHz 09430-031 85 09430-100 SUPPLY CURRENT (mA) 19.8 90 19.6 80 19.7 70 19.5 60 19.4 50 19.3 40 19.2 30 19.1 20 19.0 10 18.9 0 09430-028 0 80 –40 –30 –20 –10 18.8 85 Data Sheet ADL5240 70 60 40 30 20 10 0 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 NOISE FIGURE (dB) 4.0 09430-032 PERCENTAGE (%) 50 Figure 33. AMP: Noise Figure Distribution at 2140 MHz Rev. A | Page 15 of 28 ADL5240 Data Sheet APPLICATIONS INFORMATION BASIC LAYOUT CONNECTIONS The basic connections for operating the ADL5240 are shown in Figure 34. SERIAL PARALLEL INTERFACE VDD VDD 0.1µF C8 3 100pF DSAIN 4 C6 VDD NC NC NC DSAIN 5 NC 6 NC 7 8 VDD NC ADL5240 DSAOUT NC NC NC AMPOUT/VCC NC NC NC NC AMPIN NC 1 2 SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6 32 31 30 29 28 27 26 25 NC NC NC NC 24 23 22 100pF DSAOUT 21 20 C7 19 18 17 9 10 11 12 13 14 15 16 0.1µF 0.1µF C2 AMPIN C1 L1 470nH C3 68pF C4 VCC 1.2nF C5 1µF Figure 34. Basic Connections Rev. A | Page 16 of 28 09430-033 AMPOUT Data Sheet ADL5240 Amplifier Bias The dc bias for the amplifier in ADL5240 is supplied through Inductor L1 and is connected to the AMPOUT pin. Three decoupling capacitors (C3, C4, and C5) are used to prevent RF signals from propagating onto the dc lines. The dc supply ranges from 4.75 V to 5.25 V and should be connected to the VCC test point on the evaluation board. Digital Step Attenuator Bias The bias for the DSA is provided through the VDD pin. At least one decoupling capacitor (C8) is recommended on the VDD trace. The voltage ranges from 4.75 V to 5.25 V and should be connected to the VDD test point on the evaluation board. The DSA is shown to work for dc voltages as low as 2.5 V. Amplifier RF Input Interface Pin 15 is the RF input for the amplifier of ADL5240. The amplifier is internally matched to 50 Ω at the input; therefore, no external components are required. Only a dc blocking capacitor (C1) is required. Amplifier RF Output Interface Pin 10 is the RF output for the amplifier of ADL5240. The amplifier is internally matched to 50 Ω at the output; therefore, no external components are required. Only a dc blocking capacitor (C2) is required. The bias is provided through this pin via a choke inductor. DSA RF Input Interface Pin 4 is the RF input for the DSA of ADL5240. The input impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C6) is required. DSA RF Output Interface Pin 21 is the RF output for the DSA of ADL5240. The output impedance of the DSA is close to 50 Ω over the entire frequency range; therefore, no external components are required. Only a dc blocking capacitor (C7) is required. DSA SPI Interface The DSA of the ADL5240 can operate in either serial or parallel mode. Pin 32 (SEL) controls the mode of operation. To select serial mode, connect SEL to ground; to select parallel mode, connect SEL to VDD. In parallel mode, Pin 25 to Pin 30 (D6 to D1) are the data bits, with D6 being the LSB. Connect Pin 31 (D0) to ground during the parallel mode of operation. In serial mode, Pin 29 is the latch enable (LE), Pin 30 is the data (DATA), and Pin 31 is the clock (CLK). Pin 26, Pin 27, and Pin 28 are not used in serial mode and should be connected to ground. Pin 25 (D6) should be connected to VDD during the serial mode of operation. To prevent noise from coupling onto the digital signals, an RC filter can be used on each data line. Rev. A | Page 17 of 28 ADL5240 Data Sheet SPI TIMING Table 4. Mode Selection Table Table 5 provides details about the timing characteristics for the SPI signals—namely, the clock (CLK), latch enable (LE), and data (DATA) signals—and Figure 35 shows the corresponding SPI timing diagram. Pin 32 (SEL) Connect to Ground Connect to Supply Functionality Serial mode Parallel mode SPI Timing Sequence Figure 36 is the timing sequence for the SPI function using a 6-bit operation. The clock can be as fast as 20 MHz. In serial mode, Register B5 (MSB) is first and Register B0 (LSB) is last. Table 5. SPI Timing Setup Limit 10 25 25 10 10 10 30 Unit MHz ns min ns min ns min ns min ns min ns min Test Conditions/Comments Data clock frequency Clock high time Clock low time Data to clock setup time Clock to data hold time Clock low to LE setup time LE pulse width t1 t3 t4 CLK DON'T CARE DATA DON'T CARE t5 t2 DON'T CARE MSB B5 B4 B3 B2 LSB B0 B1 DON'T CARE 09430-034 t6 LE Figure 35. SPI Timing Diagram (Data Is Loaded MSB First), Serial Mode D0/CLK DON'T CARE D1/DATA DON'T CARE DON'T CARE MSB B5 B4 B3 B2 B1 LSB B0 DON'T CARE D2/LE 09430-035 Parameter f CLK t1 t2 t3 t4 t5 t6 D6 Figure 36. SPI Timing Sequence, Serial Mode Rev. A | Page 18 of 28 Data Sheet ADL5240 Table 6. DSA Attenuation Truth Table—Serial Mode Attenuation State (dB) 0 (Reference) 0.5 1.0 2.0 4.0 8.0 16.0 31.5 B5 (MSB) 1 1 1 1 1 1 0 0 B4 1 1 1 1 1 0 1 0 B3 1 1 1 1 0 1 1 0 B2 1 1 1 0 1 1 1 0 B1 1 1 0 1 1 1 1 0 B0 (LSB) 1 0 1 1 1 1 1 0 D3 1 1 1 1 0 1 1 0 D4 1 1 1 0 1 1 1 0 D5 1 1 0 1 1 1 1 0 D6 (LSB) 1 0 1 1 1 1 1 0 Table 7. DSA Attenuation Truth Table—Parallel Mode Attenuation State (dB) 0 (Reference) 0.5 1.0 2.0 4.0 8.0 16.0 31.5 D1 (MSB) 1 1 1 1 1 1 0 0 D2 1 1 1 1 1 0 1 0 Rev. A | Page 19 of 28 ADL5240 Data Sheet LOOP PERFORMANCE The ADL5240 can be configured so that either the DSA precedes the amplifier (see Figure 37) or the amplifier precedes the DSA (see Figure 38). The performance of the loop configurations is presented in Figure 20 to Figure 27. To improve the overall return loss, a shunt capacitor can be placed between the amplifier and DSA. This helps to align the phases of the two blocks. SERIAL PARALLEL INTERFACE VDD VDD 0.1µF C7 2 3 100pF RFIN 4 5 C6 6 7 8 VDD VDD NC NC NC NC DSAIN ADL5240 NC DSAOUT NC NC NC NC AMPOUT/VCC NC NC NC NC AMPIN NC 1 SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6 32 31 30 29 28 27 26 25 NC NC NC NC 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 100pF 0.1µF C2 C1 L1 470nH C3 68pF C4 VCC 1.2nF C5 1µF Figure 37. DSA-AMP Loop Configuration Rev. A | Page 20 of 28 09430-036 RFOUT Data Sheet ADL5240 SERIAL PARALLEL INTERFACE VDD VDD C7 1 2 3 4 VDD NC NC NC DSAIN NC 6 NC 7 VDD NC 5 8 C2 100pF SEL D0/CLK D1/DATA D2/LE D3 D4 D5 D6 32 31 30 29 28 27 26 25 ADL5240 DSAOUT NC NC NC AMPOUT/VCC NC NC NC NC AMPIN NC NC NC NC NC 24 23 22 100pF RFOUT 21 20 C6 19 18 17 9 10 11 12 13 14 15 16 0.1µF RFIN C1 L1 470nH C3 68pF C4 VCC 1.2nF C5 1µF Figure 38. AMP-DSA Loop Configuration Rev. A | Page 21 of 28 09430-037 0.1µF ADL5240 Data Sheet AMPLIFIER DRIVE LEVEL FOR OPTIMUM ACLR THERMAL CONSIDERATIONS It is usually required to drive the amplifier as high as possible in order to maximize output power. However, properly driving Amplifier at the ADL5240 is required to achieve optimum ACLR performance. Once output power approaches P1dB and OIP3, there is ACLR degradation. The driving level of amplifier with a modulated signal should be backed off properly from P1dB by at least the amount of a signal crest factor for optimum ACLR. So assuming a gain and output P1dB of Amplifier at 2140 MHz are 19 dB and 19 dBm respectively, the output power, which is backed off by 11 dB crest factor at the modulated signal case, is 8 dBm. Therefore, the proper input driving level should be under −11 dBm. The ADL5240 is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP. The thermal resistance from junction to air (θJA) is 36.8o C/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 25 conductive, epoxy filled thermal vias. The thermal resistance from junction to case (θJC) is 6.9o C/W, where case is the exposed pad of the lead frame package. –30 –40 AMP_ADJ The ADL5240 consumes approximately 93 mA with a 5 V supply voltage. Even though the part dissipates less than 0.5 W, for the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The thermal resistance values given in this section assume a minimum of 25 thermal vias arranged in a 5 × 5 array with a diameter of 13 mils and a pitch of 25 mils. Figure 40 shows a close-up of the thermal via distribution under the exposed pad. ACPR (dBc) –50 –60 –70 –80 –30 –25 –20 PIN (dBm) –15 –10 –5 Figure 39. Single Carrier WCDMA Adjacent Chanel Power Ratio vs. Input Power at Amplifier, 2140 MHz 09430-038 –35 09430-101 AMP_ALT –90 –40 Figure 40. Exposed Pad with Thermal Via Distribution Rev. A | Page 22 of 28 Data Sheet ADL5240 EVALUATION BOARD The schematic of the ADL5240 evaluation board is shown in Figure 41, the evaluation board configuration options are detailed in Table 8, and the layout of the ADL5240 evaluation board is shown in Figure 43 and Figure 44. Each RF trace on the evaluation board has a characteristic impedance of 50 Ω and is fabricated on Rogers3003 material. In addition, each trace is a coplanar waveguide (CPWG) with a width of 25 mils, a spacing of 20 mils, and a dielectric thickness of 10 mils. The input to and output from the DSA and amplifier should be ac-coupled with capacitors of appropriate values to ensure the broadband performance. The bias to the amplifier is provided by connecting a choke to the AMPOUT pin. Bypassing capacitors are recommended on all supply lines to minimize the RF coupling. The DSA and the amplifier can be individually biased or connected to the VDD plane using Resistors R2 and R1. The ADL5240 can be operated in two ways: the amplifier can precede the DSA (AMP-DSA loop configuration) or the DSA can precede the amplifier (DSA-AMP loop configuration). The evaluation board can be configured to handle either option. In normal operation, R12 and R13 are open, and R10 and R11 are 0 Ω and are used to terminate any RF coupling onto the bypass trace. To configure the ADL5240 in AMP-DSA loop configuration, R12 should be replaced with a capacitor, R13 should be replaced with a 0 Ω resistor, and R10 and R11 should be left open. Similarly, to configure the ADL5240 in the DSA-AMP loop configuration, R16 should be replaced with a capacitor, R17 should be replaced with a 0 Ω resistor, and R14 and R15 should be left open. The digital signal traces incorporate a footprint for an RC filter to prevent potential noise from coupling onto the signal. In normal operation, series resistors are 0 Ω and shunt resistors and capacitors are open. The evaluation board is designed to control DSA in either parallel or serial mode by connecting the SEL pin to the supply or ground by a switch. For adjusting attenuation at DSA, the ADL5240 can be programmed in two ways: through the on-board USB interface from a PC USB port, or through an SDP board, which will become the Analog Devices common control board in the future. The on-board USB interface circuitry of the evaluation board is powered directly by the PC. USB based programming software is available to download from the ADL5240 product page at www.analog.com. Figure 45 shows the window of the programming software where the user selects serial or parallel mode for the attenuation adjustment at DSA. The selection of the mode in the window should match the mode of the evaluation board switch. It is highly recommended to refer the evaluation board layout for the optimal and stable performance of each block as well as for the improvement of thermal efficiency. Rev. A | Page 23 of 28 ADL5240 Data Sheet CLK_D0 S1 DATA_D1 3 1 2 LE_D2 D3 AGND VDD D4 RED D5 D6 R2 0 DNI 26 27 28 29 25 D6 D5 D4 D3 NC 24 23 22 C5 19 1 100pF R16 18 0 0 R11 0 AGND AMPOUT 3 2 NC R17 0 4 3 2 AGND 0 R15 0 DNI C8 AMPIN 1 R10 AGND 4 R14 DNI 16 AMPIN NC 15 NC 5 DNI 17 AGND AGND DSAOUT 21 20 DNI 14 9 R12 5 30 NC NC 10 4 D2/LE NC NC C1 100pF 3 ADL5240ACPZ NC NC 1 2 DSAOUT NC NC DSAIN NC DSAIN NC 8 NC NC 7 NC 13 6 VDD NC 12 4 5 U1 VDD 11 1 2 3 D1/DATA 32 EPAD AGND D0/CLK PAD C17 0.1µF 31 DNI SEL 0 AMPOUT/VCC VDD DNI 0.1µF AGND 5 DNI R13 0 C4 DNI AGND 1 0.1µF 2 3 4 5 AGND VCC RED L1 R1 0 2 DNI C13 C14 470nH C15 1µF 1200pF 68pF 1 09430-039 VDD AGND Figure 41. ADL5240 Evaluation Board Table 8. Evaluation Board Configuration Options Component C1, C2 C3, C4 C5, C6, C7 C8 L1 R1, R2 R10, R11, R14, R15 R12, R13, R16, R17 S1 Function/Notes Input/output dc blocking capacitors for DSA. Input/output dc blocking capacitors for AMP. Power supply decoupling for amplifier. The bias associated with the AMPOUT pin is the most sensitive to noise because the bias is connected directly to the output. The smallest capacitor (C7) should be the closest to the AMPOUT pin. Power supply decoupling for the DSA. The bias for the amplifier comes through L1 when VCC is connected to a 5 V supply. L1 should be high impedance for the frequency of operation while providing low resistance for the dc current. Resistors to connect the supply for the amplifier and the DSA to the same VDD plane. These resistors are used to terminate RF coupling onto the traces and to close the loop. R12 and R16 are replaced with capacitors, and R13 and R17 are replaced with 0 Ω to close the loop. Switch to change between the serial mode and parallel mode of operation. Connect to supply for parallel mode and to ground for serial mode operation. Rev. A | Page 24 of 28 Default Value C1, C2 = 100 pF C3, C4 = 0.1 µF C5 = 1 µF C6 = 1.2 nF C7 = 68 pF C8 = 0.1 µF L1 = 470 nH R1, R2 = open R10, R11, R14, R15 = 0Ω R12, R13, R16, R17 = open S1 connected to ground D1 C37 1µF A C SML-210MTT86 R4 2kΩ U3 DGND 7 1 IN1 OUT1 8 2 OUT2 IN2 6 3 FB SD_N PAD GND PAD 5 ADP3334ACPZ DGND C35 0.1µF DGND 3V3_USB R3 78.7kΩ FB C44 1000pF C36 0.1µF R9 140kΩ IN IN IN IN R45 2kΩ C38 0.1µF WAKEUP RESETN SCL SDA C47 1µF Rev. A | Page 25 of 28 Figure 42. USB/SDP Interface Circuitry on the Customer Evaluation Board R18 100kΩ LE_D2 R44 100kΩ R43 TBD0603 DNI CLK_D0 DATA_D1 DGND1 BLK DGND 1 AGND DGND 0Ω R46 0Ω R17 0Ω R42 0Ω R6 DNI DNI DNI C45 0.1µF DECOUPLING FOR U1 C39 0.1µF C33 0.1µF 1 2 3 6 7 8 DGND U5 0Ω R22 0Ω R21 C46 0.1µF DGND DNI C49 0.1µF R47 100kΩ R5 2kΩ C48 0.1µF DGND DGND A0 VCC A1 5 A2 SDA SCL WP 24LC32A-I/MS VSS E014160 4 JEDEC_TYPE=MSOP8 U2 8 VCC A0 A1 A2 5 SCL SDA WC_N GND 4 24LC64-I-SN DGND 1 2 3 6 7 C9 10pF D6 D5 D4 D3 C34 0.1µF R7 100kΩ DNI AGND RDY0_SLRD RDY1_SLWR WAKEUP RESERVED XTALIN RESET_N SCL SDA P2 DGND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 FX8-120S-SV(21) DGND 1 2 44 14 5 42 15 16 AVCC C50 0.1µF C31 10pF GND 1 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 DGND P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 FX8-120S-SV(21) 5V_SDP RED (FROM MAIN BOARD; 200mA MINIMUM) 5V_SDP PA7 1 2kΩ R8 OUT IFCLK CLKOUT CTL0_FLAGA CTL1_FLAGB CTL2_FLAGC C51 22pF XTALOUT XTALIN CR2 3 A C SML-210MTT86 DM DP CASE 2 4 Y1 24.000000MHZ CY7C68013A-56LTXC E013815 JEDEC_TYPE=QFN56_8X8_PAD5_2X4_5 PB0_FD0 PB1_FD1 PB2_FD2 PB3_FD3 PB4_FD4 PB5_FD5 PB6_FD6 PB7_FD7 PD0_FD8 PD1_FD9 PD2_FD10 PD3_FD11 PD4_FD12 PD5_FD13 PD6_FD14 PD7_FD15 PAD 33 34 35 36 37 38 39 40 4 8 9 13 54 29 30 31 U4 XTALOUT DPLUS DMINUS IFCLK CLKOUT CTL0_FLAGA CTL1_FLAGB CTL2_FLAGC VCC DGND PA0_INT0_N PA1_INT1_N PA2_SLOE PA3_WU2 PA4_FIFOADR0 PA5_FIFOADR1 PA6_PKTEND PA7_FLAGD_SLCS_N 17 28 3 6 27 41 11 26 32 53 7 10 43 56 IO 12 55 PAD 5V_USB DGND OUT PB0 DGND DGND C52 22pF CLK_D0 D3 D4 D5 D6 LE_D2 DATA_D1 DGND OUT OUT OUT OUT OUT OUT OUT 0Ω R25 0Ω R23 0Ω R20 0Ω R19 0Ω R24 0Ω 0Ω R54 GND PINS P1 DGND R29 1.00kΩ DNI DGND R28 1.00kΩ DNI DGND R27 1.00kΩ DNI DGND R26 1.00kΩ DNI R55 1.00kΩ DNI C19 330pF DNI C18 330pF DNI C16 330pF DNI C12 330pF DNI C53 330pF DNI 897-43-005-00-100001 G1 G2 G3 G4 1 2 3 4 5 TSW-105-08-G-D DNI PLACEHOLDER DGND P3 R53 PA0 PA1 PA2 PA3 PA4 PA5 PA6 5V_USB 1 2 3 4 5 6 7 8 9 10 R13 1.00kΩ DNI C55 330pF DNI DGND R14 1.00kΩ DNI D6 D5 D4 D3 C56 330pF DNI CLK_D0 DATA_D1 LE_D2 09430-102 3V3_USB Data Sheet ADL5240 09430-040 Data Sheet 09430-040 ADL5240 Figure 43. Evaluation Board Layout—Top Figure 44. Evaluation Board Layout—Bottom Rev. A | Page 26 of 28 ADL5240 09430-103 Data Sheet Figure 45. Evaluation Board Control Software Rev. A | Page 27 of 28 ADL5240 Data Sheet OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 32 1 24 0.50 BSC 3.45 3.30 SQ 3.15 EXPOSED PAD 17 TOP VIEW 1.00 0.85 0.80 SEATING PLANE 0.80 MAX 0.65 TYP 12° MAX 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.25 0.18 8 16 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 05-23-2012-A 4.75 BSC SQ PIN 1 INDICATOR PIN 1 INDICATOR Figure 46. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5240ACPZ-R7 ADL5240-EVALZ 1 Temperature Range −40°C to +85°C Package Description 32 Lead LFCSP_VQ, 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09430-0-6/13(A) Rev. A | Page 28 of 28 Package Option CP-32-3