Collin Wells, Reza Abdullah
TI Precision Designs: Verified Design
Combined Voltage and Current Output Terminal for
Analog Outputs (AO) in Industrial Applications
TI Precision Designs
Circuit Description
TI Precision Designs are analog solutions created by
TI’s analog experts. Verified Designs offer the theory,
part selection, simulation, complete PCB schematic &
layout, bill of materials, and measured performance of
useful circuits. Circuit modifications that help to meet
alternate design goals are also discussed.
Standard industrial analog output (AO) circuits are
dedicated to either voltage or current outputs. This
design using the DAC8760 can output both the
standard industrial voltage and current outputs on a
single terminal, thus reducing the number of terminals
needed from three to two. A combined output
succeeds in reducing the wiring cost, connector
count, and increasing the versatility of the AO design.
The possible outputs of the design include: 4-20 mA,
0-20 mA, 0-24 mA, 0-5 V, 0-10 V, +/-5 V, +/-10 V, as
well as voltage over-ranges.
Design Resources
Design Archive
TINA-TI™
DAC8760
OPA192
Ask The Analog Experts
WEBENCH® Design Center
TI Precision Designs Library
All Design files
SPICE Simulator
Product Folder
Product Folder
+15V
Isolation
Barrier
0.1 μF
0.1uF
4.7uF
0.1uF
0.1uF
0.1uF
100 pF
+15V -15V
0.1uF
4.7uF
+
+5V
0.1uF
VDD
Digital
Controller
MOSI
OPA192
100 pF
DVDD DVDD
Select
VCC1
VCC2
INA
OUTA
/CS
INB
SCLK
INC
ISO7641
LATCH
OUTC
SCLK
SDO
OUTD
IND
GND
GND1
GND2
0.1 μF
DNI
DIN
OUTB
MISO
AVDD AVSS
+VSENSE
CMP
VOUT
DAC8760
-15V
+/-10V, 0-10V, +/-5V, 0-5V,
4-20mA, 0-20mA, 0-24mA
VOUT / IOUT
-VSENSE
IOUT
HART-IN
GND REFOUT REFIN
RTN
22nF
0.1uF
TINA-TI is a trademark of Texas Instruments
WEBENCH is a registered trademark of Texas Instruments
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
1
www.ti.com
1
Design Summary
The design requirements are as follows:
Supply Voltage: +/-15 V
Digital Input: 4-Wire SPI
Digital Isolation: 4 kV
Resolution: 16-Bit
Voltage Output: +/-10 V, with 10% over-range option
Current Output: 0 mA – 24 mA
Temperature: 25 °C
The design goals and performance are summarized in Table 1. Figure 1 depicts the dc transfer function of
the design measured in both voltage and current output modes.
Table 1. Comparison of Design Goals, Simulated, and Measured Performance
Warning! Do not move,
alter,Do
violate,
or
Warning!
not move
delete red bounding
box or
warning!
delete
redthis
bounding
bo
Goals
Calculated
Measured
Current (0-24 mA)
TUE (%FSR)
0.1%
0.02
0.048
Voltage (+/-10 V)
TUE (%FSR)
0.1%
0.015
0.014
10
24
+/-10 V
0-24 mA
8
20
6
Output Current (mA)
Output Voltage (V)
4
2
0
-2
-4
16
12
8
-6
4
-8
-10
0
0
20000
40000
60000 65535
0
20000
Input Code
40000
60000 65535
Input Code
C004
C004
Figure 1: Measured dc Transfer Function
Warning! Do not move,
alter,Do
violate,
or
Warning!
not move
delete red bounding
box or
warning!
delete
redthis
bounding
bo
2
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
2
Theory of Operation
Figure 2 displays a simplified version of the circuitry inside the DAC8760 that is used to create a combined
voltage and current (V+I) output driver. A 0 V to 5 V digital-to-analog converter (DAC) drives the inputs for
both the voltage (VOUT) and current (IOUT) output stages. The DAC requires an accurate, low-drift reference
voltage (VREF) to deliver strong dc performance, along with a voltage regulator (VREG) to drop the analog
supply, AVDD, down to +5 V for the low-voltage analog and digital circuitry.
Isolation
Barrier
Simplified DAC8760 Output Block Diagram
+5 V
AVDD
AVDD
VREG
RS2
RS3
AVDD
+
AVDD
+
VISO
Digital
Controller
+5 V
Digital
Isolator
+5 V
Q2
AVSS
Q1
A1
A2
IOUT
AVSS
RSET
DAC
AVDD
+
A3
VOUT / IOUT
VOUT
AVSS
RLOAD
+5 V
AVDD
RG2
RF
VREF
VOUT
Range
Scaling
+VSENSE
A4
+
AVSS
RTN
OPA192
RG1
-VSENSE
Figure 2: Circuit Schematic
2.1
IOUT Circuitry
The IOUT circuit is composed of amplifiers A1 and A2, MOSFETs Q1 and Q1, and the three current sensing
resistors, RSET, RS2, and RS3. The two-stage current source enables the GND referenced DAC output to
drive the high-side amplifier required for the current-source. For detailed design information on the design
of a high-side voltage-to-current output stage, please refer to TIPD502.
When VOUT is active, Q2 is kept in a high-impedance state and does not negatively affect the VOUT circuit
performance. Refer to SBAA199 for a more detailed investigation of the effects that occur when creating a
combined voltage and current output driver with the DACx760 family.
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
3
www.ti.com
2.2
VOUT Circuitry
The VOUT circuit is composed of amplifiers A3, A4, and the feedback network around A3 consisting of RF,
RG1, and RG2. A3 operates as a modified summing amplifier where the DAC controls the non-inverting
input and the inverting input has one path to GND and a second to VREF. This configuration allows the
single ended 0-5 V DAC to create both the unipolar 0-5 V and 0-10 V outputs and the bi-polar +/-5 V and
+/-10 V outputs. A resistor switching network is used to change the values of R G1 and RG2 depending on
the selected voltage output range.
A4 is used to buffer the resistive feedback network of A3 so the feedback resistors do not present a
resistive load on the IOUT circuitry which would reduce the current delivered to the load. A4 is therefore
inside the feedback loop of A3 and contributes directly to errors of the voltage output stage. In a buffer
configuration the gain and linearity errors will be negligible but the offset voltage will add directly to the
VOUT circuit offset voltage.
2.3
Digital Isolation
Most AO modules require isolation from the backplane and other AO modules. This is typically
accomplished by isolating the digital signals between the host processor/controller and the DAC in the AO
circuit. There are many topologies available to achieve the isolation but galvanic (capacitive) isolation has
many advantages over other topologies and will be selected for this design.
3
Component Selection
A detailed schematic for the design with the final components is shown in Figure 3.
+15V
Isolation
Barrier
0.1 μF
0.1uF
4.7uF
0.1uF
0.1uF
0.1uF
100 pF
+15V -15V
0.1uF
4.7uF
+
+5V
0.1uF
VDD
Digital
Controller
MOSI
OPA192
100 pF
DVDD DVDD
Select
VCC1
VCC2
INA
OUTA
/CS
INB
SCLK
INC
ISO7641
LATCH
OUTC
SCLK
SDO
MISO
OUTD
GND
GND1
GND2
0.1 μF
DNI
DIN
OUTB
IND
AVDD AVSS
+VSENSE
CMP
-15V
VOUT
DAC8760
+/-10V, 0-10V, +/-5V, 0-5V,
4-20mA, 0-20mA, 0-24mA
VOUT / IOUT
-VSENSE
IOUT
HART-IN
GND REFOUT REFIN
RTN
22nF
0.1uF
Figure 3: Complete Schematic for Combined V+I Analog Output
3.1
DAC – DAC8760
The DAC8760 includes the DAC, amplifiers A1, A2, and A3, VREG, VREF, and all of the switches, transistors,
and resistors required to create a configurable integrated solution for industrial voltage and current output
drivers. The DAC8760 features a max 0.1% full-scale range (FSR) total-unadjusted-error (TUE)
specification, which includes offset error, gain error, and integral non-linearity (INL) errors at 25°C. The
0.1% FSR TUE is valid for all of the voltage and current output stages providing a baseline for the final
system accuracy. The max differential non-linearity (DNL) specification of +/-1 least significant bit (LSB)
provides fully monotonic operation for both VOUT and IOUT.
4
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
The integral non-linearity (INL) specifications of 0.022% FSR for VOUT and 0.024% FSR for IOUT
demonstrate high linearity and accuracy. The integrated VREF circuit provides a low temperature drift
reference for the DAC, specified at 10 ppm/°C. The 4-wire SPI communication bus features a daisy-chain
option that allows multiple DAC8760 devices to be controlled through a single 4-channel digital isolator,
enabling a group-isolated multiple output system.
Another integrated option is the 12-bit DAC7760. For discrete options refer to Section 7.
3.2
Amplifier Selection – OPA192
The buffer amplifier becomes a part of the feedback network of the DAC8760 VOUT circuit and any dc
errors will directly contribute to the final VOUT accuracy. An amplifier with low offset voltage (VOS), low VOS
drift (VOS(DRIFT)), high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR)
will help keep the error contribution of the amplifier as low as possible. A JFET, CMOS, or low input bias
current BJT input topology amplifier should be used to prevent the input bias current from affecting the IOUT
TM
circuit. The OPA192 was chosen for its precision e-trim topology that achieves 5uV typical, 25 uV max,
VOS and 0.2 uV/°C typical, 0.5 uV/°C max VOS(DRIFT) without the use of chopping or other switching offset
cancellation techniques. The rail-to-rail CMOS input stage features a typical CMRR of 110 dB and a typical
PSRR of 0.5 μV/V over the full supply range of +4 V to +36 V. The CMOS inputs result in a maximum input
bias current (iB) of 20pA which will not noticeably affect the IOUT circuit performance. A bandwidth of 10
MHz, slew rate of 20 V/μs, and 0.01% settling time of 1 μs keeps the amplifier from limiting system
bandwidth. The rail-to-rail output and output current drive capabilities allow for good swing to GND if
operated in a single-supply configuration.
3.3
Digital Isolator – ISO7641
The four serial data signals required to communicate bi-directionally with the DAC8760 are SCLK, DIN,
SDO, and LATCH. In order to maintain isolation from the host controller, these signals must be isolated
through a digital isolator. The ISO7641 is a 25 MBPS digital isolator that features >4 kV galvanic isolation.
3.4
Passive Component Selection
Although it was not tested in this design, a footprint was included for an external R SET resistor (R1). Unless
the RSET resistor is populated, there are not any passive components that require high precision for this
design. If an external RSET resistor is used with this design then it should be chosen for high accuracy and
low temperature coefficient.
The voltage compensation capacitor, CCOMP, was not installed for this design because the output
capacitive load was very small. If capacitive load drive capabilities are required then C COMP will need to be
installed and sized based on the DACx760 datasheet requirements. All capacitors in the signal path should
be sized for a voltage coefficient that well exceeds the voltage that will be placed across them to keep the
capacitance values constant during. Use C0G/NP0 dielectric capacitors when possible and X7R when
C0G/NP0 are not available.
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
5
www.ti.com
4
Circuit Performance Calculations
4.1
IOUT Accuracy
The IOUT circuit performance is based on the specifications of the DAC8760. The small 20 pA iB current of
the OPA192, shown in Figure 4, is lower than the output noise of the DAC8760 and will not negatively
affect the output. The expected performance can be calculated based on the specifications in the product
datasheet that are shown in Figure 5.
Figure 4: OPA192 iB Specification
Figure 5: DAC8760 DC IOUT Specifications
Based on the product specifications, the expected output performance for the IOUT circuit at room
temperature (25°C) is displayed in Table 2.
Table 2. Calculated IOUT Circuit Performance
Current (0-24 mA)
4.2
Goals
Calculated
Offset (%FSR)
N/A
+/-0.01
Gain Error (%FSR)
N/A
+/-0.01
INL (%FSR)
N/A
+/-0.024
TUE (%FSR)
0.1%
+/-0.02
VOUT Accuracy
The op amp is included within the feedback loop of the DAC8760 VOUT circuit. Therefore the op amp errors
combine with the errors of the DAC8760 for the final VOUT error. In a buffer configuration, the high openloop gain of the OPA192 won’t contribute any significant gain or linearity errors. The OPA192 offset
voltage and CMRR specifications are shown in Figure 6. Since the OPA192 is in a buffer configuration, the
common-mode voltage changes with the input signal and will cause additional offset voltage. The worstcase will be at the +10V and -10V levels resulting the total offset voltage calculated in Equation 1. The
OPA192 offset voltage will directly add to the bipolar zero offset voltage of the DAC8760, shown in Figure
7.
6
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
110
VOS _ OPA192 VOS VOS _ CMRR 5 V 10V / 10 20 36.62 V
(1)
Figure 6: OPA192 Specifications
Figure 7: DAC8760 VOUT Specifications
Since the two offset voltages are uncorrelated, a probable total offset error can be calculated by taking the
root of the sum of squares (RSS) of their individual offset voltages, as shown in the equations below.
VOS _ TOTAL ( VOS _ OPA192 ) 2 ( VOS _ DAC8760 ) 2 (0.0366 mV) 2 (1 mV) 2 1 mV
(2)
Based on the product specifications, the expected output performance for the VOUT circuit at room
temperature is displayed in Table 3.
Table 3. Calculated VOUT Circuit Performance
Voltage (+/-10 V)
Goals
Calculated
Offset (mV)
N/A
+/-1
Gain Error (%FSR)
N/A
+/-0.01
INL (%FSR)
N/A
+/-0.022
TUE (%FSR)
0.1%
+/-0.015
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
7
www.ti.com
5
PCB Design
The PCB schematic and bill of materials can be found in Appendix A.1.
5.1
PCB Layout
For optimal performance of this design follow standard precision PCB layout guidelines, including proper
decoupling very close to all mixed signal integrated circuits and providing adequate power and GND
connections with large copper pours. The +VSENSE signal routed directly from the output terminal to
reduce errors from PCB wiring resistance that would be present if it was connected to VOUT before the
output terminal. The layout for the design is shown in Figure 8.
Figure 8: Altium PCB Layout
8
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
6
Verification and Measured Performance
6.1
IOUT Circuit
DC transfer function data for the IOUT circuit in 0-24 mA mode was collected using an 8.5 digit multi-meter
to measure the output of the circuit while driving a 300 Ω load with +/-15 V supplies. The measurement
results are shown in Table 4, Figure 9, and Figure 10. IOUT data for a single-supply 0-24 mA output can be
found in Appendix B.2.
Table 4. Measured IOUT Circuit Performance
Warning! Do not move, alter, violate, or
delete red bounding box or this warning!
Current (0-24 mA)
Goals
Calculated
Measured
Offset (%FSR)
N/A
+/-0.01
0.0054
Gain Error (%FSR)
N/A
+/-0.01
0.039
INL (%FSR)
N/A
+/-0.024
0.009
TUE (%FSR)
0.1%
+/-0.02
0.048
24
0-24 mA
Output Current (mA)
20
16
12
8
4
0
0
10000
20000
30000
40000
50000
60000
65535
Input Code
C003
Figure 9. IOUT Circuit 0-24 mA Output Transfer Function
Warning! Do not move, alter, violate, or
delete red bounding box or this warning!
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
9
Warning! Do not move,
alter, violate,
Warning!
Do not or
move
delete red bounding box
or red
this bounding
warning! bo
delete
www.ti.com
2.000E-05
2.400E-02
0-24 mA
0-24 mA
2.400E-02
Output Current (A)
Output Current (A)
1.500E-05
1.000E-05
5.000E-06
2.399E-02
2.399E-02
0.000E+00
0
10
20
30
40
50
2.398E-02
65485
65495
Input Code
65505
65515
65525
65535
Input Code
C001
C002
Figure 10. 0-24 mA Zero-Scale and Full-Scale Outputs
6.2
Warning! Do not move,
alter, violate,
Warning!
Do not or
move
delete red bounding box
or red
this bounding
warning! bo
delete
VOUT Circuit
DC transfer function data for the VOUT circuit in +/-10V mode was collected using an 8.5 digit multi-meter to
measure the output of the circuit while driving a 1 kΩ load with +/-15 V supplies. VOUT data for a singlesupply 0-10V output can be found in Appendix B.3.
Table 5. Measured VOUT Circuit Performance
Warning! Do not move, alter, violate, or
delete red bounding box or this warning!
Goals
Voltage (+/-10 V)
Calculated
Measured
Offset (mV)
N/A
+/-1
0.61
Gain Error (%FSR)
N/A
+/-0.01
0.023
INL (%FSR)
N/A
+/-0.022
0.007
TUE (%FSR)
0.1%
+/-0.015
0.014
10
8
6
Output Voltage (V)
4
2
0
-2
+/-10 V
-4
-6
-8
-10
0
10000
20000
30000
40000
50000
60000
65535
Input Code
C003
Figure 11. VOUT +/-10 V Output Transfer Function
10
Warning! Do not move, alter, violate, or
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
Warning! Do not move,
alter, Do
violate,
or
Warning!
not move
delete red boundingdelete
box orred
thisbounding
warning!bo
www.ti.com
10
-9.982
+/-10 V
-9.984
9.998
-9.986
9.996
-9.988
9.994
Output Voltage (V)
Output Voltage (V)
+/-10 V
-9.99
-9.992
9.992
9.99
-9.994
9.988
-9.996
9.986
-9.998
9.984
-10
0
10
20
30
40
50
9.982
65485
65495
65505
65515
65525
65535
Input Code
Input Code
C002
C001
Figure 12. +/-10 V Zero-Scale and Full-Scale Outputs
6.3
Warning! Do not move,
alter, Do
violate,
or
Warning!
not move
delete red boundingdelete
box orred
thisbounding
warning!bo
Measured Result Summary
The measured results are summarized and compared against the design goals and calculations in Table
6.
Table 6: Measured Result Summary
Current
Voltage
7
Goals
Calculated
Measured
Offset (mV)
N/A
+/-0.01
0.0054
Gain Error
N/A
+/-0.01
0.039
INL
N/A
+/-0.024
0.009
TUE
0.1%
+/-0.02
0.048
Offset (mV)
N/A
+/-1
0.61
Gain Error
N/A
+/-0.01
0.023
INL
N/A
+/-0.022
0.007
TUE
0.1%
+/-0.015
0.014
Modifications
The DAC7760 is the 12-bit equivalent to the DAC8760 and can be directly substituted for applications
where 16-bit resolution is not required. Another option for a combined output is to use a discrete DAC,
such as a DAC856x device, and the XTR300 output driver.
For designs that only require IOUT, the DACx750 family offers 12-bit and 16-bit integrated solutions. A
DAC856x device and the XTR111 output driver can be used for a discrete current only solution.
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
11
www.ti.com
Any +36 V op amp can be used as the buffer amplifier in this design. However, as mentioned in Section
3.2, dc errors from the op amp combine with the dc errors of the DAC affecting the VOUT performance.
Therefore, selecting an op amp with low offset voltage, low offset drift, high CMRR, and high PSRR will
TM
prevent the op amp from reducing the performance of the DAC. The OPA192 is a precision e-trim device
TM
and other devices in this family will work well in this application. Devices in the zero-drift offset
cancellation series such as the OPA188 are also very good options for the best drift and offset
performance. Other +36 V amplifiers for this application are the OPA277, OPA170, or OPA140. Op amps
for single-supply applications must have input and output stages that include the negative rail for proper
operation.
Table 7: Alternate +36V Amplifiers
Amplifier
Typical
Offset
Voltage
(μV)
Max Offset
Voltage
Over Temp
(μV)
Typical
Offset
Drift
(μV/°C)
Min
CMRR
(dB)
Max
PSRR
(μV/V)
Max
Input
Bias
Current
(pA)
Min Aol
(dB)
Noise at 1
kHz
(nV/√Hz)
Quiescent
Current
(mA)
OPA192
10
150
0.2
110
3
20
110
5.5
1
0.425
OPA188
6
33.5
0.03
114
0.3
1400
120
8.8
OPA277*
10
30*
0.1*
130*
0.5*
2800
126*
8
0.79
OPA170
250
2
0.3
104
5
15
110
19
0.110
OPA140
30
220
0.35
126
0.5
10
120
5.1
1.8
*OPA277 is only rated to +85°C where the other devices are rated to +125°C.
8
About the Authors
Collin Wells is an applications engineer in the Precision Linear group at Texas Instruments where he
supports industrial products and applications. Collin received his BSEE from the University of Texas,
Dallas.
Reza Abdullah is a characterization engineer in the Precision DAC group at Texas Instruments. Reza
received his MSEE from Texas A&M University, College Station and his BSEE from Kwame Nkrumah
University of Science & Technology in Kumasi, Ghana.
9
Acknowledgements & References
1.
12
Collin Wells, Reza Abdullah, “Creating a Combined Voltage and Current Output with the DACx760”
SBAA199, October 2013.
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Appendix A.
A.1 Electrical Schematic
The Altium electrical schematic for this design can be seen in Figure 13.
Figure 13: Altium Schematic
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
13
www.ti.com
A.2 Bill of Materials
The bill of materials for this circuit can be seen in Figure 14.
Figure 14: Bill of Materials
14
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
www.ti.com
Appendix B.
B.1 Single-Supply Result Summary
Table 8: Measured Result Summary
Current
Voltage
Goals
Calculated
Measured
Offset (mV)
N/A
+/-0.01
0.005
Gain Error
N/A
+/-0.01
0.037
INL
N/A
+/-0.024
0.009
TUE
0.1%
+/-0.02
0.048
Offset (mV)
N/A
+/-1
0.07
Warning! Do not move, alter, violate, or
delete red bounding box or this warning!
Gain Error
N/A
+/-0.01
0.024
INL
N/A
+/-0.022
0.006
TUE
0.1%
+/-0.015
0.026
B.2 Single-Supply 0-24 mA IOUT Results
24
0-24 mA
Output Current (mA)
20
16
12
8
4
0
0
10000
20000
30000
40000
50000
60000
65535
Input Code
Figure 15. Single-Supply IOUT 0-24 mA Output Transfer Function
C003
Warning! Do not move, alter, violate, or
delete red bounding box or this warning!
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
15
Warning! Do not move,
alter, violate,
Warning!
Do not or
move,
delete red bounding box
or red
this bounding
warning! bo
delete
www.ti.com
2.000E-05
2.400E-02
0-24 mA
0-24 mA
2.400E-02
Output Current (A)
Output Current (A)
1.500E-05
1.000E-05
5.000E-06
2.399E-02
2.399E-02
0.000E+00
0
10
20
30
40
2.398E-02
65485
50
65495
Input Code
65505
65515
65525
65535
Input Code
C001
C002
Warning! Do not move, alter, violate, or
Warning! Do not move,
alter, violate,
Do not or
move,
delete
red bounding Warning!
box
or this
warning!
Figure 16. Single-Supply IOUT 0-24 mA Zero-Scale and Full-Scale Outputs
B.3 Single-Supply 0-10V Results
delete red bounding box
or red
this bounding
warning! bo
delete
10
9
8
Output Voltage (V)
7
6
5
4
0-10 V
3
2
1
0
0
10000
20000
30000
40000
50000
60000
65535
Input Code
C003
Figure 17. 0-10V Output Transfer Function
Warning! Do not move, alter, violate, or
delete red bounding box or this warning!
16
Combined Voltage and Current Output Terminal for Analog Outputs
SLAU119-December 2013-Revised December 2013
Copyright © 2013, Texas Instruments Incorporated
Warning! Do not move,
alter, violate,
or
Warning!
Do not move
delete red bounding delete
box orred
thisbounding
warning! bo
www.ti.com
65535
0.035
10
0-10 V
0.03
9.998
0.025
9.996
Output Voltage (V)
Output Voltage (V)
0-10 V
0.02
0.015
9.994
9.992
0.01
9.99
0.005
9.988
0
0
50
100
150
200
9.986
65485
Input Code
65495
65505
65515
65525
65535
Input Code
C001
C002
Figure 18. Single-Supply VOUT Circuit 0-10 V Zero-Scale and Full-Scale Outputs
Warning! Do not move,
alter, violate,
or
Warning!
Do not move
delete red bounding delete
box orred
thisbounding
warning! bo
SLAU119-December 2013-Revised December 2013
Combined Voltage and Current Output Terminal for Analog Outputs
Copyright © 2013, Texas Instruments Incorporated
17
IMPORTANT NOTICE FOR TI REFERENCE DESIGNS
Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that
incorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remains
responsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products.
TI reference designs have been created using standard laboratory conditions and engineering practices. TI has not conducted any
testing other than that specifically described in the published documentation for a particular reference design. TI may make
corrections, enhancements, improvements and other changes to its reference designs.
Buyers are authorized to use TI reference designs with the TI component(s) identified in each particular reference design and to modify the
reference design in the development of their end products. HOWEVER, NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL
OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY THIRD PARTY TECHNOLOGY
OR INTELLECTUAL PROPERTY RIGHT, IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right,
or other intellectual property right relating to any combination, machine, or process in which TI components or services are used.
Information published by TI regarding third-party products or services does not constitute a license to use such products or services, or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
TI REFERENCE DESIGNS ARE PROVIDED "AS IS". TI MAKES NO WARRANTIES OR REPRESENTATIONS WITH REGARD TO THE
REFERENCE DESIGNS OR USE OF THE REFERENCE DESIGNS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING ACCURACY OR
COMPLETENESS. TI DISCLAIMS ANY WARRANTY OF TITLE AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT, QUIET POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY
INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO TI REFERENCE DESIGNS OR USE THEREOF. TI SHALL NOT BE LIABLE
FOR AND SHALL NOT DEFEND OR INDEMNIFY BUYERS AGAINST ANY THIRD PARTY INFRINGEMENT CLAIM THAT RELATES TO
OR IS BASED ON A COMBINATION OF COMPONENTS PROVIDED IN A TI REFERENCE DESIGN. IN NO EVENT SHALL TI BE
LIABLE FOR ANY ACTUAL, SPECIAL, INCIDENTAL, CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY
THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN
ANY WAY OUT OF TI REFERENCE DESIGNS OR BUYER’S USE OF TI REFERENCE DESIGNS.
TI reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per
JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant
information before placing orders and should verify that such information is current and complete. All semiconductor products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques for TI components are used to the extent TI
deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not
necessarily performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
Reproduction of significant portions of TI information in TI data books, data sheets or reference designs is permissible only if reproduction is
without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for
such altered documentation. Information of third parties may be subject to additional restrictions.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards that
anticipate dangerous failures, monitor failures and their consequences, lessen the likelihood of dangerous failures and take appropriate
remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in
Buyer’s safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed an agreement specifically governing such use.
Only those TI components that TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components that
have not been so designated is solely at Buyer's risk, and Buyer is solely responsible for compliance with all legal and regulatory
requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated