INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 Precision, 200-µA Supply Current, 2.7-V to 36-V Supply Instrumentation Amplifier with Rail-to-Rail Output Check for Samples: INA826 FEATURES DESCRIPTION • Input Common-Mode Range: Includes V– • Common-Mode Rejection: – 104 dB, min (G = 10) – 100 dB, min at 5 kHz (G = 10) • Power-Supply Rejection: 100 dB, min (G = 1) • Low Offset Voltage: 150 µV, max • Gain Drift: 1 ppm/°C (G = 1), 35 ppm/°C (G > 1) • Noise: 18 nV/√Hz, G ≥ 100 • Bandwidth: 1 MHz (G = 1), 60 kHz (G = 100) • Inputs Protected up to ±40 V • Rail-to-Rail Output • Supply Current: 200 µA • Supply Range: – Single Supply: +2.7 V to +36 V – Dual Supply: ±1.35 V to ±18 V • Specified Temperature Range: –40°C to +125°C • Packages: MSOP-8, SO-8 and DFN-8 The INA826 is a low-cost instrumentation amplifier that offers extremely low power consumption and operates over a very wide single or dual supply range. A single external resistor sets any gain from 1 to 1000. It offers excellent stability over temperature, even at G > 1, as a result of the low gain drift of only 35 ppm/°C (max). 1 234 APPLICATIONS • • • • • • • The INA826 is optimized to provide excellent common-mode rejection ratio of over 100 dB (G = 10) over frequencies up to 5 kHz. In G = 1, the commonmode rejection ratio exceeds 84 dB across the full input common-mode range from the negative supply all the way up to 1 V of the positive supply. Using a rail-to-rail output, the INA826 is well-suited for low voltage operation from a 2.7 V single supply as well as dual supplies up to ±18 V. Additional circuitry protects the inputs against overvoltage of up to ±40 V beyond the power supplies by limiting the input currents to less than 8 mA. The INA826 is available in SO-8, MSOP-8, and tiny 3-mm × 3-mm DFN-8 surface-mount packages. All versions are specified for the –40°C to +125°C temperature range. Industrial Process Controls Circuit Breakers Battery Testers ECG Amplifiers Power Automation Medical Instrumentation Portable Instrumentation RELATED PRODUCTS DEVICE DESCRIPTION INA333 25-µV VOS, 0.1 µV/°C VOS drift, 1.8-V to 5-V, RRO, 50-µA IQ, chopper-stabilized INA PGA280 20-mV to ±10-V programmable gain IA with 3-V or 5-V differential output; analog supply up to ±18 V INA159 G = 0.2 V differential amplifier for ±10-V to 3-V and 5-V conversion PGA112 Precision programmable gain op amp with SPI™ interface -IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 -VS MSOP-8, SO-8 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING MSOP-8 DGK IPDI SO-8 D I826 DFN-8 DRG IPEI INA826 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) INA826 UNIT Supply voltage ±20 V Input voltage range ±40 V REF input ±20 Output short-circuit (2) V Continuous Operating temperature range, TA –50 to +150 °C Storage temperature range, TA –65 to +150 °C +175 °C Human body model (HBM) 2500 V Charged device model (CDM) 1500 V Machine model (MM) 150 V Junction temperature, TJ ESD rating (1) (2) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Short-circuit to VS/2. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INA826 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTI 40 150 vs temperature, TA = –40°C to +125°C 0.4 2 RTI 200 700 µV 2 10 µV/°C INPUT VOSI Input stage offset voltage (1) VOSO Output stage offset voltage (1) PSRR vs temperature, TA = –40°C to +125°C Power supply rejection µV µV/°C G = 1, RTI 100 124 dB G = 10, RTI 115 130 dB G = 100, RTI 120 140 dB G = 1000, RTI 120 140 dB ZIN Differential impedance 20 || 1 GΩ || pF ZIN Common-mode impedance 10 || 5 GΩ || pF RFI filter, –3-dB frequency VCM Operating input range 20 V– (2) VS = ±1.35 V to ±18 V, TA = –40°C to +125°C Input overvoltage range CMRR At 5 kHz, RTI V ±40 V G = 1, VCM = (V–) to (V+) – 1 V 84 95 dB G = 10, VCM = (V–) to (V+) – 1 V 104 115 dB G = 100, VCM = (V–) to (V+) – 1 V 120 130 dB G = 1000, VCM = (V–) to (V+) – 1 V 120 130 dB G = 1, VCM = (V–) to (V+) – 1 V, TA = –40°C to +125°C Common-mode rejection V See Figure 41 to Figure 44 TA = –40°C to +125°C DC to 60 Hz, RTI MHz (V+) – 1 80 dB G = 1, VCM = (V–) to (V+) – 1 V 84 dB G = 10, VCM = (V–) to (V+) – 1 V 100 dB G = 100, VCM = (V–) to (V+) – 1 V 105 dB G = 1000, VCM = (V–) to (V+) – 1 V 105 dB BIAS CURRENT IB IOS VCM = VS/2 Input bias current 35 TA = –40°C to +125°C VCM = VS/2 Input offset current 0.7 TA = –40°C to +125°C 65 nA 95 nA 5 nA 10 nA 20 nV/√Hz 115 nV/√Hz NOISE VOLTAGE eNI eNO iN (1) (2) f = 1 kHz, G = 100, RS = 0 Ω Input stage voltage noise (3) Output stage voltage noise Noise current (3) 18 fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω 0.52 f = 1 kHz, G = 1, RS = 0 Ω 110 µVPP fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω 3.3 µVPP f = 1 kHz 100 fA/√Hz fB = 0.1 Hz to 10 Hz 5 pAPP Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO/G). Input voltage range of the INA826 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See Typical Characteristic curves Figure 9 through Figure 16 and Figure 41 through Figure 44 for more information. (3) (eNI)2 + Total RTI voltage noise = eNO 2 G . Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 3 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INA826 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GAIN 49.4 kW G Gain equation G Range of gain GE Gain error Gain vs temperature (4) Gain nonlinearity 1+ V/V RG 1 1000 V/V G = 1, VO = ±10 V ±0.003 ±0.015 % G = 10, VO = ±10 V ±0.03 ±0.15 % G = 100, VO = ±10 V ±0.04 ±0.15 % G = 1000, VO = ±10 V ±0.04 ±0.15 G = 1, TA = –40°C to +125°C ±0.1 ±1 ppm/°C G > 1, TA = –40°C to +125°C ppm/°C % ±10 ±35 G = 1 to 100, VO = –10 V to +10 V 1 5 ppm G = 1000, VO = –10 V to +10 V 5 20 ppm OUTPUT Voltage swing RL = 10 kΩ (V–) + 0.1 Load capacitance stability Open loop output impedance Short-circuit current (V+) – 0.15 1000 V pF See Figure 56 Continuous to VS/2 ±16 mA FREQUENCY RESPONSE G=1 BW SR tS tS (4) 4 Bandwidth, –3 dB Slew rate Settling time to 0.01% Settling time to 0.001% 1 MHz G = 10 500 kHz G = 100 60 kHz G = 1000 6 kHz G = 1, VO = ±14.5 V 1 V/µs G = 100, VO = ±14.5 V 1 V/µs G = 1, VSTEP = 10 V 12 µs G = 10, VSTEP = 10 V 12 µs G = 100, VSTEP = 10 V 24 µs G = 1000, VSTEP = 10 V 224 µs G = 1, VSTEP = 10 V 14 µs G = 10, VSTEP = 10 V 14 µs G = 100, VSTEP = 10 V 31 µs G = 1000, VSTEP = 10 V 278 µs The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INA826 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE INPUT RIN Input impedance 100 Voltage range kΩ (V–) Gain to output (V+) V 1 Reference gain error V/V 0.01 % POWER SUPPLY VS Power-supply voltage IQ Quiescent current Single Dual +2.7 +36 ±1.35 ±18 V V VIN = 0 V 200 250 µA vs temperature, TA = –40°C to +125°C 250 300 µA TEMPERATURE RANGE Specified –40 +125 °C Operating –50 +150 °C THERMAL INFORMATION THERMAL METRIC (1) INA826 INA826 INA826 D (SOIC) DGK (MSOP) DRG (DFN) 8 PINS 8 PINS 8 PINS θJA Junction-to-ambient thermal resistance 141.4 215.4 50.9 θJCtop Junction-to-case (top) thermal resistance 75.4 66.3 60.0 θJB Junction-to-board thermal resistance 59.6 97.8 25.4 ψJT Junction-to-top characterization parameter 27.4 10.5 1.2 ψJB Junction-to-board characterization parameter 59.1 96.1 25.5 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A 7.2 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 5 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com PIN CONFIGURATIONS DGK PACKAGE MSOP-8, SO-8 (TOP VIEW) DRG PACKAGE 3-mm × 3-mm DFN-8 (TOP VIEW) -IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 -VS -IN 1 RG 2 RG 3 +IN 4 Exposed Thermal Die Pad on Underside 8 +VS 7 VOUT 6 REF 5 -VS PIN DESCRIPTIONS 6 NAME NO. –IN 1 Negative input DESCRIPTION RG 2 Gain setting pin. Place a gain resistor between pin 2 and pin 3. RG 3 Gain setting pin. Place a gain resistor between pin 2 and pin 3. +IN 4 Positive input –VS 5 Negative supply REF 6 Reference input. This pin must be driven by low impedance. VOUT 7 Output +VS 8 Positive supply Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. TYPICAL DISTRIBUTION OF INPUT OFFSET VOLTAGE TYPICAL DISTRIBUTION OF INPUT OFFSET VOLTAGE DRIFT 1600 25 1400 20 1200 Count Count 1000 800 15 10 600 400 5 200 −2 −1.8 −1.6 −1.4 −1.2 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 −200 −180 −160 −140 −120 −100 −80 −60 −40 −20 0 20 40 60 80 100 120 140 160 180 200 0 VOSI (µV) VOSI Drift (µV/°C) G026 Figure 1. Figure 2. TYPICAL DISTRIBUTION OF OUTPUT OFFSET VOLTAGE TYPICAL DISTRIBUTION OF OUTPUT OFFSET VOLTAGE DRIFT 1600 G029 25 1400 20 1200 Count Count 1000 800 15 10 600 400 5 200 VOSO (µV) −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 0 −1000 −900 −800 −700 −600 −500 −400 −300 −200 −100 0 100 200 300 400 500 600 700 800 900 1000 0 G025 Figure 3. VOSO Drift (µV/°C) G030 Figure 4. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 7 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. TYPICAL DISTRIBUTION OF INPUT BIAS CURRENT TYPICAL DISTRIBUTION OF INPUT OFFSET CURRENT 3000 2000 2500 1500 Count Count 2000 1000 1500 1000 500 500 0 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 −5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 IB (nA) IOS (nA) G027 Figure 6. TYPICAL GAIN ERROR DRIFT DISTRIBUTION (G = 1) TYPICAL GAIN ERROR DRIFT DISTRIBUTION (G > 1) 32000 16000 Wafer Probe Data 14000 24000 12000 20000 10000 Count 28000 16000 8000 12000 6000 8000 4000 4000 2000 0 0 Gain Error Drift (ppm/°C) −20 −19 −18 −17 −16 −15 −14 −13 −12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 −1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Count Wafer Probe Data Gain Error Drift (ppm/°C) G052 G051 Figure 7. Figure 8. INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Single Supply, VS = +2.7 V, G = 1) INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Single Supply, VS = +2.7 V, G = 100) 3 3 VREF = 0 V VREF = 1.35 V 2.5 2 1.5 1 0.5 0 −0.5 −1 VREF = 0 V VREF = 1.35 V VS = 2.7 V, G = 100 Common−Mode Voltage (V) Common−Mode Voltage (V) VS = 2.7 V, G = 1 2.5 2 1.5 1 0.5 0 −0.5 0 0.5 1 1.5 2 Output Voltage (V) 2.5 3 −1 0 G035 Figure 9. 8 G028 Figure 5. 0.5 1 1.5 2 Output Voltage (V) 2.5 3 G036 Figure 10. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 −0.5 −1 VREF = 0 V VREF = 2.5 V VS = 5 V, G = 1 0 0.5 1 1.5 2 2.5 3 3.5 Output Voltage (V) 4 4.5 INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Single Supply, VS = +5 V, G = 100) Common−Mode Voltage (V) Common−Mode Voltage (V) INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Single Supply, VS = +5 V, G = 1) 5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 −0.5 −1 VREF = 0 V VREF = 2.5 V VS = 5 V, G = 100 0 0.5 1 1.5 G034 2 2.5 3 3.5 Output Voltage (V) 4 4.5 5 G037 Figure 11. Figure 12. INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Dual Supply, VS = ±3.3 V) INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Dual Supply, VS = ±5 V) 5 VS = ±3.3 V VREF= 0 V 2 G=1 G = 100 VS = ±5 V VREF= 0 V 4 Common−Mode Voltage (V) Common−Mode Voltage (V) 3 1 0 −1 −2 −3 3 G=1 G = 100 2 1 0 −1 −2 −3 −4 −5 −4 −4 −3 −2 −1 0 1 Output Voltage (V) 2 3 −6 4 −6 G039 −5 −4 −3 −2 −1 0 1 2 Output Voltage (V) 3 4 5 6 G038 Figure 14. INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Dual Supply, VS = ±15 V, ±12 V, G = 1) INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Dual Supply, VS = ±15 V, ±12 V, G = 100) 16 G = 1, VREF= 0 V 14 12 10 8 6 4 2 0 −2 −4 −6 −8 −10 −12 −14 −16 −16−14−12−10 −8 −6 −4 −2 0 2 4 6 Output Voltage (V) VS= ±15 V VS= ±12 V Common−Mode Voltage (V) Common−Mode Voltage (V) Figure 13. 8 10 12 14 16 G040 16 G = 100, VREF= 0 V 14 12 10 8 6 4 2 0 −2 −4 −6 −8 −10 −12 −14 −16 −16−14−12−10 −8 −6 −4 −2 0 2 4 6 Output Voltage (V) Figure 15. VS= ±15 V VS= ±12 V 8 10 12 14 16 G040 Figure 16. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 9 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INPUT OVERVOLTAGE vs INPUT CURRENT WITH 10-kΩ RESISTANCE (G = 1, VS = ±15 V) 16 8m 9m 12 6m 12 6m 8 4m 8 3m 4 2m 4 0 0 0 0 −4 −6m −8 Input Current (A) −3m G065 Figure 17. Figure 18. CMRR vs FREQUENCY (RTI) CMRR vs FREQUENCY (RTI, 1-kΩ Source Imbalance) 120 100 80 60 G=1 G = 10 G = 100 G = 1000 40 20 10 100 1k Frequency (Hz) 10k 120 100 80 60 40 0 100k G=1 G = 10 G = 100 G = 1000 20 10 100 G001 Figure 19. 140 140 Negative Power−Supply Rejection Ratio (dB) Positive Power−Supply Rejection Ratio (dB) 160 120 100 80 60 G=1 G = 10 G = 100 G = 1000 20 10 100 100k G002 120 100 80 60 G=1 G = 10 G = 100 G = 1000 40 20 1k Frequency (Hz) 10k NEGATIVE PSRR vs FREQUENCY (RTI) 160 40 1k Frequency (Hz) Figure 20. POSITIVE PSRR vs FREQUENCY (RTI) 10k 100k 0 10 G003 Figure 21. 10 G064 140 140 0 −12 −16 −8m −40−35−30−25−20−15−10 −5 0 5 10 15 20 25 30 35 40 Input Voltage (V) Common−Mode Rejection Ratio (dB) Common−Mode Rejection Ratio (dB) −8 IIN VOUT −6m 160 0 −4 −2m −4m IIN VOUT −12 −9m RS = 0 Ω −16 −12m −40−35−30−25−20−15−10 −5 0 5 10 15 20 25 30 35 40 Input Voltage (V) 16 RS = 10k Ω Output Voltage (V) 12m Output Voltage (V) Input Current (A) INPUT OVERVOLTAGE vs INPUT CURRENT (G = 1, VS = ±15 V) 100 1k Frequency (Hz) 10k 100k G004 Figure 22. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY (RTI) GAIN vs FREQUENCY 1k 70 50 40 Voltage Noise (nV/ Hz) G=1 G = 10 G = 100 G = 1000 60 Gain (dB) 30 20 10 0 −10 G=1 G = 10 G = 100 G = 1000 100 −20 −30 10 100 1k 10k 100k Frequency (Hz) 1M 10 10M 1 10 100 1k Frequency (Hz) G005 Figure 23. 10k 100k G019 Figure 24. CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY (RTI) 0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 1) 1k 3 Noise (µV/div) Current Noise (fA/ Hz) 2 100 1 0 −1 −2 10 1 10 100 Frequency (Hz) 1k −3 10k 0 1 2 3 G020 Figure 25. 4 5 6 Time (s/div) 7 8 9 10 G007 Figure 26. 0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 1000) 0.1-Hz TO 10-Hz RTI CURRENT NOISE 400 15 300 10 Noise (pA/div) Noise (nV/div) 200 100 0 −100 5 0 −5 −200 −10 −300 −400 0 1 2 3 4 5 6 Time (s/div) 7 8 9 10 −15 0 G006 Figure 27. 1 2 3 4 5 6 Time (s/div) 7 8 9 10 G008 Figure 28. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 11 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE (VS = +2.7 V) INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE (VS = ±15 V) 0 0 −40°C +25°C +125°C −20 −30 −40 −50 −60 −70 −80 −40°C +25°C +125°C −10 Input Bias Current (nA) Input Bias Current (nA) −10 −20 −30 −40 −50 −60 −70 −1 −0.5 0 0.5 1 1.5 2 Common Mode Voltage (V) 2.5 −80 −16 3 −12 −8 G056 Figure 29. INPUT BIAS CURRENT vs TEMPERATURE Input Offset Current − IOS (nA) Input Bias Current − IB (nA) Representative Data 60 50 40 30 20 10 4 2 0 −2 −4 −6 −8 −25 0 25 50 75 Temperature (°C) 100 125 150 −25 0 G033 25 50 75 Temperature (°C) 100 Figure 32. GAIN ERROR vs TEMPERATURE (G = 1) GAIN ERROR vs TEMPERATURE (G > 1) 2000 30 1500 125 150 G053 Figure 31. 1000 10 Gain Error (ppm) Gain Error (ppm) 6 −10 −50 20 0 −10 −20 −30 500 0 −500 −1000 −40 Representative Data Normalized at +25°C −25 0 25 50 75 Temperature (°C) −1500 100 125 150 −2000 −50 G031 Figure 33. 12 Max Data Min Data Unit 1 Unit 2 Unit 3 8 40 −60 −50 G055 INPUT OFFSET CURRENT vs TEMPERATURE 70 −50 16 10 80 0 −50 12 Figure 30. 100 90 −4 0 4 8 Common Mode Voltage (V) Representative Data Normalized at +25°C −25 0 25 50 75 Temperature (°C) 100 125 150 G054 Figure 34. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. CMRR vs TEMPERATURE (G = 1) SUPPLY CURRENT vs TEMPERATURE 300 10 VS = 2.7 V VS = ±15 V 8 250 Supply Current (µA) 6 CMRR (µV/V) 4 2 0 −2 −4 200 150 100 −6 −8 −10 −50 50 Representative Data Normalized at +25°C −25 0 25 50 75 Temperature (°C) 100 125 0 −50 150 −25 0 25 50 75 Temperature (°C) G032 Figure 35. 3 3 2 1 G043 2 1 −8 −6 −4 −2 0 2 4 Output Voltage (V) 6 8 0 −10 10 −8 −6 −4 G021 Figure 37. −11 −2 −12 −4 Nonlinearity (ppm) 0 −13 −14 −15 −16 −17 G022 −8 −12 −14 −16 −18 −2 0 2 4 Output Voltage (V) 10 −10 −19 −4 8 −6 −18 −6 6 GAIN NONLINEARITY (G = 1000) −10 −8 −2 0 2 4 Output Voltage (V) Figure 38. GAIN NONLINEARITY (G = 100) Nonlinearity (ppm) 150 GAIN NONLINEARITY (G = 10) 4 Nonlinearity (ppm) Nonlinearity (ppm) GAIN NONLINEARITY (G = 1) −20 −10 125 Figure 36. 4 0 −10 100 6 8 10 −20 −10 G023 Figure 39. −8 −6 −4 −2 0 2 4 Output Voltage (V) 6 8 10 G024 Figure 40. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 13 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. OFFSET VOLTAGE vs NEGATIVE COMMON-MODE VOLTAGE (VS = ±15 V) OFFSET VOLTAGE vs POSITIVE COMMON-MODE VOLTAGE (VS = ±15 V) 400 100 VS = ±15 V Offset Voltage (µV) 300 250 200 0 150 100 50 −150 −250 −350 −15.3 −15.1 −14.9 −14.7 Common Mode Voltage (V) −400 13.8 −14.5 14 14.1 14.2 Common Mode Voltage (V) 14.3 14.4 G058 Figure 42. OFFSET VOLTAGE vs NEGATIVE COMMON-MODE VOLTAGE (VS = +2.7 V) OFFSET VOLTAGE vs POSITIVE COMMON-MODE VOLTAGE (VS = +2.7 V) 200 VS = 2.7 V −50°C −40°C +25°C +85°C +125°C +150°C 150 −50°C −40°C +25°C +85°C +125°C +150°C 150 Offset Voltage (µV) 200 100 50 0 −50 100 50 0 −50 −100 −150 −100 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 Common Mode Voltage (V) 0.3 0.4 −200 0.5 1 1.2 G059 1.4 1.6 1.8 2 2.2 Common Mode Voltage (V) 2.4 2.6 G060 Figure 43. Figure 44. POSITIVE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (VS = ±15 V) NEGATIVE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (VS = ±15 V) 15 −14 −50°C −40°C +25°C +85°C +125°C +150°C −14.2 Output Voltage (V) 14.8 14.6 −50°C −40°C +25°C +85°C +125°C +150°C 14.4 14.2 0 2 4 −14.4 −14.6 −14.8 6 8 10 Output Current (mA) 12 14 16 −15 0 G045 Figure 45. 14 13.9 G057 Figure 41. VS = 2.7 V 14 −50°C −40°C +25°C +85°C +125°C +150°C −200 −300 250 Offset Voltage (µV) −100 0 300 Output Voltage (V) −50 −50 −100 −15.5 VS = ±15 V 50 Offset Voltage (µV) 350 −50°C −40°C +25°C +85°C +125°C +150°C 2 4 6 8 10 Output Current (mA) 12 14 16 G046 Figure 46. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. POSITIVE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (VS = 2.7 V) NEGATIVE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (VS = 2.7 V) 2.7 1 25°C 2.6 0.8 Output Voltage (V) Output Voltage (V) 2.5 2.4 2.3 2.2 2.1 2 1.9 0.6 0.5 0.4 0.3 0.1 VS = 2.7 V 0 2 4 6 8 10 Output Current (mA) 12 14 0 16 VS = 2.7 V 0 2 4 G048 6 8 10 Output Current (mA) 12 14 16 G049 Figure 47. Figure 48. LARGE-SIGNAL FREQUENCY RESPONSE SETTLING TIME vs STEP SIZE (VS = ±15-V) 25 30 VS = ±15 V VS = +5 V 27 0.01% 0.001% 24 21 21 Settling Time (µs) Output Voltage (V) 0.7 0.2 1.8 1.7 25°C 0.9 18 15 12 9 6 17 13 9 3 1k 10k 100k Frequency (Hz) 5 1M 4 6 8 10 12 14 Step Size (V) 16 Figure 50. SMALL-SIGNAL RESPONSE OVER CAPACITIVE LOADS (G = 1) SMALL-SIGNAL RESPONSE (G = 1, RL = 1 kΩ, CL = 100 pF) 100 80 80 60 60 40 0 pF 20 0 100 pF −20 220 pF 500 pF −40 1 nF −60 20 0 −20 −40 −60 −80 −100 −100 16 24 Time (ps) 20 40 −80 8 18 G061 Figure 49. 100 0 2 G014 Amplitude (mV) Amplitude (mV) 0 32 40 48 0 G013 Figure 51. 5 10 15 20 25 time (us) 30 35 40 G009 Figure 52. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 15 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. SMALL-SIGNAL RESPONSE (G = 100, RL = 10 kΩ, CL = 100 pF) 100 100 80 80 60 60 40 40 Amplitude (mV) Amplitude (mV) SMALL-SIGNAL RESPONSE (G = 10, RL = 10 kΩ, CL = 100 pF) 20 0 −20 −40 −60 20 0 −20 −40 −60 −80 −80 −100 −100 0 5 10 15 20 25 time (us) 30 35 40 0 20 40 60 80 G010 Figure 53. 100 120 140 160 180 200 time (us) G011 Figure 54. SMALL-SIGNAL RESPONSE (G = 1000, RL = 10 kΩ, CL = 100 pF) OPEN-LOOP OUTPUT IMPEDANCE 100 100k 80 40 10k 20 ZO (Ω) Amplitude (mV) 60 0 −20 1k −40 −60 −80 −100 0 100 100 200 300 400 500 600 700 800 900 1000 time (us) G012 1 10 100 Figure 55. 1k 10k Frequency (Hz) 100k 1M 10M G062 Figure 56. CHANGE IN INPUT OFFSET VOLTAGE vs WARM-UP TIME Change in Input Offset Voltage (µV) 15 10 5 0 −5 −10 −15 0 2 4 6 8 10 Warm−up Time (s) 12 14 16 G063 Figure 57. 16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 APPLICATION INFORMATION Figure 58 shows the basic connections required for operation of the INA826. Good layout practice mandates the use of bypass capacitors placed as close to the device pins as possible. The output of the INA826 is referred to the output reference (REF) terminal, which is normally grounded. This connection must be low-impedance to assure good common-mode rejection. Although 5 Ω or less of stray resistance can be tolerated while maintaining specified CMRR, small stray resistances of tens of ohms in series with the REF pin can cause noticeable degradation in CMRR. V+ 0.1 mF 8 (1) RS 1 RFI Filter -IN 50 kW 50 kW A1 VO = G ´ (VIN+ - VIN-) 2 24.7 kW RG G=1+ 7 A3 24.7 kW + 3 Load VO 50 kW (1) RS +IN 49.4 kW RG 50 kW A2 4 6 REF RFI Filter Device 5 0.1 mF V- Also drawn in simplified form: -IN RG +IN Device VO REF (1) This resistor is optional if the input voltage stays above [(V–) – 2 V] or the signal source current drive capability is limited to less than 3.5 mA. See the Input Protection section for more details. Figure 58. Basic Connections Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 17 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com SETTING THE GAIN Gain of the INA826 is set by a single external resistor, RG, connected between pins 2 and 3. The value of RG is selected according to Equation 1: G=1+ 49.4 kW RG (1) Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the INA826. Table 1. Commonly-Used Gains and Resistor Values DESIRED GAIN (V/V) RG (Ω) NEAREST 1% RG (Ω) 1 — — 2 49.4k 49.9k 5 12.35k 12.4k 10 5.489k 5.49k 20 2.600k 2.61k 50 1.008k 1k 100 499 499 200 248 249 500 99 100 1000 49.5 49.9 Gain Drift The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of RG to gain accuracy and drift can be directly inferred from the gain of Equation 1. The best gain drift of 1 ppm/℃ can be achieved when the INA826 uses G = 1 without RG connected. In this case, the gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 50-kΩ resistors in the differential amplifier (A3). At G greater than 1, the gain drift increases as a result of the individual drift of the 24.7-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG. Process improvements of the temperature coefficient of the feedback resistors now make it possible to specify a maximum gain drift of the feedback resistors of 35 ppm/℃, thus significantly improving the overall temperature stability of applications using gains greater than 1. Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately 100 or greater. To ensure stability, avoid parasitic capacitance of more than a few picofarads at RG connections. Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see Typical Characteristics curves (Figure 19 and Figure 20). 18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 OFFSET TRIMMING Most applications require no external offset adjustment; however, if necessary, adjustments can be made by applying a voltage to the REF terminal. Figure 59 shows an optional circuit for trimming the output offset voltage. The voltage applied to the REF terminal is summed at the output. The op amp buffer provides low impedance at the REF terminal to preserve good common-mode rejection. VIN- V+ RG VIN+ INA826 VO 100 mA 1/2 REF200 REF OPA333 ±10 mV Adjustment Range 100 W 10 kW 100 W 100 mA 1/2 REF200 V- Figure 59. Optional Trimming of Output Offset Voltage INPUT COMMON-MODE RANGE The linear input voltage range of the INA826 input circuitry extends from the negative supply voltage to 1 V below the positive supply, while maintaining 84-dB (minimum) common-mode rejection throughout this range. The common-mode range for most common operating conditions is described in the typical characteristic curves (Input Common-Mode Voltage vs Output Voltage, Figure 9 through Figure 16) and Offset Voltage vs CommonMode Voltage (Figure 41 through Figure 44). The INA826 can operate over a wide range of power supplies and VREF configurations, making it impractical to provide a comprehensive guide to common-mode range limits for all possible conditions. The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2, which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1 and A2 (see Figure 60) provides a check for the most common overload conditions. The designs of A1 and A2 are identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when the A2 output is saturated, A1 may continue to be in linear operation, responding to changes in the noninverting input voltage. This difference may give the appearance of linear operation but the output voltage is invalid. A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range that extends to single-supply ground, the INA826 employs a current-feedback topology with PNP input transistors; see Figure 60. The matched PNP transistors Q1 and Q2 shift the input voltages of both inputs up by a diode drop, and through the feedback network, shift the output of A1 and A2 by approximately +0.8 V. With both inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the linear range, allowing users to make differential measurements at the GND level. As a result of this input level-shifting, the voltages at pin 2 and pin 3 are not equal to the respective input terminal voltages (pin 1 and pin 4). For most applications, this inequality is not important because only the gain-setting resistor connects to these pins. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 19 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com INSIDE THE INA826 See Figure 58 for a simplified representation of the INA826. A more detailed diagram (shown in Figure 60) provides additional insight into the INA826 operation. Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA. The differential input voltage is buffered by Q1 and Q2 and is impressed across RG, causing a signal current to flow through RG, R1, and R2. The output difference amp, A3, removes the common-mode component of the input signal and refers the output signal to the REF terminal. The equations shown in Figure 60 describe the output voltages of A1 and A2. The VBE and voltage drop across R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages. V+ V+ RG (External) 50 kW R1 24.7 kW A1 Out = VCM + VBE + 0.125 V - VD/2 ´ G A2 Out = VCM + VBE + 0.125 V + VD/2 ´ G Output Swing Range A1, A2, (V+) - 0.1 V to (V-) + 0.1 V V- R2 24.7 kW V- V+ 50 kW VOUT A3 50 kW V+ VO = G ´ (VIN+ - VIN-) + VREF Linear Input Range A3 = (V+) - 0.9 V to (V-) + 0.1 V V- 50 kW REF VV+ V+ -IN Q1 VD/2 Overvoltage Protection Q2 C1 V- A1 A2 RB VCM C2 VB V- Overvoltage Protection RB VD/2 V+IN Figure 60. INA826 Simplified Circuit Diagram INPUT PROTECTION The inputs of the INA826 are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one input and +40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) – 2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite polarity; see typical characteristic curve Input Overvoltage vs Input Current (Figure 17). This polarity reversal can easily be avoided by adding resistance of 10 kΩ in series with both inputs. Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. The typical characteristic curves Input Current vs Input Overvoltage (Figure 17 and Figure 18) illustrate this input current limit behavior. The inputs are protected even if the power supplies are disconnected or turned off. 20 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 INPUT BIAS CURRENT RETURN PATH The input impedance of the INA826 is extremely high—approximately 20 GΩ. However, a path must be provided for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current for proper operation. Figure 61 shows various provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the common-mode range of the INA826, and the input amplifiers saturate. If the differential source resistance is low, the bias current return path can be connected to one input (as shown in the thermocouple example in Figure 61). With higher source impedance, using two equal resistors provides a balanced input with possible advantages of lower input offset voltage as a result of bias current and better high-frequency common-mode rejection. Microphone, Hydrophone, etc. Device 47 kW 47 kW Thermocouple Device 10 kW Device Center tap provides bias current return. Figure 61. Providing an Input Common-Mode Current Path Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 21 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com REFERENCE TERMINAL The output voltage of the INA826 is developed with respect to the voltage on the reference terminal. Often, in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In singlesupply operation, it can be useful to offset the output signal to a precise mid-supply level (for example, 2.5 V in a 5-V supply environment). To accomplish this, a voltage source can be tied to the REF pin to level-shift the output so that the INA826 can drive a single-supply ADC, for example. For the best performance, source impedance to the REF terminal should be kept below 5 Ω. As can be seen in Figure 58, the reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to this 50-kΩ resistor. The imbalance in the resistor ratios results in degraded common-mode rejection ratio (CMRR). Figure 62 shows two different methods of driving the reference pin with low impedance. The OPA330 is a lowpower, chopper-stabilized amplifier, and therefore offers excellent stability over temperature. It is available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference in the small SOT23-6 package. +5 V VIN- +5 V RG VOUT INA826 VIN- REF VIN+ +5 V RG VOUT INA826 REF +5 V VIN+ +2.5 V OPA330 a) Level shifting using the OPA330 as a low-impedance buffer REF3225 +5 V b) Level shifting using the low-impedance output of the REF3225 Figure 62. Options for Low-Impedance Level Shifting DYNAMIC PERFORMANCE The typical characteristic curve Gain vs Frequency (Figure 23) illustrates that, despite its low quiescent current of only 200 µA, the INA826 achieves much wider bandwidth than other INAs in its class. This achievement is a result of using TI’s proprietary high-speed precision bipolar process technology. The current-feedback topology provides the INA826 with wide bandwidth even at high gains. Settling time also remains excellent at high gain because of a high slew rate of 1 V/µs. 22 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 OPERATING VOLTAGE The INA826 operates over a power-supply range of +2.7 V to +36 V (±1.35 V to ±18 V). Supply voltages higher than 40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section of this data sheet. Low-Voltage Operation The INA826 can operate on power supplies as low as ±1.35 V. Most parameters vary only slightly throughout this supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires careful attention to assure that the input voltages remain within the linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low power-supply voltage. The typical characteristic curves Typical Common-Mode Range vs Output Voltage (Figure 9 to Figure 16) and Offset Voltage vs CommonMode Voltage (Figure 41 to Figure 44) describe the range of linear operation for various supply voltages, reference connections, and gains. ERROR SOURCES Most modern signal conditioning systems calibrate errors at room temperature. However, calibration of errors that result from a change in temperature is normally difficult and costly. Therefore, it is important to minimize these errors by choosing high-precision components such as the INA826 that have improved specifications in critical areas that impact the precision of the overall system. Figure 63 shows an example application. RS+ = 10 kW VDIFF = 1 V 5.49 kW +15 V VOUT Device REF VCM = 10 V RS- = 9.9 kW Signal Bandwidth: 5 kHz - 15 V Figure 63. Example Application with G = 10 V/V and 1-V Differential Voltage Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 23 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com Resistor-adjustable INAs such as the INA826 show the lowest gain error in G = 1 because of the inherently wellmatched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G = 10 V/V or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor. Except for very high gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset drift. The INA826 offers the lowest gain error over temperature in the marketplace for both G > 1 and G = 1 (no external gain resistor). Table 2 summarizes the major error sources in common INA applications and compares the two cases of G = 1 (no external resistor) and G = 10 (5.49-kΩ external resistor). As can be seen in Table 2, while the static errors (absolute accuracy errors) in G = 1 are almost twice as great as compared to G = 10, there are much fewer drift errors because of the much lower gain error drift. In most applications, these static errors can readily be removed during calibration in production. All calculations refer the error to the input for easy comparison and system evaluation. Table 2. Error Calculation INA826 ERROR SOURCE ERROR CALCULATION SPEC G = 10 ERROR (ppm) G = 1 ERROR (ppm) ABSOLUTE ACCURACY AT +25°C Input offset voltage (μV) VOSI/VDIFF 150 150 150 Output offset voltage (μV) VOSO/(G × VDIFF) 700 70 700 Input offset current (nA) IOS × maximum (RS+, RS–)/VDIFF 5 50 50 104 (G = 10), 84 (G = 1) 63 631 333 1531 35 (G = 10), 1 (G = 1) 2800 80 CMRR (dB) VCM/(10CMRR/20 × VDIFF) Total absolute accuracy error (ppm) DRIFT TO +105°C Gain drift (ppm/°C) GTC × (TA – 25) Input offset voltage drift (μV/°C) (VOSI_TC/VDIFF) × (TA – 25) 2 160 160 Output offset voltage drift (μV/°C) [VOSO_TC/( G × VDIFF)] × (TA – 25) 10 80 800 Offset current drift (pA/°C) IOS_TC × maximum (RS+, RS–) × (TA – 25)/VDIFF 60 48 48 3088 1088 5 5 5 eNI = 18, eNO = 110 10 10 15 15 3436 2634 Total drift error (ppm) RESOLUTION Gain nonlinearity (ppm of FS) Voltage noise (1 kHz) BW ´ (eNI2 + eNO G 2 6 ´ VDIFF Total resolution error (ppm) TOTAL ERROR Total error Total error = sum of all error sources LAYOUT GUIDELINES Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place 0.1-μF bypass capacitors close to the supply pins. These guidelines should be applied throughout the analog circuit to improve performance and provide benefits such as reducing the electromagnetic-interference (EMI) susceptibility. CMRR vs Frequency The INA826 pinout has been optimized for achieving maximum CMRR performance over a wide range of frequencies. However, care must be taken to ensure that both input paths are well-matched for source impedance and capacitance to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain switching using switches or PhotoMOS® relays to change the value of RG, the component should be chosen so that the switch capacitance is as small as possible. 24 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 APPLICATION IDEAS Circuit Breaker Figure 64 showns the INA826 used in a circuit breaker application. +3 V AVDD DVDD SCLK Serial Interface (SPI) Passive Integrator 100 kW RG DIO MSP430 Microcontroller CS INA826 IP Mux Ch 1 ADC REF G=1 Rogowski Coil 100 kW PGA112 PGA113 +3 V GND REF3312 REF 1.2 V Figure 64. Circuit Breaker Example Programmable Logic Controller (PLC) Input The INA826 used in an example programmable logic controller (PLC) input application is shown in Figure 65. ±10 V 100 kW +15 V 4.87 kW 4 mA to 20 mA ±20 mA 12.4 kW VOUT = 2.5 V ± 2.3 V Device 20 W REF -15 V +2.5 V REF3225 +5 V Figure 65. ±10-V, 4-mA to 20-mA PLC Input Additional application ideas are shown in Figure 66 to Figure 70. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 25 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com TINA-TI (FREE DOWNLOAD SOFTWARE) Using TINA-TI SPICE-Based Analog Simulation Program with the INA826 TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range of both passive and active models. It provides all the conventional dc, transient, and frequency domain analysis of SPICE as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. Figure 66 and Figure 68 show example TINA-TI circuits for the INA826 that can be used to develop, modify, and assess the circuit design for specific applications. Links to download these simulation files are given below. NOTE: These files require that either the TINA software (from DesignSoft) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. The circuit in Figure 66 is used to convert inputs of ±10 V, ±5 V, or ±20 mA to an output voltage range from 0.5 V to 4.5 V. The input selection depends on the settings of SW1 and SW2. Further explanation as well as the TINATI simulation circuit is provided in the compressed file that can be downloaded at the following link: PLC Circuit. +Vs V1 15 CurrentInput V2 15 Source_Switch Vin Iin + Terminal Iin -Vs Sen se - +Vs Amp Out Vin SW1 Ref RG 49.9k VoltageInput INA Out + + Rg R4 250 SW2 Rg - + U2 INA826 Vs 5 - Terminal + Ref 1 U1 INA159 Ref 2 + ADC_Diff - Vref 2.5 -Vs Figure 66. Two Terminal Programmable Logic Controller (PLC) Input 26 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 Figure 67 is an example of a LEAD I ECG circuit. The input signals come from leads attached to the right arm (RA) and left arm (LA). These signals are simulated with the circuitry in the corresponding boxes. Protection resistors (RPROT1 and RPROT2) and filtering are also provided. The OPA333 is used as an integrator to remove the gained-up dc offsets and servo the INA826 outputs to VREF. Finally, the right leg drive is biased to a potential (+VS/2) and it inverts and amplifies the average common-mode signal back into the patient's right leg. This architecture reduces the 50-/60-Hz noise pickup. Click the following link to download the TINA-TI file: ECG Circuit. +Vs U1 OPA333 LA Electrode + R4 52k + Vref ECGp C2 47n +Vs Rprot1 100k + C10 1u ECG_LA C5 33p RG1 6.1k RG2 6.1k C6 1n + C4 47n + + Rg U4 INA826 Vout Rg - C7 33p Rprot2 100k ECG_RA +Vs R7 52k ECGn R1 1M C_RLD 47n R_RLD 52k RA Electrode RL Electrode R12 500k Ref Vref V1 5 R6 10k C11 1n R9 1M R3 10k R5 10M + U3 OPA2314 - Rprot3 100k U2 OPA2314 + + + +Vs Vref +Vs Figure 67. ECG Circuit Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 27 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com Figure 68 shows an example of how the INA826 can be used for low-side current sensing. The load current (ILOAD) creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the INA826, with gain set to 100. The output swing of the INA826 is set by the common-mode voltage (which is 0 V in low-side current sensing) and power supplies. Therefore, a dual-supply circuit is implemented. The load current was set from 1 A to 10 A, which corresponds to an output voltage range from 350 mV to 3.5 V. The output range can be adjusted by changing the shunt resistor and/or the gain of the INA826. Click the following link to download the TINA-TI file: Current Sensing Circuit. +Vs +Vs Iload 10 V1 5 Vbus 10 + U2 INA826 + Rg Rshunt 3.5m Ref RG 499 Vout Rg V2 5 Rout 10k - -Vs -Vs Figure 68. Low-Side Current Sensing 28 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 Figure 69 shows an example of how the INA826 can be used for RTD signal conditioning. This circuit creates an excitation current (ISET) by forcing +2.5 V from the REF5025 across RSET. The zero-drift, low-noise OPA188 creates the virtual ground that maintains a constant differential voltage across RSET with changing common-mode voltage. This voltage is necessary because the voltage on the positive input of the INA826 fluctuates over temperature as a result of the changing RTD resistance. Click the following link to download the TINA-TI file: RTD Circuit. +Vs Vref5025 U2 REF5025 NC Vin Vout Temp Trim GND R2 1.5M + Vset Rset 2.5k - VirtualGND -Vs +Vs - + + V1 15 U1 OPA188 + +Vs A Iset V2 15 +Vs + Rg -Vs + U4 INA826 Ref RTD 100 Rg 5k + Rg Vout - Rparasitic 5 -Vs Figure 69. RTD Signal Conditioning Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 29 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com The circuit in Figure 70 creates a precision current ISET by forcing the INA826 VDIFF across RSET. The input voltage VIN is amplified to the output of the INA826 and then divided down by the gain of the INA826 to create VDIFF. ISET can be controlled either by changing the value of the gain-set resistor RG, the set resistor RSET, or by changing VOUT through the gain of the composite loop. Care must be taken to ensure that the changing load resistance RL does not create a voltage on the negative input of the INA826 that violates the compliance of the common-mode input range. Likewise, the voltage on the output of the OPA170 must remain compliant throughout the changing load resistance for this circuit to work properly. Click the following link to download the TINA-TI file: Current Source. R1 10k R2 10k C1 100p -Vs +Vs U2 OPA170 + + Rg Vin + + + + Vdiff Ref Vout RG 1k Rset 10k - +Vs U4 INA826 Rg - +Vs -Vs + A V1 15 Iset RL 1k V2 15 -Vs Figure 70. Precision Current Source 30 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 INA826 www.ti.com SBOS562C – AUGUST 2011 – REVISED MARCH 2012 EVALUATION MODULE (EVM) The INA826EVM is intended to provide basic functional evaluation of the INA826. A diagram of the INA826EVM is provided in Figure 71. Figure 71. INA826 Evaluation Module The INA826 provides the following features: • Intuitive evaluation with silkscreen schematic • Easy access to nodes with surface-mount test points • Advanced evaluation with two prototype areas • Reference voltage source flexibility • Convenient input and output filtering The INA826EVM User Guide (SBOU115) available for download at www.ti.com provides instructions on how to set up the device for dual- and single-supply operation. The user guide also includes schematics, layout, and a bill of material (BOM). Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 31 INA826 SBOS562C – AUGUST 2011 – REVISED MARCH 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (December 2011) to Revision C Page • Changed product status from Mixed Status to Production Data .......................................................................................... 1 • Changed DFN-8 package to production data ....................................................................................................................... 2 • Deleted gray shading and footnote 2 from Package/Ordering Information table ................................................................. 2 Changes from Revision A (September 2011) to Revision B • 32 Page Deleted gray from SO-8 row in Package/Ordering Information ............................................................................................ 2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): INA826 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) INA826AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA826AIDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA826AIDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA826AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA826AIDRGR ACTIVE SON DRG 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR INA826AIDRGT ACTIVE SON DRG 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing INA826AIDGKR VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 INA826AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 INA826AIDRGR SON DRG 8 1000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 INA826AIDRGT SON DRG 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA826AIDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 INA826AIDR SOIC D 8 2500 367.0 367.0 35.0 INA826AIDRGR SON DRG 8 1000 367.0 367.0 35.0 INA826AIDRGT SON DRG 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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