SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • • • (1) Controlled Baseline – One Assembly – One Test Site – One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Member of the Texas Instruments Widebus™ Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 DGG, DGV, OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2006, Texas Instruments Incorporated SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 DESCRIPTION/ORDERING INFORMATION The SN74LVTH16245A is a 16-bit (dual-octal) noninverting 3-state transceiver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses effectively are isolated. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 V and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 TERMINAL ASSIGNMENTS (1) 1 6 2 3 4 5 6 A 1DIR NC NC NC NC 1OE A B 1B2 1B1 GND GND 1A1 1A2 B C 1B4 1B3 VCC VCC 1A3 1A4 C D 1B6 1B5 GND GND 1A5 1A6 D E 1B8 1B7 1A7 1A8 E F 2B1 2B2 12A2 2A1 G 2B3 2B4 GND 2A4 2A3 H 2B5 2B6 VCC VCC 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE F G H GND J K (1) NC – no internal connection ORDERING INFORMATION PACKAGE (1) TA –40°C to 125°C –40°C to 85°C –55°C to 125°C (1) 2 ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP – DL Tape and reel CLVTH16245AQDLREP LH16245AEP TSSOP – DGG Tape and reel CLVTH16245AQDGGREP LH16245AEP TVSOP – DGV Tape and reel CLVTH16245AIDGVREP LL245AEP VFBGA – GQL CLVTH16245AIGQLREP VFBGA – ZQL (Pb-free) Tape and reel SSOP – DL Tape and reel CLVTH16245AIZQLREP CLVTH16245AMDLREP LL245AEP LH16245AEP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Submit Documentation Feedback SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 FUNCTION TABLE (each 8-bit section) INPUTS OE OPERATION DIR L L B data to A bus L H A data to B bus H X Isolation LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 To Seven Other Channels 2B1 To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V –0.5 VCC + 0.5 V VO Voltage range applied to any output in the high state (2) SN74LVTH16245A(Q/M) 96 IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) Tstg Storage temperature range SN74LVTH16245AI 128 SN74LVTH16245A(Q/M) 48 SN74LVTH16245AI 64 DGG package 70 DGV package 58 DL package 63 GQL/ZQL package (1) (2) (3) (4) mA mA °C/W 42 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback 3 SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 Recommended Operating Conditions (1) SN74LVTH16245AQ SN74LVTH16245AM MIN MAX MIN MAX MIN MAX 2.7 3.6 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 0.8 VI Input voltage 5.5 5.5 5.5 V IOH High-level output current –24 –32 –24 mA IOL Low-level output current 24 64 24 mA ∆t/∆v Input transition rise or fall rate 10 10 10 ns/V 2 Outputs enabled ∆t/∆VCC Power-up ramp rate 200 TA –40 (1) 4 SN74LVTH16245AI Operating free-air temperature 2 2 200 125 –40 V –55 V µs/V 200 85 V 125 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). Submit Documentation Feedback SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER VIK SN74LVTH16245AQ TEST CONDITIONS VCC = 2.7 V, MIN TYP (1) II = –18 mA VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC = 2.7 V, VOH VCC = 3.3 V VCC = 2.7 V VOL VCC = 3 V Control inputs II IOH = –8 mA IOH = –24 mA MIN TYP (1) –1.2 –1.2 2.4 2.4 2.4 2 MAX –1.2 VCC – 0.2 IOH = –32 mA 2 IOL = 100 µA 0.2 0.2 0.2 IOL = 24 mA 0.5 0.5 0.5 IOL = 16 mA 0.4 0.4 0.4 IOL = 32 mA 0.5 IOL = 64 mA 0.55 ±1 ±1 ±1 VCC = 0 or 3.6 V, VI = 5.5 V 10 10 10 20 20 20 VCC = 3 V VI = VCC 5 1 5 –5 –5 –5 A or B port ±100 VI = 0.8 V VI = 2 V V V VCC = 3.6 V, VI = VCC or GND VCC = 3.6 V UNIT 2 VCC = 0, VI or VO = 0 to 4.5 V II(hold) (3) MIN TYP (1) VCC – 0.2 VI = 0 Ioff SN74LVTH16245AM MAX VCC – 0.2 VI = 5.5 V A or B port (2) SN74LVTH16245AI MAX 75 75 –75 –75 V µA µA 75 –75 VCC = 3.6 V, VI = 0 to 3.6 V µA 500 –750 IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care ±100 ±100 ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care ±100 ±100 ±100 µA 0.19 0.19 0.19 ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 5 5 5 0.19 0.19 0.19 0.2 0.2 0.2 Outputs high Outputs low Outputs disabled mA ∆ICC (4) VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 4 4 4 pF Cio VO = 3 V or 0 10 10 10 pF (1) (2) (3) (4) mA All typical values are at VCC = 3.3 V, TA = 25°C. Unused pins at VCC or GND This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Submit Documentation Feedback 5 SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 Switching Characteristics over operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LVTH16245AQ SN74LVTH16245AM PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A OE A or B OE A or B VCC = 3.3 V ±0.3 V SN74LVTH16245AI 6 VCC = 2.7 V MAX MIN TYP (1) MAX 4.5 4.6 1.5 2.3 3.3 3.7 0.5 4.4 3.9 1.3 2.1 3.3 3.5 0.5 6.5 6.6 1.5 2.8 4.5 5.3 0.5 5.4 6.2 1.6 2.9 4.6 5.2 1 6.8 7 2.3 3.7 5.1 5.5 1 6.2 6.3 2.2 3.5 5.1 5.4 0.5 0.5 MIN MAX 0.5 MIN tsk(o) (1) VCC = 3.3 V ±0.3 V VCC = 2.7 V All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback MIN UNIT MAX ns ns ns ns SN74LVTH16245A-EP 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS693G – APRIL 2003 – REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION 6V S1 500 W From Output Under Test Open GND CL = 50 pF (see Note A) 500 W TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 2.7 V Input 1.5 V 1.5 V 0V tPHL tPLH V 1.5 V Output 1.5 V V V Output 1.5 V 1.5 V 1.5 V V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V tPZH tPLH tPHL 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V V tPHZ V 1.5 V VOH - 0.3 V »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 59 W, tr £ 2.5 ns, tf £ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 8V16245AMDLREPG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16245AIDGVREP ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16245AIZQLREP ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 SNAGCU Level-1-260C-UNLIM CLVTH16245AMDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16245AQDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16245AQDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04602-01XE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04602-01YE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04602-02UA ACTIVE BGA MI CROSTA R JUNI OR GQL 56 V62/04602-02ZE ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04602-03XE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Pb-Free (RoHS) TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-Nov-2008 incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVTH16245A-EP : SN74LVTH16245A • Catalog: Automotive: SN74LVTH16245A-Q1 • Military: SN54LVTH16245A • NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Automotive • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CLVTH16245AIDGVREP Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 CLVTH16245AIZQLREP BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.45 8.0 16.0 Q1 CLVTH16245AMDLREP SSOP CLVTH16245AQDGGREP TSSOP CLVTH16245AQDLREP SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVTH16245AIDGVREP TVSOP DGV 48 2000 367.0 367.0 38.0 ZQL 56 1000 333.2 345.9 28.6 CLVTH16245AIZQLREP BGA MICROSTAR JUNIOR CLVTH16245AMDLREP SSOP DL 48 1000 367.0 367.0 55.0 CLVTH16245AQDGGREP TSSOP DGG 48 2000 367.0 367.0 45.0 CLVTH16245AQDLREP SSOP DL 48 1000 367.0 367.0 55.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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