Application Report SLVA695 – May 2015 Maximum Clock Frequency of I2C Bus Using Repeaters Rajan Arora, Jim Le ABSTRACT In this application report we show how to calculate the maximum clock frequency (fSCL (max)) of an I2C bus when using a repeater. The propagation delays added by the repeater are included in the timing budget calculations and shown to limit the maximum clock frequency in the case of I2C FM+ bus. 1 2 3 4 Contents Introduction ................................................................................................................... I2C Bus Without a Repeater ............................................................................................... I2C Bus With a Repeater ................................................................................................... Summary ...................................................................................................................... 1 2 3 6 List of Figures 1 Timing Diagram for an I2C System With the Master Generating the SCL Clock Signal and a Slave Responding With Data on SDA ............................................................................................ 2 2 Generic I2C Bus System Showing a Bus Master, Repeater, and a Slave ........................................... 3 3 Timing Diagram for an I2C System With the Master Generating the SCL Clock Signal, an I2C Repeater Providing Capacitance Buffering (and Adding Propagation Delay), and a Slave Responding With Data on SDA ............................................................................................................................ 5 List of Tables 1 1 fSCL (max) Calculation for I2C Systems Based on FM or FM+ Masters and Slaves................................. 3 2 Relationship Between tLOW (min), tVD;DAT and tSU;DAT ....................................................................... 3 3 Maximum Clock Frequency (fSCL (max)) Calculation Based on I2C FM Specifications and for FM Specifications with TCA9617B Repeater Characteristics .............................................................. 5 4 Maximum Clock Frequency (fSCL (max)) Calculation Based on I2C FM+ Specifications and for FM+ Specifications With TCA9617B Repeater Characteristics .............................................................. 6 Introduction The I2C communication standard is a widely used inter-chip communication standard in today’s electronic systems. The I2C standard limits the maximum allowed capacitance on the bus to 400 pF for I2C fast mode (FM) and 550 pF for I2C fast mode plus (FM+). With ever-growing system complexity more and more integrated circuits (IC’s) are added to the I2C bus and complying with the I2C spec capacitance limit has become a concern. Each IC added results in a capacitance increase up to approximately 15 pF on the I2C bus. I2C repeaters are circuits which provide a solution to the previously described problem by isolating the capacitance between two I2C bus, hence, allowing greater capacitance on an I2C bus for a given timing budget. The maximum clock frequency (fSCL (max)) is specified to be up to 400 kHz for I2C FM and up to 1000 kHz for FM+ spec. With the increasing number of devices, application requirements also tend to dictate faster operating frequencies to improve overall system response time. Since I2C repeaters typically buffer both the clock (SCL) and the data (SDA) lines, an I2C system utilizing I2C repeaters must properly account for the propagation delays through the repeater when determining the optimal operating frequency. In this article we show the calculations that can be used to determine the maximum clock frequency on an I2C bus-based on repeater propagation delays. The trade-offs that need to be considered between system design parameters and timing budget requirements are also discussed. SLVA695 – May 2015 Submit Documentation Feedback Maximum Clock Frequency of I2C Bus Using Repeaters Copyright © 2015, Texas Instruments Incorporated 1 I2C Bus Without a Repeater 2 www.ti.com I2C Bus Without a Repeater The timing diagram for an I2C bus with a master generating the SCL clock signal and a slave responding with data on SDA is shown in Figure 1 (refer to the I2C spec for a detailed description of the timing parameters). tHIGH tLOW tR SCL tF 0.7xVCC 0.3xVCC tSU;DAT tVD;DAT SDA (LOW Æ HIGH) 0.7xVCC tSU;DAT tVD;DAT SDA (HIGH Æ LOW) 0.3xVCC Figure 1. Timing Diagram for an I2C System With the Master Generating the SCL Clock Signal and a Slave Responding With Data on SDA The maximum clock frequency for this case can be calculated as: (1) Where, tLOW = low period of the clock tHIGH = high period of the clock tR = rise time of the clock tF = fall time of the clock 2 Maximum Clock Frequency of I2C Bus Using Repeaters Copyright © 2015, Texas Instruments Incorporated SLVA695 – May 2015 Submit Documentation Feedback I2C Bus With a Repeater www.ti.com The timing parameters in Equation 1 and the fSCL (max) calculation result based on these timing parameters for a system based on I2C FM and FM+ spec is shown in Table 1. As expected, the fSCL (max) for FM spec is 400 kHz and for FM+ spec is 1000 kHz, as also mentioned in the I2C spec. Table 1. fSCL (max) Calculation for I2C Systems Based on FM or FM+ Masters and Slaves Based on I2C FM Spec Limits Based on I2C FM+ Spec Limits LOW period of SCL clock (tLOW (min)) 1300 ns 500 ns HIGH period of SCL clock (tHIGH (min)) 600 ns 260 ns Rise time of both SDA and SCL signals (tR (max)) 300 ns 120 ns Parameter Fall time of both SDA and SCL signals (tF (max)) Maximum clock frequency (fSCL (max)) 300 ns 120 ns 400 kHz 1000 kHz From the timing diagram in Figure 1, tLOW (min) must be greater than tVD;DAT (max) plus tSU;DAT to satisfy the data valid and setup time requirement. (2) Based on numbers in Table 2, the FM spec has enough timing margin to satisfy Equation 2, however, there is no timing margin in FM+ spec to satisfy Equation 2. This can cause challenges when a repeater that adds propagation delays is used on the I2C FM+ bus. Table 2. Relationship Between tLOW (min), tVD;DAT and tSU;DAT Based on FM Spec Limits Based on FM+ Spec Limits LOW period of SCL clock (tLOW (min)) 1300 ns 500 ns Data valid time (tVD;DAT (max)) 900 ns 450 ns Data valid time (tSU;DAT (min)) 100 ns 50 ns Timing margin (= tLOW (min) - tVD;DAT (max) - tSU;DAT (min)) 300 ns 0 ns Parameter 3 I2C Bus With a Repeater Consider an I2C bus system where a repeater is used to isolate the capacitance between the master and slave side similar to Figure 2. VCC VCC RP RP SCL Master SDA Repeater SDAA A-side SCL SCLB SCLA SDAB SDA Slave B-side Figure 2. Generic I2C Bus System Showing a Bus Master, Repeater, and a Slave The worst-case timing delay is seen for the case when the slave is sending the data to the master as in this case the data valid time (tVD;DAT) and setup time (tSU;DAT) has to be met with the repeater propagation delayed SCL (Figure 3). The master generates the I2C clock signal (SCL) on the A-side of the repeater. This SCL is passed through the repeater and appears at the B-side with the repeater propagation delay added (tPHL;AB). The data on the B-side (SDA) must be valid within the data valid time (tVD;DAT) as per the I2C spec (note that the tVD;DAT is referenced to the delayed SCL on B-side). After the data becomes valid, it SLVA695 – May 2015 Submit Documentation Feedback Maximum Clock Frequency of I2C Bus Using Repeaters Copyright © 2015, Texas Instruments Incorporated 3 I2C Bus With a Repeater www.ti.com passes through the repeater from B-side to A-side and a propagation delay (tPHL;BA) is added. For simplicity, we have assumed that the rise/fall time on the A- and B-side of the repeater are the same, however, in practice they can differ. The data on the A-side must be available at setup time (tSU;DAT) before the rising edge of SCL. For the LOW to HIGH transition on SDA, adding all of the mentioned time corresponds to the LOW period of the SCL as: (3) For the HIGH to LOW transition on SDA adding the previously mentioned timings corresponds to the LOW period of the SCL as: (4) The maximum clock (SCL) frequency that can be used on an I2C bus with a repeater can be calculated as: (5) Assuming the HIGH-to-LOW transition on SDA results in greater timing delay compared to the LOW-toHIGH transition: (6) Table 3 shows the values for the timing parameters shown in Equation 6 and the calculation result for the fSCL (max) based on I2C FM spec and for I2C FM spec with TCA9617B repeater rise/fall time specs. The calculation shows that it is possible to meet the 400 kHz I2C FM fSCL (max) spec in both cases (fSCL (max) is higher than 400 kHz in both cases). 4 Maximum Clock Frequency of I2C Bus Using Repeaters Copyright © 2015, Texas Instruments Incorporated SLVA695 – May 2015 Submit Documentation Feedback I2C Bus With a Repeater www.ti.com tHIGH tLOW tF tR tPHL;AB SCL 0.7xVCC 0.3xVCC A-side B-side tSU;DAT tVD;DAT SDA (LOW Æ HIGH) 0.7xVCC tPLH;BA tSU;DAT tVD;DAT tPHL;BA SDA (HIGH Æ LOW) 0.3xVCC 0.3xVCC Figure 3. Timing Diagram for an I2C System With the Master Generating the SCL Clock Signal, an I2C Repeater Providing Capacitance Buffering (and Adding Propagation Delay), and a Slave Responding With Data on SDA Table 3. Maximum Clock Frequency (fSCL (max)) Calculation Based on I2C FM Specifications and for FM Specifications with TCA9617B Repeater Characteristics Based on I2C FM Spec With TCA9617B Propagation Delays Based on I2C FM Spec With TCA9617B Propagation Delays and Rise/Fall Times Data valid time (tVD;DAT (max)), from I2C FM spec 900 ns 900 ns Data setup time (tSU;DAT (min)), from I2C FM spec 100 ns 100 ns High period of SCL (tHIGH (min)), from I2C FM spec 600 ns 600 ns Repeater propagation delay from B to A defined as 0.3xVCC on A and B side (tPHL;BA), from repeater datasheet (TCA9617B) 140 ns 140 ns Repeater propagation delay from A to B defined as 0.7xVCC on A and B side (tPHL;AB), from repeater datasheet (TCA9617B) 144 ns 144 ns Fall time of SCL (tF (max)), from I2C FM spec or repeater datasheet (TCA9617B) 300 ns 13.8 ns Rise time of SCL (tR (max)), from I2C FM spec or repeater datasheet (TCA9617B) 300 ns 88 ns 402.6 kHz 503.6 kHz Parameter Maximum clock frequency (fSCL (max)) Table 4 shows the values for the timing parameters shown in Equation 6 and the calculation result for the fSCL (max) based on I2C FM+ spec and for I2C FM+ spec with TCA9617B repeater rise/fall time specs. These calculation results show that with the TCA9617B repeater it may not be possible to meet the 1000 kHz I2C FM+ fSCL (max) spec under all loading conditions (fSCL (max) is lower than 1000 kHz in both cases). For smaller loading conditions than those specified in TCA9617B datasheet the repeater propagation delays and rise/fall times are smaller, hence, higher fSCL (max) than those mentioned in Table 4 can be achieved. However, because of no timing margin on the I2C FM+ spec it still is not possible to meet the 1000 kHz fSCL (max) spec. SLVA695 – May 2015 Submit Documentation Feedback Maximum Clock Frequency of I2C Bus Using Repeaters Copyright © 2015, Texas Instruments Incorporated 5 Summary www.ti.com Table 4. Maximum Clock Frequency (fSCL (max)) Calculation Based on I2C FM+ Specifications and for FM+ Specifications With TCA9617B Repeater Characteristics Parameter Based on I2C FM+ Spec With TCA9617B Propagation Delays Based on I2C FM+ Spec With TCA9617B Propagation Delays and Rise/Fall Times 450 ns 450 ns Data valid time (tVD;DAT (max)), from I2C FM+ spec Data setup time (tSU;DAT (min)), from I2C FM+ spec 50 ns 50 ns High period of SCL (tHIGH (min)), from I2C FM+ spec 260 ns 260 ns Repeater propagation delay from B to A defined as 0.3xVCC on A and B side (tPHL;BA), from repeater datasheet (TCA9617B) 140 ns 140 ns Repeater propagation delay from A to B defined as 0.7xVCC on A and B side (tPHL;AB), from repeater datasheet (TCA9617B) 144 ns 144 ns Fall time of SCL (tF (max)), from I2C FM+ spec or repeater datasheet (TCA9617B) 120 ns 13.8 ns Rise time of SCL (tR (max)), from I2C FM+ spec or repeater datasheet (TCA9617B) 120 ns 88 ns 778.8 kHz 872.8 kHz Maximum clock frequency (fSCL (max)) If an experiment is carried out in the lab to measure the maximum frequency on SCL when using a repeater, it may be possible to clock the signals at a faster rate than what the calculations in Table 4 show. However, the system designer should take these calculations into consideration as all the slaves on the I2C bus may not be able to support that high frequency over all possible temperature / voltage corners conditions, hence, leading to yield fallout. The system designer has the flexibility to reduce the loading conditions and achieve the highest clock frequency possible. 4 Summary In this application report we showed a method of calculating the maximum clock frequency of an I2C bus using a repeater. It is shown that the I2C FM spec has timing margin for repeater propagation delays; however, the FM+ spec does not have timing margin for the repeater propagation delay. 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