Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 LM10011 6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current 1 Features 3 Description • • • • • • • • The LM10011 is a precision, digitally programmable device used to control the output voltage of a DC/DC converter. The LM10011 outputs a dc current proportional to a 6-bit or 4-bit input word. By connecting the IDAC_OUT pin to the feedback node of a regulator, the regulator output voltage can be adjusted to a desired range and resolution set by the user. As the input word counts up, the output voltage is adjusted higher based on the values of the feedback resistors in the converter. 1 1.0% Output Current Accuracy (0°C to 100°C) 1.25% Output Current Accuracy (–40°C to 125°C) Input Voltage Range: 2.97 V to 5.5 V Pin Selectable VID Format (6- or 4-bit) 16 Selectable Start-Up Currents Precision Enable to Support Custom UVLO SON-10 3-mm × 3-mm Footprint, 0.5-mm Pitch Footprint Compatible with the LM10010 The current from the IDAC_OUT pin on start-up is programmable by an external resistor to cover the range of 0 to 56.4 µA with 4 bits of resolution. The MODE pin allows programming of the device through a 4-bit parallel VID interface or through a 6-bit interface consisting of upper and lower 3-bit VID codes. The LM10011 is specifically designed to program a wide variety of Texas Instruments DC/DC converters for VID (Voltage Identification) applications. 2 Applications • • • • • Broadband, Networking, and Wireless Communications Notebook Power Solutions Portable Instruments Battery-Powered Equipment Powering Digital Loads with a 6-bit or 4-bit, 4-Pin VID Interface Device Information(1) PART NUMBER LM10011 PACKAGE BODY SIZE (NOM) WSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit VIN VIN VOUT SW 2.97V to 5.5V DC/DC RFB1 FB GND RFB2 3 5 4 6 RSET MODE EN VDD IDAC_OUT LM10011 VIDS VIDC SET VIDB GND 1 VIDA 2 0 - 59.2 µA VCORE 10 9 8 VID Interface 7 SON-10 3 mm x 3 mm 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 4 4 4 5 7 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................. 10 7.4 Device Functional Modes........................................ 11 7.5 Programming........................................................... 11 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 16 10.1 Layout Guidelines ................................................. 16 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 Trademarks ........................................................... 18 11.2 Electrostatic Discharge Caution ............................ 18 11.3 Glossary ................................................................ 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History Changes from Original (December 2012) to Revision A • 2 Page Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 5 Pin Configuration and Functions 10-PIN WSON PACKAGE TOP VIEW GND 1 10 VIDS IDAC_OUT 2 9 VIDC VDD 3 8 VIDB EN 4 7 VIDA MODE 5 6 SET DAP Pin Functions PIN NAME NUMBER I/O DESCRIPTION GND 1 – Ground IDAC_OUT 2 O Output pin of the current DAC that connects to the feedback node of the regulator. VDD 3 I Positive supply input. Operating voltage is 2.97 V to 5.5 V. It is recommended to add a small 1-nF or greater bypass capacitor from this pin to GND. EN 4 I Precision enable input. The LM10011 will operate when the EN pin voltage exceeds 1.34 V. MODE 5 – MODE will set the VID operating mode. Connecting MODE to VDD will select a 4-bit parallel interface. Connecting MODE to GND will select a 4-pin, 6-bit interface. SET 6 – A resistor connected from SET to GND will set the start-up code (current) at the IDAC_OUT pin. There are 16 different start-up codes to select from. VIDA 7 I VID digital input. In 6-bit mode: Bit 0 when VIDS transitions low; Bit 3 when VIDS transitions high. In 4-bit mode: Bit 0. VIDB 8 I VID digital input. In 6-bit mode: Bit 1 when VIDS transitions low; Bit 4 when VIDS transitions high. In 4-bit mode: Bit 1. VIDC 9 I VID digital input. In 6-bit mode: Bit 2 when VIDS transitions low; Bit 5 when VIDS transitions high. In 4-bit mode: Bit 2. VIDS 10 I VID select line. In 6-bit mode: transition low selects lower 3 bits, transition high selects upper 3 bits and updates the IDAC_OUT current to reflect the present VID code. In 4-bit mode: Bit 3. DAP DAP – Die Attach Pad. Not electrically connected to device, connect to system ground plane for reduced thermal resistance. 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD, EN, IDAC_OUT, MODE –0.3 6 V VIDA, VIDB, VIDC, VIDS –0.3 6 V 150 °C Junction Temperature (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. If Military- or Aerospace-specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 3 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com 6.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 1 kV JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX VDD 2.97 5.5 UNIT V IDAC_OUT –0.3 VDD – 1.75 V VIDA, VIDB, VIDC, VIDS, EN, MODE –0.3 5.5 V Junction Temperature −40 125 °C Ambient Temperature −40 125 °C 6.4 Thermal Information LM10011 THERMAL METRIC (1) DSC UNIT 10 PINS Junction-to-ambient thermal resistance (2) RθJA (3) 52.1 RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance (4) 26.8 ψJT Junction-to-top characterization parameter (5) 0.9 ψJB Junction-to-board characterization parameter (6) 26.9 RθJC(bot) Junction-to-case (bottom) thermal resistance (7) 7.7 (1) (2) (3) (4) (5) (6) (7) 4 30.6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 6.5 Electrical Characteristics Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range unless otherwise stated. (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 300 µA SUPPLY, UVLO, AND ENABLE Quiescent current VDD = 5.0 V, VEN = 2.0 V 260 IQ_FS IQ Quiescent current, IDAC_OUT = IFS_6 VDD = 5.0 V, VEN = 2.0 V, IFS_6 382 IQ_DIS Quiescent current disabled VDD = 5.0 V, VEN = 0.0 V VUVLO_R Undervoltage rising threshold VDD rising VUVLO_F Undervoltage falling threshold VDD falling VUVLO_HYS VEN VEN_HYS IEN 2.2 Hysteresis Enable rising threshold VEN rising Enable hysteresis µA 45 65 µA 2.65 2.95 V 2.45 V 200 mV 1.20 1.34 1.45 V 50 100 180 mV Enable pullup current 2 µA IDAC_OUT ACC Accuracy Measured at full scale ACC Accuracy Measured at full scale, 0°C to 100°C –1.25 1.25 % –1.0 1.0 % 6 LSB_6 DAC step size, 6-bit mode IFS_6 / (2 – 1) 940 nA LSB_4 DAC step size, 4-bit mode IFS_4 / (24 – 1) 3.76 µA IFS_6 Full-scale output current (6-bit mode) VID[5:0] = 000000b 59.2 µA IFS_4 Full-scale output current (4-bit mode) VID[3:0] = 0000b 56.4 INL Integral non-linearity DNL Differential non-linearity OFFSET VOUT_MAX –1 –0.25 Offset current VID[5:0] = 111111b (6-bit), VID[3:0] = 1111b (4-bit) IDAC_OUT compliance voltage VDD = 3 V, VDD-VIDAC_OUT µA 1 LSB_6 0.25 LSB_6 60 nA 1.75 V START-UP SET CURRENT (1) (2) (3) (4) VSETFSR SET pin voltage FSR SETRES SET ADC resolution SETRNG SET ADC current full-scale range 1.12 4.75 1.2 1.23 V 4 bits 56.4 µA ISET SET Current SET0 Start-up DAC error, code 0 RSET = 0 Ω, IDAC_OUT = 56.4 µA 0 5.1 5.40 0 LSB µA SET1 Start-up DAC error, code 1 RSET = 21.0 kΩ (3), IDAC_OUT = 52.7 µA 0 0 LSB SET2 Start-up DAC error, code 2 RSET = 35.7 kΩ (3), IDAC_OUT = 48.9 µA 0 0 LSB SET3 Start-up DAC error, code 3 RSET = 51.1 kΩ (3), IDAC_OUT = 45.2 µA 0 0 LSB SET4 Start-up DAC error, code 4 (4) RSET = 71.5 kΩ (3), IDAC_OUT = 41.4 µA 0 1 LSB SET5 Start-up DAC error, code 5 (4) RSET = 86.6 kΩ (3), IDAC_OUT = 37.7 µA 0 1 LSB SET6 Start-up DAC error, code 6 (4) RSET = 105 kΩ (3), IDAC_OUT = 33.9 µA 0 1 LSB SET7 Start-up DAC error, code 7 (4) RSET = 118 kΩ (3), IDAC_OUT = 30.1 µA 0 1 LSB SET8 Start-up DAC error, code 8 (4) RSET = 140 kΩ (3), IDAC_OUT =26.4 µA 0 1 LSB SET9 Start-up DAC error, code 9 (4) RSET = 154 kΩ (3), IDAC_OUT = 22.6 µA 0 1 LSB SET10 Start-up DAC error, code 10 (4) RSET = 169 kΩ (3), IDAC_OUT = 18.8 µA 0 1 LSB SET11 Start-up DAC error, code 11 (4) RSET = 182 kΩ (3), IDAC_OUT = 15.1 µA 0 1 LSB SET12 Start-up DAC error, code 12 (4) RSET = 200 kΩ (3), IDAC_OUT = 11.3 µA 0 1 LSB SET13 Start-up DAC error, code 13 (4) RSET = 215 kΩ (3), IDAC_OUT = 7.59 µA 0 1 LSB SET14 Start-up DAC error, code 14 (4) RSET = 237 kΩ (3), IDAC_OUT = 3.80 µA 0 1 LSB SET15 Start-up DAC error, code 15 RSET = 301 kΩ (3), IDAC_OUT = 0.06 µA 0 0 LSB All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section. RSET is based on 1% E96 standard resistor values. "+1" LSB implies a positive step in CODE. LSB is in reference to LSB_4. Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 5 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com Electrical Characteristics (continued) Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over –40°C to 125°C junction temperature range unless otherwise stated.(1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.75 V VID LOGIC INPUTS (5) (5) VIL Input voltage low VIH Input voltage high 1.0 V IIL Input current low –3.5 µA IIH Input current high tDEGLITCH Input deglitch time 5 3.6 µA µs t1 Input delay time VIDS rising edge 1 t2 Input hold time VIDA, VIDB, VIDC valid VIDS falling edge t3 Input delay time VIDS falling edge t4 Input hold time VIDA, VIDB, VIDC valid VIDS rising edge t5 Delay to beginning of IDAC_OUT transition Measured from VIDS rising edge 6.3 t6 IDAC_OUT transition time Time constant for exponential rise 40 µs t7 Minimum hold time in 4-bit mode VIDA, VIDB, VIDC, VIDS 4.4 µs 20 µs µs 1 20 µs µs 10 µs For VID timing, see Figure 1. 6 BIT MODE TIMING IDAC_OUT Update IDAC_OUT Update t6 IDAC_OUT Current t6 t5 t5 VID[2:0] Capture VID[5:3] Capture t2 VID[5:3] Capture t4 t3 VIDS t1 t1 VIDA,B,C 4 BIT MODE TIMING t6 t5 IDAC_OUT Current VID[0:3] Hold-Time VIDA,B,C,S tDEGLITCH t7 Figure 1. Timing Diagram for LM10011 Communications 6 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 6.6 Typical Characteristics Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5 V. All graphs show junction temperature. 390 60 VDD = 5.0V VDD = 5.0V 50 VDD CURRENT (nA) VDD CURRENT (µA) 385 380 375 370 VDD = 2.97V 365 40 30 VDD = 2.97V 20 10 360 0 -50 -25 0 25 50 75 100 125 150 -50 -81&7,217(03(5$785(Û& -25 0 25 50 75 100 125 150 -81&7,217(03(5$785(Û& C010 C003 Figure 2. Supply Current Maximum Output Current VID = [000000] Figure 3. Supply Current (EN LOW) 0.5 1.5 0.3 VDD = 5.5V GAIN ERROR (%) COMPLIANCE VOLTAGE (V) 1.6 1.4 1.3 VDD = 3.3V 1.2 0.1 -0.1 -0.3 1.1 1 -0.5 -50 -25 0 25 50 75 -50 100 125 150 -81&7,217(03(5$785(Û& -25 0 25 50 75 100 125 150 -81&7,217(03(5$785(Û& C007 C005 Figure 5. Gain Error 100 2.75 90 2.7 VDD UVLO VOLTAGE (V) OFFSET CURRENT (nA) Figure 4. Output Compliance to Positive Rail (VDD-VIDAC_OUT) 80 70 60 50 40 2.65 VDD RISING 2.6 2.55 VDD FALLING 2.5 2.45 30 20 2.4 -50 -25 0 25 50 75 100 125 150 -81&7,217(03(5$785(Û& -50 -25 0 25 50 75 100 125 150 -81&7,217(03(5$785(Û& C006 Figure 6. IDAC_OUT Offset Current VID = [111111] C009 Figure 7. UVLO Thresholds Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 7 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) Unless otherwise specified, the following conditions apply: TJ = 25°C, VDD = 5 V. All graphs show junction temperature. 0.15 INTEGRAL NON-LINEARITY (LSB) 1.45 1.4 EN VOLTAGE (V) RISING 1.35 1.3 FALLING 1.25 1.2 1.15 Û& 0.1 0.05 Û& 0 -0.05 -0.1 -0.15 -0.2 -Û& -0.25 -50 -25 0 25 50 75 0 100 125 150 10 -81&7,217(03(5$785(Û& 20 30 40 50 60 C008 C002 Figure 8. Enable (EN) Threshold DIFFERENTIAL NON-LINEARITY (LSB) 70 CODE Figure 9. Integral Non-Linearity 0.08 Û& -Û& Û& 0.06 0.04 0.02 0 -0.02 -0.04 0 10 20 30 40 50 60 70 CODE C001 Figure 10. Differential Non-Linearity 8 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 7 Detailed Description 7.1 Overview The LM10011 is a precision current DAC used for controlling any point of load regulator with an adjustable resistor feedback network. Four VID communication lines (VIDA, VIDB, VIDC, and VIDS) are used to write a 6-bit or 4-bit VID value. The output of the IDAC (IDAC_OUT) is used to inject a precision current into the feedback node of a regulator, thus adjusting the output voltage. With this method, it is possible to precisely control the output voltage of the regulator. An enable pin (EN) is provided to allow for a reduced quiescent current when not in use. Also, the VDD line is monitored so that an undervoltage event will shutdown the LM10011 (IDAC_OUT = 0.0 µA). The device is available in a 10-pad No-Pullback Package (SON-10). The LM10011 can be used in numerous applications with regulators from 2.97-V to 5.5-V supplies. 7.2 Functional Block Diagram Edge-Detector VIDS 3 µs deglitch rise 6 µs deglitch Logic Receiver Update DAC fall 3 µs deglitch D VIDC Logic Receiver 3 µs deglitch rise Q VID[5] RQ UVLO D fall Q VID[2] RQ UVLO D VIDB Logic Receiver 3 µs deglitch rise Q VID[4] RQ UVLO D fall Q VID[1] RQ UVLO D VIDA Logic Receiver 3 µs deglitch rise Q VID[3] RQ UVLO D fall EdgeDetector Q VID[0] 6-BIT MODE=0 RQ UVLO 6 bit IDAC 4-BIT MODE=1 Slew Limit IDAC_OUT 0 ± 56.4 / 59.2 µA (4-bit / 6-bit) VID[3] VID[2] VID[1] VID StartUp Current Set VID[0] RSET MODE VDD UVLO (VDD > 2.65V) DISABLE EN PRECISION ENABLE (1.34V) Bandgap Core IREF + - GND Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 9 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com 7.3 Feature Description The LM10011 can be treated as a D/A converter, converting digital VID codes to analog outputs. The LM10011 DAC analog output is a current that flows out of the IDAC_OUT pin. The IDAC_OUT pin is intended to be connected to the feedback node of a voltage regulator as shown in Figure 11. In a typical voltage regulator, the current in RFB2 is constant by virtue of the regulator feedback loop maintaining the reference voltage at the feedback node. The current flowing through RFB2 is the same current flowing through RFB1. When current is injected into the feedback node by the LM10011, less current is required from the RFB1 resistor. The consequence of this is that the output voltage of the regulator will decrease to maintain the total amount of current in RFB2 to regulate at the correct feedback (reference) voltage. Each VID code corresponds to a different IDAC_OUT current and thus a different output voltage. Increasing the VID code lowers the IDAC_OUT current and raises the output voltage. Decreasing the VID code raises the IDAC_OUT current and lowers the output voltage. All VID codes are decoded into a 6-bit or 4-bit current DAC output whether the MODE equals 0 (connected to GND) or 1 (connected to VDD), respectively. Slave Regulator VOUT + FB + RFB1 LM10011 IRFB1 IDAC_OUT VID - +- VOUT + LM10011 RFB2 VRFB1 IRFB2 VFB - - IDAC_OUT Figure 11. Output Voltage (VOUT) is Controlled Via Current Injection into the Feedback Node 7.3.1 Current DAC The LM10011 current DAC is based on a low-voltage bandgap reference setting a current through a precision adjustable resistor. This bandgap is trimmed for precision and gives excellent performance over temperature. The output current has a maximum full-scale range [VID = 000000b] of 59.2 µA and is adjustable with a 6- or 4bit VID word. This allows for 64 or 16 settings with a resolution of 940 nA or 3.76 µA, respectively. The current DAC also has a slew limit to prevent abrupt changes in the output. The slew limit is represented as a time constant, t6 = 40 µs, in the Electrical Characteristics table. A deglitch filter for the VID inputs provides noise immunity and effectively adds a small delay from the transition of a VID line to the change in IDAC_OUT current. 7.3.2 Enable Pin and UVLO The enable (EN) pin allows the output of the device to be enabled or disabled (IDAC_OUT = 0.0 µA) with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.34 V. The EN pin has 100 mV of hysteresis and will disable the output when the enable voltage falls below 1.23 V. If EN is not used, it can be left open, and will be pulled high by an internal 2-μA current source. Since the EN pin has a precise turn-on threshold it can be used along with an external resistor divider network from VDD to configure the device to turn on at a precise input voltage. The LM10011 has a built-in undervoltage lockout (UVLO) protection circuit that keeps the device from operating until the input voltage reaches 2.65 V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the LM10011 from responding to power-on glitches during start-up. Note that descending below the EN voltage and/or the UVLO voltage are functionally the same as a reset. Bringing the device back from a low enable setting or from a VDD UVLO event will reset the IDAC_OUT current to its start-up RSET setting. 10 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 7.4 Device Functional Modes Table 1 lists the functional modes of the LM10011 device. Table 1. Mode Pin Summary MODE PIN CONNECTION LOGIC STATE DESCRIPTION GND 0 6-bit mode VDD 1 4-bit mode 7.5 Programming 7.5.1 VID Programming, 6-Bit Mode Four pins are used to communicate with the LM10011. In 6-bit mode (MODE = 0), VIDA, VIDB, and VIDC are data lines, while VIDS is a latching strobe that programs in the LM10011 data. As shown in the 6-bit mode timing diagram of Figure 1, the falling edge of VIDS latches in the data from VIDA, VIDB, and VIDC as the lower three LSB of the IDAC_OUT value, [2:0]. After a minimum hold time (t2), the rising edge of VIDS latches in the data from VIDA, VIDB, and VIDC as the upper three LSB of the IDAC_OUT value, [5:3]. Internally, a delay (t3,t1) on VIDS allows for the setting of all VIDA, VIDB, and VIDC lines to change simultaneously as VIDS rises or falls. 7.5.2 VID Programming, 4-Bit Mode The LM10011 includes a 4-bit mode to facilitate parallel VID communication. In 4-bit mode (MODE = 1), VIDC, VIDB, VIDA, and VIDS are all parallel data lines. As shown in the 4-bit mode timing diagram in Figure 1, a changing edge of any of the VID communication lines will change the IDAC_OUT current to the corresponding new 4-bit value found on the data lines. There is a 3-μs deglitch filter to eliminate spurious noise events. The data must overcome the deglitch time and the minimum hold time (t7) or else the IDAC_OUT pin current may not reflect the value indicated at the VID data inputs. During the hold time, no other data line can be transitioned. As mentioned in a previous section, for both the 4-bit and 6-bit mode, the VID data word is set so that the lowest output current is seen at the highest VID data word (59.2 µA at a code of 0d in 6-bit mode and 56.4 µA in 4-bit mode). Conversely, the lowest current is seen at the highest VID data word (0.06 µA at 63d or 15d). During VID operation with the regulator, this will translate to the lowest output voltage with the lowest VID word, 0d, and the highest output voltage with the highest VID word, 63d or 15d. The communications pins can be used with a lowvoltage microcontroller with a maximum VIL of 0.75 V and a minimum VIH of 1.0 V. 7.5.3 Programming the Start-Up Current Depending on the value of RSET during start-up (when VDD > VUVLO_R and EN > VEN), the output current on the IDAC_OUT pin will take on 1 of 16 discrete values corresponding to the currents available in the 4-bit mode. These discrete start-up currents can be programmed by connecting a resistor (RSET) from the SET pin to GND. If the EN voltage is toggled or a UVLO is triggered during operation, the current will default back to the value set by the RSET resistor. It takes only one VID command transition in either 4-bit or 6-bit mode to change the current to something other than the pre-programmed start-up current. The required RSET resistors and their corresponding start-up currents codes can be found in Table 2. Table 2. Start-Up–4-Bit Mode Currents with Corresponding RSET Values and Output Currents VID CODE NOMINAL IDAC_OUT CURRENT (µA) 0000b (0d) 56.4 RSET (kΩ) 0 0001b (1d) 52.7 21.0 0010b (2d) 48.9 35.7 0011b (3d) 45.2 51.1 0100b (4d) 41.4 71.5 0101b (5d) 37.7 86.6 0110b (6d) 33.9 105 0111b (7d) 30.1 118 1000b (8d) 26.4 140 1001b (9d) 22.6 154 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 11 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com Programming (continued) Table 2. Start-Up–4-Bit Mode Currents with Corresponding RSET Values and Output Currents (continued) VID CODE NOMINAL IDAC_OUT CURRENT (µA) RSET (kΩ) 1010b (10d) 18.8 169 1011b (11d) 15.1 182 1100b (12d) 11.3 200 1101b (13d) 7.59 215 1110b (14d) 3.80 237 1111b (15d) 0.06 301 Codes 0100b (4d) through 1110b (14d) will start-up into either the selected code or 1 code higher. This means that the output voltage of the POL may start-up into the selected output voltage or 1 LSB higher. 7.5.4 IDAC_OUT Current Values Table 3. IDAC_OUT Currents and Corresponding VID Codes 12 Table 3. IDAC_OUT Currents and Corresponding VID Codes (continued) VID CODE (6-BIT [4-BIT]) IDAC CURRENT (µA) VID CODE (6-BIT [4-BIT]) IDAC CURRENT (µA) 32d 29.2 0d 59.2 33d 28.2 1d 58.3 34d 27.3 2d 57.4 35d [8d] 26.4 3d [0d] 56.4 36d 25.4 4d 55.5 37d 24.5 5d 54.6 38d 23.6 6d 53.6 39d [9d] 22.6 7d [1d] 52.7 40d 21.6 8d 51.7 41d 20.7 9d 50.8 42d 19.8 10d 49.8 43d [10d] 18.8 11d [2d] 48.9 44d 17.9 12d 48.0 45d 17.0 13d 47.0 46d 16.0 14d 46.1 47d [11d] 15.1 15d [3d] 45.2 48d 14.1 16d 44.2 49d 13.2 17d 43.3 50d 12.3 18d 42.3 51d [12d] 11.3 19d [4d] 41.4 52d 10.4 20d 40.5 53d 9.50 21d 39.5 54d 8.52 22d 38.6 55d [13d] 7.59 23d [5d] 37.7 56d 6.60 24d 36.7 57d 5.70 25d 35.7 58d 4.74 26d 34.8 59d [14d] 3.80 27d [6d] 33.9 60d 2.87 28d 33.0 61d 1.93 29d 32.0 62d 1.00 30d 31.1 63d [15d] 0.06 31d [7d] 30.1 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information LM10011 is a precision, digitally programmable device used for controlling the dc-dc converter output voltage. The LM10011 GUI design tool is available at www.ti.com/product/LM10011 and can be used to program any voltage regulator output to a desired range and resolution. The GUI enables changing the output voltage of the on-board POL based on direct user input. It is also able to assist the power designer in selecting the correct external components needed for any given application. 8.2 Typical Application In this example, an LM21215A-1 is used as the voltage regulator and the desired range of output voltage operation is 0.7 V to 1.1 V. The LM10011 can provide control of the output voltage within this range with 6 bits or 4 bits of resolution. For this example, the 400 mV of voltage range translates to a VOUT_LSB of 400 mV / 63 = 6.4 mV (26.7 mV in 4-bit mode) at the regulator output. In this calculation, 1% resistor values are used. A schematic for this example is shown in Figure 12. TSSOP-20 3V to 5.5V LF 5,6,7 VIN PVIN CIN RF 3 4 SW CC3 AVIN RFB1 LM21215A-1 FB 2 SS/ TRK CSS 0.7V to 1.1V COUT EN CF optional VOUT 11-16 COMP RC2 19 CC1 RC1 18 RFB2 CC2 17 1 PGOOD SYNC PGND AGND 20 8,9,10 CBYPASS 3 4 CVDD 5 VDD IDAC_OUT EN DVDD18 MODE LM10011 6 RSET 0 - 59.2 µA 2 VIDS VIDC VIDB SET GND 1 VIDA 10 CVDD RPU1:4 9 8 7 VCNTL[3] VCNTL[2] VCNTL[1] TMS320C6670/ TMS320C6678 VCNTL[0] SON-10 3 mm x 3 mm Figure 12. 6-Bit Mode Design Example Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 13 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com Typical Application (continued) 8.2.1 Design Requirements Table 4 lists the design parameters. Table 4. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Output voltage range 0.7 V to 1.1 V Startup voltage 1.1 V Mode 0 8.2.2 Detailed Design Procedure 8.2.2.1 Setting the VOUT Range and LSB Looking at the Typical Application Circuit in Figure 12, the following equation defines VOUT of a given regulator (valid for VOUT > VFB): VOUT = VFB x 1+ RFB1 - IDAC_OUT x RFB1 RFB2 (1) Here, the output voltage is a function of the resistor divider from RFB1 and RFB2. Using the LM10011, there is a current supplied by the IDAC_OUT pin that helps drive current through the feedback resistor RFB2, thus lowering the necessary current supplied through RFB1, and hence lowering VOUT. To calculate the nominal (maximum) VOUT, use an IDAC_OUT value of 0 µA. The change in the output voltage can be analyzed based on the resolution of the current DAC from the LM10011 compared to the desired resolution of the output swing of the regulator. RFB1 is designed to provide the desired VOUT_LSB with the equation: VOUT_LSB = LSB x RFB1 (2) Where LSB = LSB_6 (940 nA) from the electrical characteristics table (see Electrical Characteristics). Based on the desired nominal VOUT (with IDAC_OUT = 0 µA) and the calculated RFB1 from Equation 2, RFB2 can be solved using Equation 1. 8.2.2.2 4-Bit Mode Design Example Designing with the LM10011 in 4-bit mode is similar to designing in 6-bit mode. The only differences are the LSB value (LSB = LSB_4 = 3.76 µA) in Equation 2 and full-scale current range (IDAC_OUT = 56.4 µA). 8.2.2.3 Setting the Start-Up Voltage with RSET RSET is chosen depending on the required start-up voltage for the particular application. The user must use Equation 3 and solve for the required IDAC_OUT by inputting the known values of RFB1 and RFB2, VFB, and the desired start-up output voltage, VOUT. Once IDAC_OUT is solved for, choose an RSET based on Table 2 to select a start-up code to yield a current closely matching the calculated result. Use the equation below to solve for the required IDAC_OUT value at start-up. IDAC_OUT = 1 R V x 1+ FB1 - VOUT RFB1 FB RFB2 (3) 8.2.2.4 Example Solution While in 6-bit mode, assuming a 400-mV output range, 64 VID codes, and an IDAC LSB of 0.940 µA, it is desired to have a VOUT with an LSB of 6.4 mV and a default value of 1.1 V with a 1.05-V start-up voltage using an LM21215A-1 regulator (VFB = 0.6 V): 6.4mV = 0.940µA x RFB1 (4) RFB1 = 6.8k (5) Using 1% standard resistor values, RFB1 can be set to 6.81 kΩ. Now calculate RFB2 based on RFB1 and the maximum VOUT of 1.1 V using Equation 1. 14 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 1.1V = .6V x 1+ 6.81k -0V RFB2 (6) RFB2 = 8.1k (7) Using 1% standard resistor values, RFB2 can be set to 8.06 kΩ. This will yield a regulator output range of 0.704 V (CODE 0d) to 1.107 V (CODE 63d). Values calculated here will be dependent on the accuracy of the regulator, the LM10011 IDAC_OUT, and the resistor values used in the circuit. Table 5 shows the codes and some of the resultant values of the IDAC current and the corresponding regulator output voltage for the previous example. Table 5. 6-Bit VID Codes with IDAC Current and Regulator Voltage for the Example in Figure 12. VID CODE IDAC_OUT CURRENT (µA) REGULATOR VOLTAGE (V) 000000b (0d) 59.2 0.704 000001b (1d) 58.3 0.710 000010b (2d) 57.4 0.716 000011b (3d) 56.4 0.729 .... .... .... 111100b (60d) 2.87 1.087 111101b (61d) 1.93 1.094 111110b (62d) 1.00 1.100 111111b (63d) 0.06 1.107 The required IDAC_OUT value during start-up can be calculated based on the desired start-up voltage of 1.05 V and the RFB1 and RFB2 resistors found in the previous calculations. Using Equation 3 to solve for the required start-up IDAC_OUT current results in a start-up current of 8.36 µA. IDAC_OUT = 1 6.81k 0.6V x 1+ - 1.05V = 8.36µA 6.81k 8.06k (8) Choose a resistor in Table 2 that selects a start-up code that produces a current close to 8.36 µA. An RSET of 215 kΩ selects a nominal start-up code of 13d yielding a current of 7.59 µA and start-up voltage of 1.054 V. NOTE Using an RSET of 215 kΩ may also select a code of 14d (+1 LSB) yielding a current of 3.80 µA and a start-up voltage of 1.081 V. Output Voltage (V) 8.2.3 Application Curves 1.14 1.11 1.08 1.05 1.02 0.99 0.96 0.93 0.9 0.87 0.84 0.81 0.78 0.75 0.72 0.69 VIN = 2.9V VIN = 5.5V 0 5 10 15 20 25 30 35 40 45 50 55 60 65 6-Bit VID Code (Decimal) Figure 13. Output Voltage vs. Code for LM21k with LM10011 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 15 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com 9 Power Supply Recommendations The LM10011 can be driven from a PWM controller VDD pin or from the VIN supply pin as shown in Figure 12. To ensure reliable operation, the LM10011 VDD input power supply must be limited to 6 V maximum. 10 Layout 10.1 Layout Guidelines The following guidelines should be followed when designing the PC board for the LM10011: • Place the LM10011 close to the regulator feedback pin to minimize the FB trace length. • Place a small capacitor, CVDD, (1 nF) directly adjacent to the VDD and GND pins of the LM10011 to help minimize transients which may occur on the input supply line. • The high-current path from the board input to the load and the return path should be parallel and close to each other to minimize loop inductance. • The ground connections for the various components around the LM10011 should be connected directly to each other, and to the LM10011 GND pins, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high-current ground line. • For additional information about the operation of the regulator, please consult the respective data sheet and application notes on the respective evaluation boards. 16 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 LM10011 www.ti.com SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 10.2 Layout Example Figure 14. Typical Top Layer Layout Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 17 LM10011 SNVS822A – DECEMBER 2012 – REVISED NOVEMBER 2014 www.ti.com 11 Device and Documentation Support 11.1 Trademarks All trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2012–2014, Texas Instruments Incorporated Product Folder Links: LM10011 PACKAGE OPTION ADDENDUM www.ti.com 20-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM10011SD/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L271B LM10011SDX/NOPB ACTIVE WSON DSC 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L271B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM10011SD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM10011SDX/NOPB WSON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM10011SD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 LM10011SDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DSC0010A SDA10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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