LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 LM20134/LM20134Q 4A, PowerWise® Synchronous Buck Regulator with Input Synchronization Check for Samples: LM20134, LM20134Q FEATURES DESCRIPTION • The LM20134 is a full featured synchronous buck regulator capable of delivering up to 4A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor. For most cases, compensating the device only requires two external components, providing maximum flexibility and ease of use. The device is optimized to work over the input voltage range of 2.95V to 5.5V making it suited for a wide variety of low voltage systems. 1 2 • • • • • • • • • • • • • LM20134Q is AEC-Q100 Qualified and Manufactured on an Automotive Grade Flow Input Voltage Range 2.95V to 5.5V Accurate Current Limit Minimizes Inductor Size 97% Peak Efficiency Frequency Synchronization Pin 32 mΩ Integrated FET Switches Starts up into Pre-Biased Loads Output Voltage Tracking Peak Current Mode Control Adjustable Output Voltage Down to 0.8V Adjustable Soft-Start with External Capacitor Precision Enable Pin with Hysteresis Integrated OVP, UVLO, Power Good and Thermal Shutdown HTSSOP 16-Pin Exposed Pad Package The device features internal over voltage protection (OVP) and over current protection (OCP) circuits for increased system reliability. A precision enable pin and integrated UVLO allows the turn on of the device to be tightly controlled and sequenced. Start-up inrush currents are limited by both an internally fixed and externally adjustable Soft-Start circuit. Fault detection and supply sequencing is possible with the integrated power good circuit. The switching frequency of the LM20134 can be synchronized to an external clock by use of the SYNC pin. The SYNC pin is capable of synchronizing to input signals ranging from 500 kHz to 1.5 MHz APPLICATIONS • • • Simple to Design, High Efficiency Point of Load Regulation from a 5V or 3.3V Bus High Performance DSPs, FPGAs, ASICs and Microprocessors Broadband, Networking and Optical Communications Infrastructure The LM20134 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track a higher voltage rail using the SS/TRK pin. If the output of the LM20134 is pre-biased at startup it will not sink current to pull the output low until the internal soft-start ramp exceeds the voltage at the feedback pin. Typical Application Circuit L LM20134 PVIN VIN CIN RFB1 EN RF VOUT SW FB COUT AVIN SYNC CF COMP RC1 CC1 RFB2 PGOOD VCC SS/TRK PGND AGND CVCC CSS (optional) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION CONTINUED The LM20134 is offered in a 16-pin HTSSOP package with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heatsinks. Connection Diagram Top View SS/TRK 1 16 SYNC FB 2 15 AGND PGOOD 3 14 AVIN COMP 4 13 VCC NC 5 12 EN PVIN 6 11 PGND PVIN 7 10 PGND SW 8 9 EP SW See Package Number PWP0016A Pin Descriptions 2 Pin # Name 1 SS/TRK 2 FB 3 PGOOD 4 COMP 5 NC 6,7 PVIN Description Soft-Start or Tracking control input. An internal 5 µA current source charges an external capacitor to set the Soft-Start ramp rate. If driven by a external source less tan 800 mV, this pin overrides the internal reference that sets the output voltage. If left open, an internal 1ms Soft-Start ramp is activated. Feedback input to the error amplifier from the regulated output. This pin is connected to the inverting input of the internal transconductance error amplifier. An 800 mV reference connected to the non-inverting input of the error amplifier sets the closed loop regulation voltage at the FB pin. Power good output signal. Open drain output indicating the output voltage is regulating within tolerance. A pull-up resistor of 10 to 100 kΩ is recommend for most applications. External compensation pin. Connect a resistor and capacitor to this pin to compensate the device. These pins must be connected to GND to ensure proper operation. Input voltage to the power switches inside the device. These pins should be connected together at the device. A low ESR capacitor should be placed near these pins to stabilize the input voltage. 8,9 SW 10,11 PGND Switch pin. The PWM output of the internal power switches. 12 EN 13 VCC Internal 2.7V sub-regulator. This pin should be bypassed with a 1 µF ceramic capacitor. 14 AVIN Analog input supply that generates the internal bias. Must be connected to VIN through a low pass RC filter. 15 AGND Quiet analog ground for the internal bias circuitry. 16 SYNC Frequency synchronization pin. An external clock connected to this pin will set the switching frequency. If left open the device will operate at approximately 410 kHz. EP Exposed Pad Power ground pin for the internal power switches. Precision enable input for the device. An external voltage divider can be used to set the device turn-on threshold. If not used the EN pin should be connected to PVIN. Exposed metal pad on the underside of the package with a weak electrical connection to ground. It is recommended to connect this pad to the PC board ground plane in order to improve heat dissipation. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, SW, SYNC -0.3V to +6V Storage Temperature -65°C to 150°C Junction Temperature 150°C (2) 2.6W Lead Temperature (Soldering, 10 sec) 260°C Power Dissipation Minimum ESD Rating (3) (1) (2) (3) ±2kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not specific performance limits. For specifications and test conditions, see the Electrical Characteristics. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junctions-to-ambient thermal resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX – TA)/θJA. The maximum power dissipations of 2.6W is determined using TA = 25°C, θJA = 38°C/W, and TJ_MAX = 125°C. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin. OPERATING RATINGS PVIN, AVIN to GND 2.95V to 5.5V −40°C to + 125°C Junction Temperature Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 3 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified by through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions Feedback pin voltage VIN = 2.95V to 5.5V Load Regulation IOUT = 100 mA to 4A Switch Current Limit Threshold VIN = 3.3V RDS_ON High-Side Switch On Resistance RDS_ON Low-Side Switch On Resistance IQ VFB ΔVOUT/ΔIOUT ICL Min 0.788 Typ Max 0.8 0.812 0.08 V %/A 6.4 7.9 A ISW = 3.5A 36 55 mΩ ISW = 3.5A 32 52 mΩ Operating Quiescent Current Non-switching, VFB = VCOMP 3.5 6 mA ISD Shutdown Quiescent current VEN = 0V µA VUVLO VIN Under Voltage Lockout Rising VIN VIN Under Voltage Lockout Hysteresis Falling VIN VCC Voltage IVCC = 0 µA ISS Soft-Start Pin Source Current VSS/TRK = 0V VTRACK SS/TRK Accuracy, VSS - VFB VSS/TRK = 0.4V VSYNC = Static 360 VUVLO_HYS VVCC 5.8 Unit 90 180 2.7 2.95 V 45 100 mV 2.45 2.7 2.95 V 2 4.5 7 µA -10 3 15 mV 410 460 kHz 2.45 Oscillator and Clock Synchronization FOSC Oscillator Frequency FOSCH Maximum SYNC Frequency FOSCL Minimum SYNC Frequency VIH_SYNC SYNC pin Logic High VIL_SYNC SYNC pin Logic Low ISYNC DCMAX 1500 kHz 460 kHz 2 V 0.8 V SYNC pin input leakage VSYNC = 5V 10 nA Maximum Duty Cycle ILOAD = 0A 85 % 100 ns 80 ns TON_TIME Minimum On Time TCL_BLANK Current Sense Blanking Time After Rising VSW Error Amplifier and Modulator Feedback pin bias current VFB = 0.8V ICOMP_SRC IFB COMP Output Source Current VFB = VCOMP = 0.6V 80 100 µA ICOMP_SNK COMP Output Sink Current VFB = 1.0V, VCOMP = 0.6V 80 100 µA Error Amplifier Transconductance ICOMP = ± 50 µA 450 gm AVOL 1 Error Amplifier Voltage Gain 510 100 600 2000 nA µmho V/V Power Good VOVP VOVP_HYS Over Voltage Protection Rising Threshold With respect to VFB 105 108 With respect to VFB 92 2 Over Voltage Protection Hysteresis VPGTH PGOOD Rising Threshold VPGHYS PGOOD Falling Hysteresis TPGOOD PGOOD deglitch time IOL PGOOD Low Sink Current VPGOOD = 0.4V IOH PGOOD High Leakage Current VPGOOD = 5V EN Pin Turn on Threshold VEN Rising 0.6 111 % 2 3 % 94 96 % 3 % 16 µs 1 mA 5 100 1.18 1.28 nA Enable VIH_EN VEN_HYS 1.08 EN Pin Hysteresis V 66 mV Thermal Shutdown 160 °C Thermal Shutdown Hysteresis 10 °C 38 °C/W Thermal Shutdown TSD TSD_HYS Thermal Resistance θJA 4 Junction to Ambient Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V, fSW = 1 MHz) Efficiency vs. Load Current (VIN = 3.3V, fSW = 1 MHz) Figure 1. Figure 2. Efficiency vs. Load Current (VIN = 5V, fSW = 500 kHz) Efficiency vs. Load Current (VIN = 3.3V, fSW = 500 kHz) Figure 3. Figure 4. High-Side FET resistance vs. Temperature Low-Side FET resistance vs. Temperature Figure 5. Figure 6. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 5 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Error Amplifier Gain vs. Frequency Line Regulation Figure 7. Figure 8. Load Regulation Feedback Pin Voltage vs. Temperature Figure 9. Figure 10. Switching Frequency vs. Temperature Switch Synchronization Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Quiescent Current vs. Temperature (Not Switching) Shutdown Current vs. VIN Figure 13. Figure 14. Enable Threshold vs. Temperature UVLO Threshold vs. Temperature Figure 15. Figure 16. Peak Current Limit vs. Temperature Peak Current Limit vs. VOUT Figure 17. Figure 18. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 7 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 8 Peak Current Limit vs. VIN Load Transient Response Figure 19. Figure 20. Line Transient Response Start-Up (Soft-Start) Figure 21. Figure 22. Start-Up (Tracking) Power Down Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Short Circuit Input Current vs. VIN PGOOD vs. IPGOOD Figure 25. Figure 26. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 9 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM +2.7V REGULATOR AVIN 2.7V VCC UVLO + - SLOPE COMP PVIN COMP 2.7V CURRENT SENSE + 5 PA DISCHARGE (50 Ps) SS/TRK ERROR AMP gm = 510 Pmho + + FB 6.4A VREF + - 800 mV DISCHARGE CURRENT LIMIT + - PVIN + - 864 mV PWM COMPARATOR OVERVOLTAGE + - PG-L 752 mV UNDERVOLTAGE + - DIODE EMULATION CONTROL LOGIC + - SW PVIN THERMAL PROTECTION EN 1.18V + - PGND PG-L OSCILLATOR PGOOD SYNC AGND 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 OPERATION DESCRIPTION GENERAL The LM20134 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 4A of continuous output current. The regulator utilizes peak current mode control with nonlinear slope compensation to optimize stability and transient response over the entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle current limiting and easy loop compensation. The internal oscillator can synchronize up to 1.5 MHz minimizing the inductor size while still achieving efficiencies up to 96%. The precision internal voltage reference allows the output to be set as low as 0.8V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the HTSSOP 16-pin package featuring an exposed pad to aid thermal dissipation. The LM20134 can be used in numerous applications to efficiently stepdown from a 5V or 3.3V bus. The typical application circuit for the LM20134 is shown in Figure 28 in the design guide. PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN pin is not used, it should be connected to VIN. Since the enable pin has a precise turn on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn on at a precise input voltage. The precision enable circuitry will remain active even when the device is disabled. FREQUENCY SYNCHRONIZATION The frequency synchronization pin (SYNC) allows the switching frequency of the device to be controlled with an external clock signal. This feature allows the user to synchronize multiple converters, avoiding undesirable frequency bands of operation. When used with the SYNCOUT of the LM20154, multiple devices can be configured to switch out of phase reducing input capacitor requirements and EMI of the power supply system. The turn on of the high-side switch will lock-on to the rising edge of the SYNC pin input. The logic low level for the input clock must be below 0.8V and the logic high level must exceed 2.0V for proper operation. The device will synchronize to frequencies from 500 kHz to 1.5 MHz. If the synchronization clock is removed or not present during startup, the oscillator of the device will run at approximately 410 kHz. If the SYNC pin is not used it should be connected to ground. PEAK CURRENT MODE CONTROL In most cases, the peak current mode control architecture used in the LM20134 only requires two external components to achieve a stable design. The compensation can be selected to accommodate any capacitor type or value. The external compensation also allows the user to set the crossover frequency and optimize the transient performance of the device. For duty cycles above 50% all current mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What makes the LM20134 unique is the amount of slope compensation will change depending on the output voltage. When operating at high output voltages the device will have more slope compensation than when operating at lower output voltages. This is accomplished in the LM20134 by using a non-linear parabolic ramp for the slope compensation. The parabolic slope compensation of the LM20134 is much better than the traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage range. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 11 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com CURRENT LIMIT The precise current limit of the LM20134 is set at the factory to be within 10% over the entire operating temperature range. This enables the device to operate with smaller inductors that have lower saturation currents. When the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side FET turns off and the low-side FET turns on allowing the inductor current to ramp down until the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions. SOFT-START AND VOLTAGE TRACKING The SS/TRK pin is a dual function pin that can be used to set the start up time or track an external voltage source. The start up or Soft-Start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground. The Soft-Start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling start up current. If no Soft-Start capacitor is used the device defaults to the internal Soft-Start circuitry resulting in a start up time of approximately 1ms. For applications that require a monotonic start up or utilize the PGOOD pin, an external Soft-Start capacitor is recommended. The SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two external resistors connected to the SS/TRK pin as shown in Figure 33 in the design guide. PRE-BIAS START UP CAPABILITY The LM20134 is in a pre-biased state when the device starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM20134 is a synchronous converter it will not pull the output low when a pre-bias condition exists. During start up condition the LM20134 will not sink current until the Soft-Start voltage exceeds the voltage on the FB pin. Since the device can not sink current it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load. POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20134 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage falls back into regulation or the zero cross detection is triggered which in turn tri-states the FETs. If the output reaches the UVP threshold the part will continue switching and the PGOOD pin will be asserted and go low. Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient glitches the PGOOD pin has 16 µs of built in deglitch time to both rising and falling edges. UVLO The LM20134 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 45 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 32 in the design guide. THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the LM20134 tri-states the power FETs and resets soft start. After the junction cools to approximately 150°C, the part starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. LIGHT LOAD OPERATION The LM20134 offers increased efficiency when operating at light loads. Whenever the load current is reduced to a point where the peak to peak inductor ripple current is greater than two times the load current, the part will enter the diode emulation mode preventing significant negative inductor current. The point at which this occurs is the critical conduction boundary and can be calculated by the following equation: 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com IBOUNDARY = SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 (VIN ± VOUT) x D 2 x L x fSW (1) Several diagrams are shown in Figure 27 illustrating continuous conduction mode (CCM), discontinuous conduction mode, and the boundary condition. It can be seen that in diode emulation mode, whenever the inductor current reaches zero the SW node will become high impedance. Ringing will occur on this pin as a result of the LC tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional RC snubber circuit can be added from the switch node to ground. At very light loads, usually below 100mA, several pulses may be skipped in between switching cycles, effectively reducing the switching frequency and further improving light-load efficiency. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 13 LM20134, LM20134Q Switchnode Voltage SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 27. Modes of Operation for LM20134 Design Guide This section walks the designer through the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion. To facilitate component selection discussions the circuit shown in Figure 28 below may be used as a reference. Unless otherwise indicated all formulas assume units of amps (A) for current, farads (F) for capacitance, henries (H) for inductance and volts (V) for voltages. 14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 L LM20134 PVIN SW VIN VOUT RFB1 EN RF AVIN CIN FB CF VIN COUT RFB2 RPG SYNC COMP RC1 CC1 x PGOOD VCC SS/TRK PGND GND VPG CVCC CSS Figure 28. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by: D= VOUT VIN (2) INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current, and duty cycle. The inductor selected should have a saturation current rating greater than the peak current limit of the device. Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the current limit in the application may be higher than the specified value. To optimize the performance and prevent the device from entering current limit at maximum load, the inductance is typically selected such that the ripple current, ΔiL, is less than 30% of the rated output current. Figure 29, shown below illustrates the switch and inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency, and desired ripple current are known, the minimum value for the inductor can be calculated by the formula shown below: LMIN = (VIN - VOUT) x D 'iL x fSW (3) VSW VIN Time IL IL AVG = IOUT 'IL Time Figure 29. Switch and Inductor Current Waveforms If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be greater than 10% of the rated output current to provide adequate current sense information for the current mode control loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense information and can be prone to instability. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 15 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20134 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the formula shown below. 'VOUT = 'iL x ESR + 1 8 x fSW x COUT where • • • • ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output RESR (Ω) is the series resistance of the output capacitor fSW(Hz) is the switching frequency COUT (F) is the output capacitance used in the design (4) The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation. VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP2 COUT x (VIN - VOUT) where • • • • • • • COUT (F) is the minimum required output capacitance L (H) is the value of the inductor VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations ΔIOUTSTEP (A) is the load step change RESR (Ω) is the output capacitor ESR VIN (V) is the input voltage VOUT (V) is the set regulator output voltage (5) Both the tolerance and voltage coefficient of the capacitor needs to be examined when designing for a specific output ripple or transient drop target. INPUT CAPACITOR SELECTION (CIN) Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC voltage derating that occurs on Y5V capacitors. For most applications, a 22 µF, X5R, 6.3V input capacitor is sufficient; however, additional capacitance may be required if the connection to the input supply is far from the PVIN pins. The input capacitor should be placed as close as possible PVIN and PGND pins of the device. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: IIN-RMS = IOUT D(1 - D) 16 Submit Documentation Feedback (6) Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. SETTING THE OUTPUT VOLTAGE (RFB1, RFB2) The resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 1, shown below, provides suggestions for RFB1 and RFB2 for common output voltages. Table 1. Suggested Values for RFB1 and RFB2 RFB1(kΩ) RFB2(kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be calculated using the equation below. RFB1 = VOUT 0.8 - 1 x RFB2 (7) LOOP COMPENSATION (RC1, CC1) The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load, and the device itself. Table 2 below gives values for the compensation network that will result in a stable system when using a 100 µF, 6.3V ceramic X5R output capacitor and 1 µH inductor. Table 2. Recommended Compensation for COUT = 100 µF, L = 1 µH & fSW = 1 MHz VIN VOUT CC1 (nF) RC1 (kΩ) 5.00 3.30 4.7 13.3 5.00 2.50 4.7 11 5.00 1.80 4.7 6.81 5.00 1.50 4.7 4.53 5.00 1.20 4.7 3.09 5.00 0.80 4.7 1.33 3.30 1.80 4.7 8.06 3.30 1.50 4.7 5.23 3.30 1.20 4.7 3.16 3.30 0.80 4.7 1.33 If the desired solution differs from the table above the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions. For stability purposes, the objective is to have a loop gain slope that is -20db/decade from a very low frequency to beyond the crossover frequency. Figure 30, shown below, shows the transfer functions for power stage, feedback/compensation network, and the resulting closed loop system for the LM20134. Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 17 LM20134, LM20134Q www.ti.com Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 Optional Error Amp Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Compensated Closed Loop Transfer Function Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 30. LM20134 Loop Compensation The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback transfer function is set by the feedback resistor ratio, error amp gain, and external compensation network. To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should positioned to cancel the output filter pole (fP(FIL)). An additional error amp pole, located at fP2(EA), can be added to cancel the output filter zero at (fZ(FIL)). Cancellation of the output filter zero is recommended if larger value, non-ceramic output capacitors are used. Compensation of the LM20134 is achieved by adding an RC network as shown in Figure 31 below. LM20134 COMP RC1 CC2 (optional) CC1 Figure 31. Compensation Network for LM20134 A good starting value for CC1 for most applications is 4.7 nF. Once the value of CC1 is chosen the value of RC should be calculated using the equation below to cancel the output filter pole (fP(FIL)) as shown in Figure 30. RC1 = 15 x D CC1 IOUT 1-D x + + VIN COUT VOUT fSW x L -1 (8) A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of CC1 and recalculating the value of RC1. Likewise, increaseing CC1 and recalculating RC1 will provide additional phase margin at a lower crossover frequency. As with any attempt to compensate the LM20134 the stability of the system should be verified for desired transient droop and settling time. If the output filter zero, (fZ(FIL)) approaches the crossover frequency (FC), an additional capacitor (CC2) should be placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero is set by the output capacitor value and ESR as shown in the equation below. 18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 fZ(FIL) = 1 2 x S x COUT x RESR (9) If needed, the value for CC2 should be calculated using the equation shown below. COUT x RESR CC2 = RC1 where • • RESR is the output capacitor series resistance RC1 is the calculated compensation resistance (10) AVIN FILTERING COMPONENTS (CF and RF) To prevent high frequency noise spikes from disturbing the sensitive analog circuitry connected to the AVIN and AGND pins, a high frequency RC filter is required between PVIN and AVIN. These components are shown in Figure 28 as CF and RF. The required value for RF is 1Ω. CF must be used. Recommended value of CF is 1.0 µF. The filter capacitor, CF should be placed as close to the IC as possible with a direct connection from AVIN to AGND. A good quality X5R or X7R ceramic capacitor should be used for CF. SUB-REGULATOR BYPASS CAPACITOR (CVCC) The capacitor at the VCC pin provides noise filtering and stability for the internal sub-regulator. The recommended value of CVCC should be no smaller than 1 µF and no greater than 10 µF. The capacitor should be a good quality ceramic X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. SETTING THE START UP TIME (CSS) The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will reach the final regulated value. Larger values for CSS will result in longer start up times. Table 3, shown below provides a list of soft start capacitors and the corresponding typical start up times. Table 3. Start Up Times for Different Soft-Start Capacitors Start Up Time (ms) CSS (nF) 1 none 5 33 10 68 15 100 20 120 If different start up times are needed the equation shown below can be used to calculate the start up time. tSS = 0.8V x CSS ISS (11) As shown above, the start up time is influenced by the value of the Soft-Start capacitor CSS(F) and the 5 µA SoftStart pin current ISS(A). that may be found in the electrical characteristics table. While the Soft-Start capacitor can be sized to meet many start up requirements, there are limitations to its size. The Soft-Start time can never be faster than 1ms due to the internal default 1ms start up time. When the device is enabled there is an approximate time interval of 50 µs when the Soft-Start capacitor will be discharged just prior to the Soft-Start ramp. If the enable pin is rapidly pulsed or the Soft-Start capacitor is large there may not be enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging the Soft-Start capacitor during long disable periods an external 1 MΩ resistor from SS/TRK to ground can be used without greatly affecting the start-up time. USING PRECISION ENABLE AND POWER GOOD The precision enable(EN) and power good(PGOOD) pins of the LM20134 can be used to address many sequencing requirements. The turn-on of the LM20134 can be controlled with the precision enable pin by using two external resistors as shown in Figure 32 Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 19 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com External Power Supply VOUT1 LM20134 RA VOUT2 EN RB Figure 32. Sequencing LM20134 with Precision Enable The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for RB is chosen the resistor RA can be solved using the equation below to set the desired turn-on voltage. RA = VTO VIH_EN - 1 x RB (12) When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold (VIH_EN), and external resistors needs to be considered to insure proper turn-on of the device. The LM20134 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high while when the output is within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ. TRACKING AN EXTERNAL SUPPLY By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 33, the output of the LM20134 can be configured to track an external voltage source to obtain a simultaneous or ratiometric start up. External Power Supply EN VOUT1 R1 LM20134 VOUT2 SS/TRK R2 Figure 33. Tracking an External Supply Since the Soft-Start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 34, to give the desired start up. Figure 34 shows two common start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates a ratiometric start up. 20 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 34. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A simultaneous start up provides a more robust power up for these applications since it avoids turning on any parasitic conduction paths that may exist between the core and the I/O pins of the processor.. The second most common power on behavior is known as a ratiometric start up. This start up is preferred in applications where both supplies need to be at the final value at the same time. Similar to the Soft-Start function, the fastest start up possible is 1ms regardless of the rise time of the tracking voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide sufficient overdrive and transient immunity. THERMAL CONSIDERATIONS The thermal characteristics of the LM20134 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PDθJA + TA (13) and PD = PIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR where • • • • • • TJ is the junction temperature in °C PIN is the input power in Watts (PIN = VIN x IIN) θJA is the junction to ambient thermal resistance for the LM20134 TA is the ambient temperature in °C IOUT is the output load current DCR is the inductor series resistance Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q (14) Submit Documentation Feedback 21 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction temperature exceeds 160°C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 35, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB heatsink area consists of 2oz. copper located on the bottom layer of the PCB directly under the HTSSOP exposed pad. The bottom copper area is connected to the HTSSOP exposed pad by means of a 4 x 4 array of 12 mil thermal vias. Figure 35. Thermal Resistance vs PCB Area PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched very fast. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator PGND pins, to the inductor and then out to the load (see Figure 36). To minimize both loop areas the input capacitor should be placed as close as possible to the PVIN pin. Grounding for both the input and output capacitor should consist of a small localized top side plane that connects to PGND and the die attach pad (DAP). The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. Since the LM20134 has the SW pins on opposite sides of the package it is recommended to via these pins down to the bottom or internal layer with 2 to 4 vias on each SW pin. The SW pins should be directly connected with a trace that runs across the bottom of the package. To minimize IR losses this trace should be no smaller that 50 mils wide, but no larger than 100 mils wide to keep the copper area to a minimum. In general the SW pins should not be connected on the top layer since it could block the ground return path for the power ground. The inductor should be placed as close as possible to one of the SW pins to further minimize the copper area of the switch node. 3. Have a single point ground for all device analog grounds located under the DAP. The ground connections for the compensation, feedback, and Soft-Start components should be connected together then routed to the AGND pin of the device. The AGND pin should connect to PGND under the DAP. This prevents any switched or load currents from flowing in the analog ground plane. If not properly handled poor grounding can result in degraded load regulation or erratic switching behavior. 4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output resistor divider to FB pin should be as short as possible. This is most important when high value resistors are used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. 22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. If voltage accuracy at the load is important make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. 6. Provide adequate device heatsinking. Use as many vias as is possible to connect the DAP to the power plane heatsink. For best results use a 4x4 via array with a minimum via diameter of 12 mils. See the Thermal Considerations section to insure enough copper heatsinking area is used to keep the junction temperature below 125°C. LM20134 L SW PVIN VOUT CIN COUT PGND LOOP1 LOOP2 Figure 36. Schematic of LM20134 Highlighting Layout Sensitive Nodes Typical Application Circuits This section provides several application solutions with a bill of materials. All bill of materials reference the below figure. The compensation for these solutions were optimized to work over a wide range of input and output voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as outline in the design guide. L LM20134 PVIN VIN CIN RFB1 EN RF VOUT SW FB COUT AVIN SYNC CF COMP RC1 CC1 RFB2 PGOOD VCC SS/TRK PGND AGND CVCC CSS (optional) Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 23 LM20134, LM20134Q SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Bill of Materials (VIN = 5V, VOUT = 3.3V, IOUTMAX = 4A, FSYNC = 750kHz) Designator Description Part Number Manufacturer Qty U1 Synchronous Buck Regulator LM20134 Texas Instruments 1 CIN 47 µF, 1210, X5R, 6.3V GRM32ER60J476ME20 Murata 1 COUT 47 µF, 1210, X5R, 6.3V GRM32ER60J476ME20 Murata 1 L 1.5 µH, 8.1 mΩ MSS1038-152NL Coilcraft 1 RF 1Ω, 0603 CRCW06031R0J-e3 Vishay-Dale 1 CF 100 nF, 0603, X7R, 16V GRM188R71C104KA01 Murata 1 CVCC 1 µF, 0603, X5R, 6.3V GRM188R60J105KA01 Murata 1 RC1 10 kΩ, 0603 CRCW06031002F-e3 Vishay-Dale 1 CC1 1.8 nF, 0603, X7R, 25V VJ0603Y182KXXA Vishay-Vitramon 1 CSS 33 nF, 0603, X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 RFB1 31.6 kΩ, 0603 CRCW06033162F-e3 Vishay-Dale 1 RFB2 10.2 kΩ, 0603 CRCW06031022F-e3 Vishay-Dale 1 Bill of Materials (VIN = 3.3V or 5V, VOUT = 1.2V, IOUTMAX = 4A, FSYNC = 750kHz) 24 Designator Description Part Number Manufacturer Qty U1 Synchronous Buck Regulator LM20134 Texas Instruments 1 CIN 47 µF, 1210, X5R, 6.3V GRM32ER60J476ME20 Murata 1 COUT 47 µF, 1210, X5R, 6.3V GRM32ER60J476ME20 Murata 1 L 1.5 µH, 8.1 mΩ MSS1038-152NL Coilcraft 1 RF 1Ω, 0603 CRCW06031R0J-e3 Vishay-Dale 1 CF 100 nF, 0603, X7R, 16V GRM188R71C104KA01 Murata 1 CVCC 1 µF, 0603, X5R, 6.3V GRM188R60J105KA01 Murata 1 RC1 10 kΩ, 0603 CRCW06031002F-e3 Vishay-Dale 1 CC1 2.2 nF, 0603, X7R, 25V VJ0603Y222KXXA Vishay-Vitramon 1 CSS 33 nF, 0603, X7R, 25V VJ0603Y333KXXA Vishay-Vitramon 1 RFB1 4.99 kΩ, 0603 CRCW06034991F-e3 Vishay-Dale 1 RFB2 10 kΩ, 0603 CRCW06031002F-e3 Vishay-Dale 1 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q LM20134, LM20134Q www.ti.com SNVS527G – OCTOBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 23 Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LM20134 LM20134Q Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LM20134MH/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20134 MH LM20134MHE/NOPB ACTIVE HTSSOP PWP 16 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20134 MH LM20134MHX/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20134 MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20134MHE/NOPB HTSSOP PWP 16 250 178.0 12.4 LM20134MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 6.95 8.3 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20134MHE/NOPB HTSSOP PWP LM20134MHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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