MTN2302N3

CYStech Electronics Corp.
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 1/8
20V N-CHANNEL Enhancement Mode MOSFET
MTN2302N3
BVDSS
20V
ID
RDSON(MAX)@VGS=4.5V, ID=3.6A
3.6A
29mΩ(typ.)
RDSON(MAX)@VGS=2.5V, ID=3.1A
39mΩ(typ.)
Features
• Simple drive requirement
• Small package outline
• Capable of 2.5V gate drive
• Pb-free lead plating and halogen-free package
Symbol
Outline
MTN2302N3
SOT-23
D
G：Gate
S：Source
D：Drain
G
S
Absolute Maximum Ratings (Ta=25°C)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current @VGS=4.5V, TA=25°C (Note 3)
Continuous Drain Current @VGS=4.5V, TA=70°C (Note 3)
Pulsed Drain Current (Notes 1, 2)
Maximum Power Dissipation@ TA=25℃
Linear Derating Factor
Operating Junction and Storage Temperature
Symbol
VDS
VGS
ID
IDM
PD
Tj, Tstg
Limits
20
±12
3.6
2.9
10
1.38 (Note 3)
0.01
-55~+150
Unit
V
V
A
A
A
W
W/°C
°C
Note : 1. Pulse width limited by maximum junction temperature.
2. Pulse width≤ 300μs, duty cycle≤2%.
3. Surface mounted on 1 in² copper pad of FR-4 board, t≤5s; 270°C/W when mounted on minimum copper pad.
MTN2302N3
CYStek Product Specification
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 2/8
CYStech Electronics Corp.
Thermal Performance
Parameter
Symbol
Limit
Unit
Thermal Resistance, Junction-to-Ambient, max
RθJA
90
°C/W
Thermal Resistance, Junction-to-Case, max
RθJC
80
°C/W
Note : Surface mounted on 1 in² copper pad of FR-4 board, t≤5s; 270°C/W when mounted on minimum copper pad.
Electrical Characteristics (Tj=25°C, unless otherwise noted)
Symbol
Static
BVDSS
∆BVDSS/∆Tj
VGS(th)
IGSS
IDSS
*RDS(ON)
*GFS
Dynamic
Ciss
Coss
Crss
td(ON)
tr
td(OFF)
tf
Qg
Qgs
Qgd
Source-Drain Diode
*VSD
IS
ISM
Min.
Typ.
Max.
Unit
20
0.5
-
0.1
0.7
29
39
7.5
1.2
±100
1
10
55
70
-
V
V/°C
V
nA
μA
μA
-
440
61
59
4.5
7.4
19
7.2
4.4
0.7
1.7
-
-
0.8
-
1.2
1
10
Test Conditions
S
VGS=0, ID=250μA
Reference to 25°C, ID=1mA
VDS=VGS, ID=250μA
VGS=±12V, VDS=0
VDS=20V, VGS=0
VDS=20V, VGS=0 (Tj=70°C)
ID=3.6A, VGS=4.5V
ID=3.1A, VGS=2.5V
VDS=5V, ID=3.6A
pF
VDS=10V, VGS=0, f=1MHz
ns
VDS=10V, ID=3.6A, VGS=5V
RG=6Ω, RD=2.8Ω
nC
VDS=10V, ID=3.6A, VGS=4.5V
V
VGS=0V, IS=1.6A
A
VD=VG=0V, VS=1.2V
mΩ
*Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2%
Ordering Information
Device
MTN2302N3-0-T1-G
MTN2302N3
Package
SOT-23
(Pb-free lead plating and halogen-free package)
Shipping
3000 pcs / Tape & Reel
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 3/8
Typical Characteristics
Static Drain-Source On-resistance vs Ambient Temperature
Typical Output Characteristics
50
4.5V
3.5V
3V
2.5V
ID, Drain Current(A)
8
RDS(on) , Static Drain-Source On-state
Resistance(mΩ)
10
VGS=2V
6
4
VGS=1.5V
2
45
ID=3.6A, VGS=4.5V
40
35
30
25
20
15
10
5
0
0
0
0.5
1
1.5
2
2.5
-60
3
-20
VDS, Drain-Source Voltage(V)
10000
10000
IF, Forward Drain Current(mA)
R DS(on), Static Drain-Source On-State
Resistance(mΩ)
180
Forward Drain Current vs Source-Drain Voltage
Static Drain-Source On-State resistance vs Drain Current
1000
VGS=1.5V
VGS=2V
VGS=2.5V
100
Tj=25°C
VGS=0V
1000
100
10
VGS=4.5V
1
10
1
10
100
1000
ID, Drain Current(mA)
0.4
10000
TA=25°C
ID=3.1A
Ciss
Capacitance-(pF)
400
1.4
1000
500
450
0.6
0.8
1
1.2
VSD, Source Drain Voltage(V)
Capacitance vs Reverse Voltage
Static Drain-Source On-State Resistance vs Gate-Source
Voltage
R DS(on), Static Drain-Source OnState Resistance(mΩ)
20
60
100
140
TA, Ambient Temperature(°C)
350
300
250
200
150
100
Coss
Crss
100
f=1MHz
50
10
0
0
MTN2302N3
1
2
3
4
VGS, Gate-Source Voltage(V)
5
0
2
4
6
8 10 12 14 16
VDS , Drain-to-Source Voltage(V)
18
20
CYStek Product Specification
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 4/8
CYStech Electronics Corp.
Typical Characteristics(Cont.)
Gate Threshold Voltage vs Ambient Temperature
Maximum Safe Operating Area
10
VGS(th) , Gate SourceThreshold Voltage-(V)
ID, Drain Current (A)
100
100μs
1ms
1
10ms
RDS(ON) Limited
100ms
0.1
DC
Ta=25°C, Single pulse,
VGS=10V, Tj=150°C
1
ID=250μA
0.8
0.6
0.4
0.2
0.01
0.1
1
10
VDS, Drain-Source Voltage(V)
-60
100
20
60
100
140
Junction Temperature-Tj(°C)
180
Maximum Drain Current vs Junction Temperature
Gate Charge Characteristics
10
ID, Maximum Drain Current(A)
4.5
8
VGS, Gate-Source Voltage(V)
-20
VDS=10V
ID=3.6A
6
4
2
0
4
3.5
3
2.5
2
1.5
1
TA=25°C, VGS=10V
0.5
0
0
2
4
6
8
Qg, Total Gate Charge(nC)
10
25
50
75
100
125
Tj, Junction Temperature(°C)
150
175
Transient Thermal Response Curves
r(t), Normalized EffectiveTransient Thermal
Resistance
1
D=0.5
0.2
0.1
1.RθJA(t)=r(t)*RθJA
2.Duty Factor, D=t1/t2
3.TJM-TA=PDM*RθJA(t)
4.RθJA=90 °C/W
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
10
100
t1, Square Wave Pulse Duration(s)
MTN2302N3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 5/8
Recommended Soldering Footprint
MTN2302N3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 6/8
Reel Dimension
Carrier Tape Dimension
MTN2302N3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 7/8
Recommended wave soldering condition
Product
Pb-free devices
Peak Temperature
260 +0/-5 °C
Soldering Time
5 +1/-1 seconds
Recommended temperature profile for IR reflow
Profile feature
Average ramp-up rate
(Tsmax to Tp)
Preheat
−Temperature Min(TS min)
−Temperature Max(TS max)
−Time(ts min to ts max)
Time maintained above:
−Temperature (TL)
− Time (tL)
Peak Temperature(TP)
Time within 5°C of actual peak
temperature(tp)
Ramp down rate
Time 25 °C to peak temperature
Sn-Pb eutectic Assembly
Pb-free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
240 +0/-5 °C
217°C
60-150 seconds
260 +0/-5 °C
10-30 seconds
20-40 seconds
6°C/second max.
6 minutes max.
6°C/second max.
8 minutes max.
Note : All temperatures refer to topside of the package, measured on the package body surface.
MTN2302N3
CYStek Product Specification
CYStech Electronics Corp.
Spec. No. : C323N3
Issued Date : 2004.04.05
Revised Date :2012.06.26
Page No. : 8/8
SOT-23 Dimension
Marking:
TE
2302
3-Lead SOT-23 Plastic
Surface Mounted Package
CYStek Package Code: N3
Style: Pin 1.Gate 2.Source 3.Drain
*: Typical
Inches
Min.
Max.
0.1102 0.1204
0.0472 0.0669
0.0335 0.0512
0.0118 0.0197
0.0669 0.0910
0.0000 0.0040
DIM
A
B
C
D
G
H
Millimeters
Min.
Max.
2.80
3.04
1.20
1.70
0.89
1.30
0.30
0.50
1.70
2.30
0.00
0.10
DIM
J
K
L
S
V
L1
Inches
Min.
Max.
0.0032
0.0079
0.0118
0.0266
0.0335
0.0453
0.0830
0.1161
0.0098
0.0256
0.0118
0.0197
Millimeters
Min.
Max.
0.08
0.20
0.30
0.67
0.85
1.15
2.10
2.95
0.25
0.65
0.30
0.50
Notes: 1.Controlling dimension: millimeters.
2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.
3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.
Material:
• Lead: Pure tin plated.
• Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0.
Important Notice:
• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
• CYStek reserves the right to make changes to its products without notice.
• CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
• CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
MTN2302N3
CYStek Product Specification