CYStech Electronics Corp. Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 1/13 Adjustable shunt regulator TL432KA3/N3/M3 Description Features TheTL432K is a three terminal adjustable shunt regulator with thermal stability guaranteed over temperature. The output voltage can be adjusted to any value from 1.24V(VREF) to 16V with two external resistors. The TL432 has a typical dynamic output impedance of 0.05Ω. Active output circuitry provides a very sharp turn on characteristic, making TL432 an excellent replacement for zener diodes. The TL432 shunt regulator is available with two voltage tolerances(0.5%, and 1% ), and three package options(TO-92, SOT-23 and SOT-89). This allows the designer the opportunity to select the optimum combination of cost and performance for their application. ◆Low voltage operation(down to 1.24V) ◆Fast turn on response ◆Low dynamic output impedance 0.05Ω typ. ◆Trimmed bandgap design : ±0.5% ◆Operating current range : 80μA ~100mA ◆Available in TO-92, SOT-23, and SOT-89 packages Applications ◆Linear Regulators ◆Adjustable Supplies ◆Switching Power Supplies ◆Battery Operated Computers ◆Instrumentation ◆Computer Disk Drives Typical Application Circuit(Note 1,2) Notes: TL432 TL432KA3/N3/M3 1) Set VOUT according to the following equation: VOUT=VREF(1+R1/R2)+IREFR1 2) Choose the value for R as follows: ˙The maximum limit for R should be such that the cathode current, Iz, is greater than the minimum operating current(80μA) at VIN(MIN). ˙The minimum limit for R should be as such that Iz does not exceed 100mA under all load conditions, and the instantaneous turn-on value for Iz does not exceed 150mA. Both of the following conditions must be met: Rmin≥VIN(max)/150mA(to limit instantaneous turn-on Iz) Rmin≥ VIN(max)-VOUT (to limit Iz under IOUT(min)+100mA normal operating conditions) CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 2/13 CYStech Electronics Corp. Absolute Maximum Ratings Parameter Cathode Voltage Continuous Cathode Current Reference Input Current Power Dissipation at TA=25℃ SOT-23 SOT-89 TO-92 Thermal Resistance SOT-23 SOT-89 TO-92 ESD susceptibility(HBM) (Note) Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Symbol Vz IZ IREF Maximum 20 100 3 Units V mA mA 0.18 0.4 0.5 PD W 556 250 200 2000 -40 to +85 -40 to +125 -65 to +150 RθJA VESD TA TJ Tstg ℃/W V ℃ ℃ ℃ Note : Human body model, 1.5kΩ in series with 100pF Electrical Characteristics (At 25℃ free air ambient temperature, unless otherwise noted.) TL432 A-rank(±0.5%) TL432 B-rank(±1%) Parameter Symbol Condition Reference Voltage VREF VZ=VREF,IZ=10mA (Note 1) VREF Temperature Deviation VDEV VZ=VREF, IZ=10mA,TA=-40~ 85°C (Note 1) Ratio of Change in ΔVREF IZ=10mA, ΔVZ=16V to VREF VREF to change in VZ ΔVZ Reference Input IREF R1=10kΩ,R2=∞, IZ=10mA Current (Note2) IREF Temperature IREF(DEV) R1=10kΩ,R2=∞, IZ=10mA Deviation (Note 2) Off-state Cathode IZ(OFF) VREF=0V,VZ=16V (Note 3) Current Dynamic Output Impedance f <1kHz,VZ=VREF rz IZ=1mA to 100mA (Note 1) Minimum Operating Current IZ(MIN) VZ=VREF (Note 1) Min Typ 1.234 1.240 Max Min 1.246 1.228 Typ Max Unit 1.240 1.252 V - 10 25 - 10 25 mV - -1 -2.7 - -1 -2.7 mV/V - 0.15 0.5 - 0.15 0.5 μA - 0.1 0.4 - 0.1 0.4 μA - 0.14 0.5 - 0.14 0.5 μA - 0.05 0.2 - 0.05 0.2 Ω - 20 80 - 20 80 μA Notes: (1) See Test Circuit 1. (2) See Test Circuit 2. (3) See Test Circuit 3. TL432KA3/N3/M3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 3/13 Test Circuits TL432KA3/N3/M3 CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 4/13 CYStech Electronics Corp. Block Diagram Symbol Cathode Cathode REF REF VREF Anode Anode Ordering Information Device TL432KA3-A-TB-G TL432KA3-B-TB-G TL432KA3-A-BK-G TL432KA3-B-BK-G Package TO-92 (Pb-free lead plating and halogen-free package) Rank A B A B Tolerance ±0.5% ±1% ±0.5% ±1% TL432KN3-A-T1-G SOT-23 (Pb-free lead plating and halogen-free package) A ±0.5% B ±1% A ±0.5% B ±1% TL432KN3-B-T1-G TL432KM3-A-T2-G TL432KM3-B-T2-G SOT-89 (Pb-free lead plating and halogen-free package) Shipping 2000 pcs / Tape & Box 1000 pcs/ bag, 10 bags/box, 10boxes/carton 3000 pcs / Tape & Reel 1000 pcs / Tape & Reel Environment friendly grade : S for RoHS compliant products, G for RoHS compliant and green compound products Packing spec, TB :2000 pcs/tape & box; BK: 1000 pcs / bag, 10 bags/box, 10 boxes/carton T1 : 3000 pcs / tape & reel, 7” reel ; T2 :1000 pcs/tape & reel, 7” reel Product rank, zero for no rank products Product name TL432KA3/N3/M3 CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 5/13 CYStech Electronics Corp. Typical Characteristics C ATHODE C UR R ENT vs C ATHODE VOLTAGE 150 200 125 150 I K - COTHODE CURRENT(μA) I K - COTHODE CURRENT (mA) C ATHODE C UR R ENT vs C ATHODE VOLTAGE 100 75 50 25 0 -25 -50 -75 -100 -2. 0 100 50 0 - 50 - 100 - 150 - 200 -1. 0 0. 0 1. 0 2. 0 - 1. 0 - 0. 5 0.5 1. 0 1. 5 V AK - C ATHODE VOLTAGE (V) V A K - C ATHODE VOLTAGE (V) R EF ER ENCE INP UT C UR R ENT vs AMB IENT TEMP ER ATUR E R EF ER ENC E INP UT VOLTAGE vs AMB IENT TEMP ER ATUR E 1. 300 40 IKA=10mA 35 1. 280 Iref - REFERENCE INPUT CURRENT ( nA) Vref - REFERENCE INPUT VOLTAGE (mV) 0.0 1. 260 1. 240 1. 220 IKA =10mA 30 25 20 15 10 5 1. 200 0 -50 -25 0 25 50 75 100 125 - 50 - 25 AMB IENT TEMP ER ATUR E(℃ ) C ATHODE VOLTAGE vs R EF ER ENC E INP UT VOLTAGE 25 50 75 100 125 DYNAMIC IMP EDANC E vs F R EQUENC E 100 Z KA - DYNAMIC IMPEDANCE (Ω) 2 ΔVref - REFERENCE INPUT VOLTAGE (mV) 0 AMB IENT TEMP ER ATUR E(℃ ) 0 -2 -4 -6 IKA=10mA 10 1 0. 1 0. 01 -8 0 5 10 15 V KA - C ATHODE VOLTAGE (V) TL432KA3/N3/M3 20 1 10 100 1000 f - F R EQUENC Y (KHz ) CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 6/13 CYStech Electronics Corp. Typical Characteristics (Cont.) Stability Boundary Conditions OP EN-LOOP VOLTAGE GAIN vs F R EQUENC Y 0.6 K (mA) 30 VKA?2.5V, no oscillation 0.5 0.4 Cathode Current---I OPEN-LOOP VOLTAGE GAIN (dB) 40 20 10 0 1 0.3 10 100 f - F REQUENCY (KHz ) Stability Region VKA=VREF 0.2 0.1 IKA=10mA Stability Region TA=25°C 0 0.001 0.01 0.1 1 Lo ad C ap acitan ce- -- C L ( μ F) 10 Power Derating Curves 0.6 T O-92 Power Dissipation---PD(W) 0.5 0.4 SOT -89 0.3 SOT -23 0.2 0.1 0 0 50 100 150 Am b ien t Tem p er atu r e-- -TA(℃) TL432KA3/N3/M3 200 CYStek Product Specification CYStech Electronics Corp. Test Circuit-Small-Signal Gain and Phase Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 7/13 Test Circuit-Stability OUT Iz 15k PL432 TL432 + 10£gF 232 8.25k GND Applications Information - Stability Selection of load capacitance when using TL432K as a shunt regulator When the TL432K is used as a shunt regulator, two options for selection of CL(see diagram on page 6) are recommended for optimal stability: 1) No load capacitance across the device, decouple at the load. 2) Large capacitance across the device, optimal decoupling at the load. The reason for this is that TL432K exhibits instability with capacitances in the range of 47nF to 1μF (approx.) at light cathode currents(up to 0.5mA typical). The device is less stable the lower the cathode voltage has been set for. Therefore while the device will be perfectly stable operating at a cathode current of (say) 10mA with a 0.1μF capacitor across it, it will oscillate transiently during start-up as the cathode current passes through the instability region. Selecting a very low (or preferably, no) capacitance, or alternatively a high capacitance(such as 10μF) will avoid this issue altogether. Since the user will probably wish to have local decoupling at the load anyway, the most cost effective method is to use no capacitance at all directly across the device. PCB trace/via resistance and inductance prevent the local load decoupling from causing the oscillation during the transient start-up phase. Note : if the TL432K is located right at the load, so the load decoupling capacitor is directly across it, then this capacitor will have to be ≤1nF or ≥10μF. TL432KA3/N3/M3 CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 8/13 CYStech Electronics Corp. TO-92 Taping Outline H2 H2A H2A H2 D2 A H3 H4 H L L1 H1 W1 W D1 F1F2 T2 T T1 DIM A D D1 D2 F1,F2 F1,F2 H H1 H2 H2A H3 H4 L L1 P P1 P2 T T1 T2 W W1 - TL432KA3/N3/M3 D P1 P P2 Item Component body height Tape Feed Diameter Lead Diameter Component Body Diameter Component Lead Pitch F1-F2 Height Of Seating Plane Feed Hole Location Front To Rear Deflection Deflection Left Or Right Component Height Feed Hole To Bottom Of Component Lead Length After Component Removal Lead Wire Enclosure Feed Hole Pitch Center Of Seating Plane Location 4 Feed Hole Pitch Over All Tape Thickness Total Taped Package Thickness Carrier Tape Thickness Tape Width Adhesive Tape Width 20 pcs Pitch Millimeters Min. 4.33 3.80 0.36 4.33 2.40 15.50 8.50 2.50 12.50 5.95 50.30 0.36 17.50 5.00 253 Max. 4.83 4.20 0.53 4.83 2.90 ±0.3 16.50 9.50 1 1 27 21 11 12.90 6.75 51.30 0.55 1.42 0.68 19.00 7.00 255 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 9/13 SOT-23 Reel Dimension SOT-23 Carrier Tape Dimension TL432KA3/N3/M3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 10/13 SOT-89 Reel Dimension SOT-89 Carrier Tape Dimension TL432KA3/N3/M3 CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 11/13 CYStech Electronics Corp. TO-92 Dimension Marking: α2 A B 1 2 3 Date Code TL 432K □□ α3 C D H I G α1 Style: Pin 1.Reference 2.Anode 3.Cathode E F 3-Lead TO-92 Plastic Package CYStek Package Code: A3 Date Code : Year Code (left character)+ Month Code (right character) Year Code : The last digit of Chriatian year Month Code : 1→Jan, 2→Feb, …, 9→Sep, A→Oct, B→Nov, C→Dec *: Typical Inches Min. Max. 0.1704 0.1902 0.1704 0.1902 0.5000 0.0142 0.0220 *0.0500 0.1323 0.1480 DIM A B C D E F Millimeters Min. Max. 4.33 4.83 4.33 4.83 12.70 0.36 0.56 *1.27 3.36 3.76 DIM G H I α1 α2 α3 Inches Min. Max. 0.0142 0.0220 *0.1000 *0.0500 *5° *2° *2° Millimeters Min. Max. 0.36 0.56 *2.54 *1.27 *5° *2° *2° Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: • Lead: Pure tin plated. • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. TL432KA3/N3/M3 CYStek Product Specification Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 12/13 CYStech Electronics Corp. SOT-23 Dimension Marking: 432K XX Date Code 3-Lead SOT-23 Plastic Surface Mounted Package CYStek Package Code: N3 Style: Pin 1.Reference 3.Anode 2.Cathode Date Code : Year Code (bottom character)+ Month Code (top character) Year Code : The last digit of Chriatian year. Month Code : 1→Jan, 2→Feb, …, 9→Sep, A→Oct, B→Nov, C→Dec *: Typical Inches Min. Max. 0.1102 0.1204 0.0472 0.0669 0.0335 0.0512 0.0118 0.0197 0.0669 0.0910 0.0000 0.0040 DIM A B C D G H Millimeters Min. Max. 2.80 3.04 1.20 1.70 0.89 1.30 0.30 0.50 1.70 2.30 0.00 0.10 DIM J K L S V L1 Inches Min. Max. 0.0032 0.0079 0.0118 0.0266 0.0335 0.0453 0.0830 0.1161 0.0098 0.0256 0.0118 0.0197 Millimeters Min. Max. 0.08 0.20 0.30 0.67 0.85 1.15 2.10 2.95 0.25 0.65 0.30 0.50 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYCtek sales office. Material: • Lead: Pure tin plated. • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. TL432KA3/N3/M3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C112A3 Issued Date : 2015.09.10 Revised Date : Page No. : 13/13 SOT-89 Dimension A 2 1 month code: 1~9, A,B,C Marking: 3 Product Name H C Year code: 0→2010, 1→2011, 2→2012, …etc. D B E Style: Pin 1. Reference 2. Anode I F 3. Cathode G 3-Lead SOT-89 Plastic Surface Mounted Package CYStek Package Code: M3 *: Typical Inches Min. Max. 0.1732 0.1811 0.1594 0.1673 0.0591 0.0663 0.0945 0.1024 0.01417 0.0201 DIM A B C D E Millimeters Min. Max. 4.40 4.60 4.05 4.25 1.50 1.70 2.40 2.60 0.36 0.51 DIM F G H I Inches Min. Max. 0.0583 0.0598 0.1165 0.1197 0.0551 0.0630 0.0138 0.0161 Millimeters Min. Max. 1.48 1.527 2.96 3.04 1.40 1.60 0.35 0.41 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: • Lead: Pure tin plated. • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. TL432KA3/N3/M3 CYStek Product Specification