A63L83361 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Document Title 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flowthrough Data Output Revision History History Issue Date Remark 0.0 Initial issue July 14, 2005 Preliminary 1.0 Final version release April 27, 2007 Final Rev. No. (April, 2007, Version 1.0) AMIC Technology, Corp. A63L83361 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output Features Selectable BURST mode SLEEP mode (ZZ pin) provided Available in 100-pin LQFP package Industrial operating temperature range: -25°C to +85°C for -I series All Pb-free (lead-free) product are RoHS compliant Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz) Single 3.3V±5% power supply Synchronous burst function Individual Byte Write control and Global Write Three separate chip enables allow wide range of options for CE control, address pipelining General Description Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L83361 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK). This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written. The A63L83361 is a high-speed SRAM containing 9M bits of bit synchronous memory, organized as 256K words by 36 bits. The A63L83361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 256K X 36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 A17), all data inputs (I/O1 - I/O36 ), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). (April, 2007, Version 1.0) 1 AMIC Technology, Corp. A63L83361 ADSP 84 A9 ADSC 85 81 OE 86 ADV BWE 87 A8 GW 88 82 CLK 89 83 GND 90 BW1 93 CE2 BW2 94 VCC BW3 95 91 BW4 96 92 CE CE2 97 A7 99 98 A6 100 Pin Configuration I/O19 1 80 I/O18 I/O20 2 79 I/O17 I/O21 3 78 I/O16 VCCQ 4 77 VCCQ GNDQ 5 76 GNDQ I/O22 6 75 I/O15 I/O23 7 74 I/O14 I/O24 8 73 I/O13 I/O25 9 72 I/O12 GNDQ 10 71 GNDQ VCCQ 11 70 VCCQ I/O26 12 69 I/O11 I/O27 13 68 I/O10 NC 14 67 GND VCC 15 66 NC NC 16 65 VCC GND 17 64 ZZ I/O28 18 63 I/O8 I/O29 19 62 I/O7 VCCQ 20 61 VCCQ GNDQ 21 60 GNDQ I/O30 22 59 I/O6 I/O31 23 58 I/O5 I/O32 24 57 I/O4 I/O33 25 56 I/O3 GNDQ 26 55 GNDQ VCCQ 27 54 VCCQ I/O34 28 53 I/O2 I/O35 29 52 I/O1 I/O36 30 51 I/O9 (April, 2007, Version 1.0) 45 46 47 48 49 50 A13 A14 A15 A16 A17 40 GND A12 39 NC 44 38 NC A11 37 A0 43 36 A1 A10 35 A2 42 34 A3 41 33 A4 NC 32 A5 VCC 31 MODE A63L83361E 2 AMIC Technology, Corp. A63L83361 Block Diagram ZZ MODE LOGIC MODE ADV CLK CLK LOGIC BURST LOGIC ADDRESS COUNTER CLR ADSC ADSP A0-A17 ADDRESS REGISTERS 18 9 9 GW BWE BW1 BW2 BYTE WRITE ENABLE LOGIC BW3 9 9 BW4 BYTE1 WRITE DRIVER 9 BYTE2 WRITE DRIVER 9 256KX9X4 36 OUTPUT MEMORY BYTE3 WRITE DRIVER 9 BYTE4 WRITE DRIVER 9 BUFFER ARRAY 36 4 DATA-IN REGISTERS 4 CE CE2 CE2 CHIP ENABLE LOGIC OUTPUT ENABLE LOGIC OE I/O1 - I/O36 (April, 2007, Version 1.0) 3 AMIC Technology, Corp. A63L83361 Pin Description Pin No. Symbol 32 – 37 , 43 - 50, 81, 82, 99, 100 A0 - A17 89 CLK 87, 93 - 96 BWE , BW1 - BW4 88 GW Global Write 86 OE Output Enable 92, 97, 98 CE2 ,CE2, CE Chip Enables 83 ADV 84 ADSP Processor Address Status 85 ADSC Controller Address Status 31 MODE Burst Mode: HIGH or NC (Interleaved burst) LOW (Linear burst) 64 ZZ 1, 2, 3, 6 - 9, 12, 13, 18, 19, 22 - 25, 28, 29,30,51, 52, 53, 56 - 59, 62, 63, 68, 69, 72 - 75, 78, 79,80 I/O1- I/O36 14, 16, 38, 39, 42, 66 NC No Connection 15, 41, 65, 91 VCC Power Supply 17, 40, 67, 90 GND Ground 4, 11, 20, 27, 54, 61, 70, 77 VCCQ Isolated Output Buffer Supply 5, 10, 21, 26, 55, 60, 71, 76 GNDQ Isolated Output Buffer Ground (April, 2007, Version 1.0) Description Address Inputs Clock Byte Write Enables Burst Address Advance Asynchronous Power-Down (Snooze): HIGH (Sleep) LOW or NC (Wake up) Data Inputs/Outputs 4 AMIC Technology, Corp. A63L83361 Synchronous Truth Table (See Notes 1 Through 5) Operation Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used NONE CE CE2 CE2 ADSP ADSC ADV WRITE OE H X X X L X X X L-H I/O Operation High-Z NONE L X L L X X X X L-H High-Z NONE L H X L X X X X L-H High-Z NONE L X L H L X X X L-H High-Z NONE L H X H L X X X L-H High-Z External L L H L X X X L L-H Dout External L L H L X X X H L-H High-Z External L L H H L X L X L-H Din External L L H H L X H L L-H Dout External L L H H L X H H L-H High-Z Next X X X H H L H L L-H Dout Next X X X H H L H H L-H High-Z Next H X X X H L H L L-H Dout Next H X X X H L H H L-H High-Z Next X X X H H L L X L-H Din Next H X X X H L L X L-H Din Current X X X H H H H L L-H Dout Current X X X H H H H H L-H High-Z Current H X X X H H H L L-H Dout Current H X X X H H H H L-H High-Z Current X X X H H H L X L-H Din Current H X X X H H L X L-H Din (April, 2007, Version 1.0) 5 CLK AMIC Technology, Corp. A63L83361 Notes: 1. X = "Disregard", H = Logic High, L = Logic Low. 2. WRITE = L means: 1) Any BWx ( BW1, BW2 , BW3 , or BW4 ) and BWE are low or 2) GW is low. 3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK. 4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to the Write timing diagram for clarification. Write Truth Table Operation GW BWE BW1 BW2 BW3 BW4 READ H H X X X X READ H L H H H H WRITE Byte 1 H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X (April, 2007, Version 1.0) 6 AMIC Technology, Corp. A63L83361 Linear Burst Address Table (MODE = LOW) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 Absolute Maximum Ratings* VCC & VCCQ Supply Voltages VCC for all devices . . ….. . . . . . . . . . . . . . . . . . . . +3.3V VCCQ for all devices . . ….. . . . . . . . . . . . . . . . . . . +3.3V Operating ranges define those limits between which the functionally of the device is guaranteed. Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature (Tbias) . . . . . . . . . . -65°C to 150 °C Storage Temperature (Tstg) . . . . . . . . . . . -55°C to 125°C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Operating Ranges Ambient Temperature Commercial (C) Devices . . . . . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices . . . . . . . . . . . . . . . . -25°C to +85°C Recommended DC Operating Conditions (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage (Operating Voltage Range) 3.135 3.3 3.465 V VCCQ Isolated Input Buffer Supply 3.135 3.3 3.465 V GND Supply Voltage to GND 0.0 - 0.0 V VIH Input High Voltage 2 - VCC+0.3 V VIHQ Input High Voltage (I/O Pins) 2 - VCC+0.3 V VIL Input Low Voltage -0.3 - 0.8 V (April, 2007, Version 1.0) 7 Note 1, 2 1, 2 AMIC Technology, Corp. A63L83361 DC Electrical Characteristics (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC, VCCQ = 3.3V+5% or 3.3V-5%, unless otherwise noted) Symbol Parameter Min. Max. Unit Test Conditions Note ⏐ILI⏐ Input Leakage Current - ±2.0 μA All inputs VIN = GND to VCC ⏐ILO⏐ Output Leakage Current - ±2.0 μA OE = VIH, Vout = GND to VCC Supply Current - 300 mA Device selected; VCC = max. Iout = 0mA, all inputs = VIH or VIL Cycle time = tKC min. 3, 11 11 ICC1 ISB1 Standby Current ISB2 - 30 mA Device deselected; VCC = max. All inputs are fixed. All inputs ≥ VCC - 0.2V or ≤ GND + 0.2V Cycle time = tKC min. - 15 mA ZZ ≥ VCC - 0.2V VOL Output Low Voltage - 1.0 V IOL = 8 mA VOH Output High Voltage 1.6 - V IOH = -4 mA Capacitance Symbol Parameter Typ. Max. Unit CIN Input Capacitance 3 4 pF CI/O Input/Output Capacitance 4 5 pF Conditions TA = 25 C; f = 1MHz VCC = 3.3V * These parameters are sampled and not 100% tested. (April, 2007, Version 1.0) 8 AMIC Technology, Corp. A63L83361 AC Characteristics (0°C ≤ TA ≤ 70°C, -25°C ≤ TA ≤ 85°C, VCC = 3.3V+5% or 3.3V-5%) Symbol -6.5 Parameter -7.5 -8.5 Unit Min. Max. Min. Max. Min. Max. Note TKC Clock Cycle Time 7.5 - 8.5 - 10 - ns TKH Clock High Time 2.5 - 2.8 - 3.0 - ns TKL Clock Low Time 2.5 - 2.8 - 3.0 - ns TKQ Clock to Output Valid - 6.5 - 7.5 - 8.5 ns tKQX Clock to Output Invalid 3.0 - 3.0 - 3.0 - ns tKQLZ Clock to Output in Low-Z 2.5 - 2.5 - 2.5 - ns 5, 6 tKQHZ Clock to Output in High-Z - 3.5 - 3.5 - 5.0 ns 5, 6 tOEQ OE to Output Valid - 3.5 - 3.5 - 5.0 ns 8 tOELZ OE to Output in Low-Z 0 - 0 - 0 - ns 5, 6 tOEHZ OE to Output in High-Z - 3.5 - 3.5 - 5.0 ns 5, 6 Setup Times TAS Address 1.5 - 2.0 - 2.0 - ns 7, 9 tADSS Address Status ( ADSC , ADSP ) 1.5 - 2.0 - 2.0 - ns 7, 9 tADVS Address Advance ( ADV ) 1.5 - 2.0 - 2.0 - ns 7, 9 Write Signals 1.5 - 2.0 - 2.0 - ns 7, 9 tWS ( BW1, BW2 , BW3 , BW4 , BWE , GW ) TDS Data-in 1.5 - 1.5 - 2.0 - ns 7, 9 tCES Chip Enable ( CE , CE2, CE2 ) 1.5 - 2.0 - 2.0 - ns 7, 9 Hold Times TAH Address 0.5 0.5 0.5 ns 7, 9 tADSH Address Status ( ADSC , ADSP ) 0.5 0.5 0.5 ns 7, 9 tAAH Address Advance ( ADV ) 0.5 0.5 0.5 ns 7, 9 tWH Write Signal 0.5 0.5 0.5 ns 7, 9 ( BW1, BW2 , BW3 , BW4 , BWE , GW ) TDH Data-in 0.5 0.5 0.5 ns 7, 9 tCEH Chip Enable ( CE , CE2, CE2 ) 0.5 0.5 0.5 ns 7, 9 (April, 2007, Version 1.0) 9 AMIC Technology, Corp. A63L83361 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. All voltages refer to GND. Overshoot: VIH ≤ +2V for t ≤ tKC/2. Undershoot: VIL ≥ -0.7V for t ≤ tKC/2. Power-up: VIH ≤ +2 and VCC ≤ 1.7V for t ≤ 200ms ICC1 is given with no output current. ICC1 increases with greater output loading and faster cycle times. Test conditions assume the output loading shown in Figure 1, unless otherwise specified. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the required setup and hold times. OE has no effect when a Byte Write enable is sampled LOW. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values. AC I/O curves are available upon request. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means device is active (not in POWER-DOWN mode). MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage current of 10μA. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to emerge from SLEEP mode to ensure no data is lost. (April, 2007, Version 1.0) 10 AMIC Technology, Corp. A63L83361 Timing Waveforms tKC CLK tKH tKL tADSS tADSH ADSP tADSS Deselect cycle tADSH ADSC tAS tAH A1 ADDRESS A2 tWS A3 tWH GW,BWE BW1-BW4 tCES Deselect with CE tCEH CE (NOTE 2) tADVS tADVH ADV ADV suspends burst (NOTE 3) OE tOEQ tOELZ tOEHZ tKQLZ DOUT High-Z Q(A1) tKQ tKQ tKQHZ tKQX Q(A2) tKQX Q(A2+1) Q(A2+2) Q(A2+3) Q(A3) (NOTE *1) Single READ BURST READ Don't Care Undefined Read Timing Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. 2. CE and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not cause Q to be driven until after the following clock rising edge. (April, 2007, Version 1.0) 11 AMIC Technology, Corp. A63L83361 Timing Waveforms (continued) tKC CLK tKH tKL tADSS tADSH ADSP tADSS ADSC extends burst tADSS tADSH tADSH ADSC tAS tAH A1 ADDRESS A2 A3 BYTE W RITE signals are ignored for first cycle when ADSP initiates burst tWS tWH BW E,BW 1-BW 4 (NOTE 5) tWS tWH GW tCES tCEH CE (NOTE 2) tADVS tADVH ADV (NOTE 4) OE (NOTE 3) tDS DIN ADV suspends burst High-Z tDH D(A1) tOEHZ D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) (NOTE 1) DOUT BURST READ Single W RITE Extended BURST W RITE Don't Care Undefined Write Timing Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately following A2. 2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents input/output data contention for the period prior to the time Byte Write enable inputs are sampled. 4. ADV must be HIGH to permit a Write to the loaded address. 5. Byte Write enables are decided by means of a Write truth table. (April, 2007, Version 1.0) 12 AMIC Technology, Corp. A63L83361 Timing Waveforms (continued) tKC CLK tKH tKL tADSS tADSH ADSP ADSC tAS tAH ADDRESS A2 A1 A4 A3 tWS tWH tDS tDH A5 A6 GW,BWE, BW1-BW4 (NOTE 3) tCES tCEH CE (NOTE 2) ADV OE tKQ DIN High-Z tOELZ D(A3) D(A5) D(A6) tOEHZ tKQ DOUT Q(A1) Q(A2) Back-to-Back READs Q(A4) Single WRITE (NOTE 1) Q(A4+1) Q(A4+2) BURST READ Q(A4+3) Back-to-Back WRITEs Don't Care Undefined Read/Write Timing Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4. 2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE is LOW and CE2 is HIGH, When CE is HIGH, CE2 is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC , or ADV cycle is performed. 4. Byte Write enables are decided by means of a Write truth table. 5. Back-to-back READs may be controlled by either ADSP or ADSC (April, 2007, Version 1.0) 13 AMIC Technology, Corp. A63L83361 AC Test Conditions Input Pulse Levels GND to 3V Input Rise and Fall Times 1 ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figures 1 and 2 +3.3V Q ZO=50Ω 320Ω RL=50Ω Q VT=1.5V 350Ω 5pF Figure 1. Output Load Equivalent Figure 2. Output Load Equivalent Ordering Information Part No. Access Times (ns) Frequency (MHz) Package A63L83361E-6.5IF 6.5 153 100L Pb-Free LQFP A63L83361E-6.5F 6.5 153 100L Pb-Free LQFP A63L83361E-7.5IF 7.5 133 100L Pb-Free LQFP A63L83361E-7.5F 7.5 133 100L Pb-Free LQFP A63L83361E-8IF 8 117 100L Pb-Free LQFP A63L83361E-8F 8 117 100L Pb-Free LQFP Note: -I is for industrial operating temperature range -25ºC to +85ºC. (April, 2007, Version 1.0) 14 AMIC Technology, Corp. A63L83361 Package Information LQFP 100L Outline Dimensions unit: inches/mm HE A2 A1 y D E 80 51 50 100 31 1 L1 L HD D 81 30 e b c θ Symbol A1 Dimensions in inches Dimensions in mm Min. Nom. Max. Min. Nom. Max. 0.002 - - 0.05 - - A2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.011 0.013 0.015 0.27 0.32 0.37 c 0.005 - 0.008 0.12 - 0.20 HE 0.860 0.866 0.872 21.85 22.00 22.15 E 0.783 0.787 0.791 19.90 20.00 20.10 HD 0.624 0.630 0.636 15.85 16.00 16.15 D 0.547 0.551 0.555 13.90 14.00 14.10 e L 0.026 BSC 0.018 L1 0.024 0.65 BSC 0.030 0.45 0.039 REF 0.60 0.75 1.00 REF y - - 0.004 - - 0.1 θ 0° 3.5° 7° 0° 3.5° 7° Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. (April, 2007, Version 1.0) 15 AMIC Technology, Corp.