298A CY7C1298A/ GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Features • • • • • • • • • • • • • • • • • • • The CY7C1298A/GVT7164C18 SRAM integrates 65536x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), burst control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Fast access times: 5, 6, 7, and 8 ns Fast clock speed: 100, 83, 66, and 50 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 5 and 6 ns Optimal for performance (two cycle chip deselect, depth expansion without wait state) Single +3.3V –5 to +10% power supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, control, input, and output pipeline registers Internally self-timed Write Cycle Write pass-through capability Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages Low capacitive bus loading High 30-pF output drive capability at rated access time Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and DQP2. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. This device also incorporates Write pass-through capability and pipelined enable circuit for better system performance. The CY7C1298A/GVT7164C18 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, Pentium®, 680x0, and PowerPC™ systems and for systems that are benefited from a wide synchronous data bus. Functional Description The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced double-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 7C1298A-100 7164C18-5 7C1298A-83 7164C18-6 7C1298A-66 7164C18-7 7C1298A-50 7164C18-8 5 6 7 8 360 315 270 225 2 2 2 2 Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of International Business Machines, Inc. Cypress Semiconductor Corporation Document #: 38-05194 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 19, 2003 CY7C1298A/ GVT7164C18 Functional Block Diagram—64K x 18[1] UPPER BYTE WRITE WEH# * BWE# D Q LOWER BYTE WRITE D Q CE# lo byte write * GW# ENABLE D * CE2 Q D Q hi byte write WEL# * CE2# ZZ Power Down Logic OE# ADSP# ADSC# CLR ADV# A1-A0 Binary Counter & Logic OUTPUT REGISTER D Q Output Buffers Address Register 64K x 9 x 2 SRAM Array A15-A2 Input Register DQ1DQ16, DQP1, DQP2 * MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05194 Rev. *A Page 2 of 12 CY7C1298A/ GVT7164C18 Pin Configuration 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 100-Pin TQFP Top View NC NC NC CY7C1298A/GVT7164C18 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 VCC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Descriptions QFP Pins Pin Name 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44 A0–A15 InputAddresses: These inputs are registered and must meet the set-up and hold Synchronous times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. 93, 94 WEL, WEH InputByte Write Enables: A byte write enable is LOW for a Write cycle and HIGH Synchronous for a Read cycle. WEL controls DQ1–DQ8 and DQP1. WEH controls DQ9–DQ16 and DQP2. Data I/O are high-impedance if either of these inputs are LOW, conditioned by BWE being LOW. 87 BWE InputWrite Enable: This active LOW input gates byte write operations and must Synchronous meet the set-up and hold times around the rising edge of CLK. 88 GW InputGlobal Write: This active LOW input allows a full 18-bit Write to occur indeSynchronous pendent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. 89 CLK InputClock: This signal registers the addresses, data, chip enables, write control Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. 98 CE InputChip Enable: This active LOW input is used to enable the device and to gate Synchronous ADSP. 92 CE2 InputChip Enable: This active LOW input is used to enable the device. Synchronous 97 CE2 InputChip Enable: This active HIGH input is used to enable the device. Synchronous Document #: 38-05194 Rev. *A Type Description Page 3 of 12 CY7C1298A/ GVT7164C18 Pin Descriptions (continued) QFP Pins Pin Name Type Description 86 OE Input Output Enable: This active LOW asynchronous input enables the data output drivers. 83 ADV InputAddress Advance: This active LOW input is used to control the internal burst Synchronous counter. A HIGH on this pin generates wait cycle (no address advance). 84 ADSP InputAddress Status Processor: This active LOW input, along with CE being Synchronous LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. 85 ADSC InputAddress Status Controller: This active LOW input causes device to be deSynchronous selected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs. 31 MODE InputStatic Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. 64 ZZ InputStatic Snooze: LOW or NC for normal operation. HIGH for low-power standby. Input/ Output Data Inputs/Outputs: Low Byte is DQ1–DQ8. HIgh Byte is DQ9–DQ16. Input data must meet set-up and hold times around the rising edge of CLK. Input/ Output Parity Inputs/Outputs: DQP1 is parity bit for DQ1–DQ8 and DQP2 is parity bit for DQ9–DQ16. 58, 59, 62, 63, 68, 69, DQ1–DQ16 72, 73, 8, 9, 12, 13, 18, 19, 22, 23 74, 24 DQP1, DQP2 14, 15, 41, 65, 91 VCC Supply Power Supply: +3.3V –5% and +10%. 17, 40, 67, 90 VSS Ground Ground: GND. 4, 11, 20, 27, 54, 61, 70, 77 VCCQ I/O Supply Output Buffer Supply: +3.3V –5% and +10%. 5, 10, 21, 26, 55, 60, 71, 76 VSSQ I/O Ground Output Buffer Ground: GND. 1–3, 6, 7, 16, 25, 28–30, 38, 39, 42, 43, 49–53, 56, 57, 66, 75, 78–79, 95, 96 NC - No Connect: These signals are not internally connected. Burst Address Table (MODE = GND) Burst Address Table (MODE = NC/VCC) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) First Address (external) Second Address (internal) Third Address (internal) Fourth Address (internal) A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00 A...A11 A...A00 A...A01 A...A10 Partial Truth Table for Read/Write Function GW BWE WEH WEL READ H H X X READ H L H H WRITE one byte H L L H WRITE all bytes H L L L WRITE all bytes L X X X Document #: 38-05194 Rev. *A Page 4 of 12 CY7C1298A/ GVT7164C18 Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X X L X X X L-H High-Z Deselected Cycle, Power Down None L X L L X X X X L-H High-Z Deselected Cycle, Power Down None L H X L X X X X L-H High-Z Deselected Cycle, Power Down None L X L H L X X X L-H High-Z Deselected Cycle, Power Down None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D CE2 CE2 ADSP Pass-Through Truth Table Previous Cycle[9] Operation Present Cycle BWn [10, 11] Next Cycle Operation CE BWn OE Operation Initiate WRITE cycle, all bytes Address = A(n–1), data = D(n–1) All L Initiate READ cycle Register A(n), Q = D(n–1) L H L Read D(n) Initiate WRITE cycle, all bytes Address = A(n–1), data = D(n–1) All L[10, 11] No new cycle Q = D(n–1) H H L No carry-over from previous cycle Initiate WRITE cycle, all bytes Address = A(n–1), data = D(n–1) All L[10, 11] No new cycle Q = High-Z H H H No carry-over from previous cycle Initiate WRITE cycle, one byte Address = A(n–1), data = D(n–1) One L[10] No new cycle Q = D(n–1) for one byte H H L No carry-over from previous cycle Notes: 2. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. 3. WEL enables write to DQ1–DQ8 and DQP1. WEH enables write to DQ9–DQ16 and DQP2. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. 9. Previous cycle may be any cycle (non-burst, burst, or wait). 10. BWE is LOW for individual byte WRITE. 11. GW LOW yields the same result for all-byte WRITE operation. Document #: 38-05194 Rev. *A Page 5 of 12 CY7C1298A/ GVT7164C18 Maximum Ratings Power Dissipation.......................................................... 1.6W Short Circuit Output Current...................................... 100 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Range Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V VIN ...................................................................... –0.5V to 6V Range Storage Temperature (plastic) .......................–55°C to +150° Ambient Temperature[12] VCC[13,14] 0°C to +70°C 3.3V −5%/+10% Com’l Junction Temperature ..................................................+150° Electrical Characteristics Over the Operating Range Parameter Description Test Conditions [15, 16] Min. Max. Unit VIH Input High (Logic 1) Voltage 2.0 VCCQ + 0.3 V VIl Input Low (Logic 0) Voltage[15, 16] –0.3 0.8 V ILI Input Leakage Current 0V < VIN < VCC –2 2 µA ILO Output Leakage Current Output(s) disabled, 0V < VOUT < VCC –2 2 µA IOH = –4.0 mA 2.4 [17] [15, 18] VOH Output High Voltage VOL Output Low Voltage[15, 18] VCC Supply Voltage Parameter V IOL = 8.0 mA [15] 3.1 Description Conditions Typ. 100 MHz -5 0.4 V 3.6 V 83 MHz -6 66 MHz -7 50 MHz -8 Unit ICC Power Supply Current: Operating[19, 20, 21] Device selected; all inputs < VILor > VIH; cycle time > tKC min.; VCC = Max.; outputs open 180 360 315 270 225 mA ISB1 Power Supply Current: Idle[20, 21] Device selected; ADSC, ADSP, ADV, GW, BWE >VIH; all other inputs < VILor > VIH; VCC = Max.; cycle time > tKC min.; outputs open 30 60 55 50 45 mA ISB2 CMOS Standby[20, 21] Device deselected; VCC = Max.; all inputs < VSS + 0.2 or >VCC – 0.2; all inputs static; CLK frequency = 0 0.2 2 2 2 2 mA ISB3 TTL Standby[20, 21] Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 8 18 18 18 18 mA ISB4 Clock Running[20, 21] Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC min. 30 60 55 50 45 mA Capacitance[22] Parameter Description CI Input Capacitance CO Input/Output Capacitance (DQ) Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Typ. Max. Unit 3 4 pF 6 7 pF Notes: 12. TA is the case temperature. 13. Please refer to waveform (d) 14. Power Supply ramp-up should be monotonic. 15. All voltages referenced to VSS (GND). 16. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. Undershoot:VIL ≤ –2.0V for t ≤ tKC /2 17. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±30 µA. 18. AC I/O curves are available upon request. 19. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 20. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 21. Typical values are measured at 3.3V, 25°C, and20-ns cycle time. 22. This parameter is sampled. Document #: 38-05194 Rev. *A Page 6 of 12 CY7C1298A/ GVT7164C18 Thermal Resistance Description Test Conditions Symbol TQFP Typ. Unit ΘJA 20 °C/W ΘJC 1 °C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, 4-layer PCB Thermal Resistance (Junction to Case) AC Test Loads and Waveforms[23] +3.3v DQ Z0 = 50Ω 50Ω ALL INPUT PULSES 317Ω 3.0V 5 pF 0V 10% DQ 30 pF 351Ω t PU 90% 10% 90% (a) F or prope r R E S E T bring V c c dow n t o 0 V ≤ 1.5 ns ≤ 1.5 ns Vt = 1.5V = 20 0u s V c c ty p V c c m in (c) (b) (d) Capacitance Derating[23] Description Symbol Typ. ∆ KQ 0.016 t Clock to output valid Max. Unit ns / pF Switching Characteristics Over the Operating Range[25] 100 MHz -5 Parameter Description Min. Max. 83 MHz -6 Min. Max. 66 MHz -7 Min. Max. 50 MHz -8 Min. Max. Unit Clock tKC Clock Cycle Time 10 12 15 20 ns tKH Clock HIGH Time 4 4 5 6 ns tKL Clock LOW Time 4 4 5 6 ns Output Times tKQ Clock to Output Valid tKQX Clock to Output Invalid 2 2 2 2 ns tKQLZ Clock to Output in Low-Z[26, 27] 3 3 3 3 ns tKQHZ [26, 27] tOEQ 5 Clock to Output in High-Z OE to Output Valid [28] [26, 27] tOELZ OE to Output in Low-Z tOEHZ OE to Output in High-Z[26, 27] 6 7 8 ns 5 5 6 6 ns 5 5 5 6 ns 6 ns 0 0 4 0 5 0 6 ns Set-up Times tS Address, Controls, and Data In[29] 2.5 2.5 2.5 3 ns Address, Controls, and Data In[29] 0.5 0.5 0.5 0.5 ns Hold Times tH Notes: 23. Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200 ms. 24. Capacitance derating applies to capacitance different from the load capacitance shown in part (a) of AC Test Loads. 25. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted. 26. Output loading is specified with CL = 5 pF as in AC Test Loads. 27. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 28. OE is a “don’t care” when a byte write enable is sampled LOW. 29. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table. Document #: 38-05194 Rev. *A Page 7 of 12 CY7C1298A/ GVT7164C18 Timing Diagrams Read Timing[30] tKC tKL CLK tKH tS ADSP# tH ADSC# tS ADDRESS A1 A2 tH WEL#, WEH#, BWE#, GW# tS CE# tS ADV# tH OE# tKQ DQ tKQLZ tOELZ Q(A1) tOEQ tKQ Q(A2) Q(A2+1) SINGLE READ Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Notes: 30. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. Document #: 38-05194 Rev. *A Page 8 of 12 CY7C1298A/ GVT7164C18 Timing Diagrams (continued) Write Timing[30] CLK tS ADSP# tH ADSC# tS A1 ADDRESS A2 A3 tH WEL#, WEH#, BWE# GW# CE# tS ADV# tH OE# tKQX DQ Q tOEHZ D(A1) SINGLE WRITE Document #: 38-05194 Rev. *A D(A2) D(A2+1) D(A2+1) D(A2+2) BURST WRITE D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE Page 9 of 12 CY7C1298A/ GVT7164C18 Timing Diagrams (continued) Read/Write Timing[30] CLK tS ADSP# tH ADSC# tS A1 ADDRESS A2 A3 A4 A5 tH WEL#, WEH#, BWE#, GW# CE# ADV# OE# DQ Q(A1) Q(A2) D(A3) Single Reads Single Write Q(A3) Pass Through Q(A4) Q(A4+1) Burst Read Q(A4+2) D(A5) D(A5+1) Burst Write Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 100 CY7C1298A–100NC/ GVT7164C18Q-5 N100 100-Lead Plastic Quad Flatpack Commercial 83 CY7C1298A–83NC/ GVT7164C18Q-6 N100 100-Lead Plastic Quad Flatpack Commercial 66 CY7C1298A–66NC/ GVT7164C18Q-7 N100 100-Lead Plastic Quad Flatpack Commercial 50 CY7C1298A–50NC/ GVT7164C18Q-8 N100 100-Lead Plastic Quad Flatpack Commercial Document #: 38-05194 Rev. *A Page 10 of 12 7C1314A: 2/98 Revision: June 21, 2000 CY7C1298A/ GVT7164C18 Package Diagram 100-Lead Plastic Quad Flatpack N100 51-85052-A Document #: 38-05194 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1298A/ GVT7164C18 Revision History Document Title: CY7C1298A/GVT7164C18 64K x 18 Synchronous Burst RAM Pipelined Output Document Number: 38-05194 REV. ECN NO. Issue Date Orig. of Change ** 111323 02/22/02 CJM Converted from Galvantech format Change CY part number from CY7C1315A to CY7C1298A *A 123140 01/19/03 RBI Add power up requirments to operating conditions information. Document #: 38-05194 Rev. *A Description of Change Page 12 of 12