A67L9318/A67L8336 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue July 13, 2005 Preliminary (July, 2005, Version 0.0) AMIC Technology, Corp. A67L9318/A67L8336 Preliminary 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L9318, A67L8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous clock enable ( CEN ), byte write Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/ W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded. The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems. enables ( BW1, BW2 , BW3 , BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE ), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/ LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/ LD in High state. PRELIMINARY (July, 2005, Version 0.0) 2 AMIC Technology, Corp. A67L9318/A67L8336 Pin Configuration A18 A8 A9 83 82 81 A9 NC 84 A8 OE ADV/ LD 86 A17 CEN 87 NC OE ADV/ LD R/W 88 85 CEN CLK 89 R/W VSS 90 CLK VCC 91 VSS CE2 92 VCC BW1 93 CE2 BW2 94 BW1 NC 95 BW2 BW4 NC 96 BW3 CE2 CE2 97 CE CE 98 512K x 18 A7 A7 99 A6 A6 100 256K x 36 I/Oc8 NC 1 80 A10 I/Ob8 I/Oc0 NC 2 79 NC I/Ob7 I/Oc1 NC 3 78 NC I/Ob6 VCCQ VCCQ 4 77 VCCQ VCCQ VSSQ VSSQ 5 76 VSSQ VSSQ I/Oc2 NC 6 75 NC I/Ob5 I/Oc3 NC 7 74 I/Oa0 I/Ob4 I/Oc4 I/Ob8 8 73 I/Oa1 I/Ob3 I/Oc5 I/Ob7 9 72 I/Oa2 I/Ob2 VSSQ VSSQ 10 71 VSSQ VSSQ VCCQ VCCQ 11 70 VCCQ VCCQ I/Oc6 I/Ob6 12 69 I/Oa3 I/Ob1 I/Oc7 I/Ob5 13 68 I/Oa4 I/Ob0 VCC VCC 14 67 VSS VSS VCC VCC 15 66 VCC VCC VCC VCC 16 65 VCC VCC VSS VSS 17 64 ZZ ZZ I/Od0 I/Ob4 18 63 I/Oa5 I/Oa7 I/Od1 I/Ob3 19 62 I/Oa6 I/Oa6 VCCQ VCCQ 20 61 VCCQ VCCQ VSSQ VSSQ 21 60 VSSQ VSSQ I/Od2 I/Ob2 22 59 I/Oa7 I/Oa5 I/Od3 I/Ob1 23 58 I/Oa8 I/Oa4 I/Od4 I/Ob0 24 57 NC I/Oa3 I/Od5 NC 25 56 NC I/Oa2 VSSQ VSSQ 26 55 VSSQ VSSQ VCCQ VCCQ 27 54 VCCQ VCCQ I/Od6 NC 28 53 NC I/Oa1 I/Od7 NC 29 52 NC I/Oa0 I/Od8 NC 30 51 NC I/Oa8 34 35 36 37 38 39 40 41 42 44 45 46 47 48 49 50 A3 A2 A1 A0 NC NC VSS VCC NC NC A11 A12 A13 A14 A15 A16 A17 A3 A2 A1 A0 NC NC VSS VCC NC NC A10 A11 A12 A13 A14 A15 A16 PRELIMINARY (July, 2005, Version 0.0) 3 43 33 A4 A4 32 31 A5 MODE MODE A5 A67L9318E A67L8336E AMIC Technology, Corp. A67L9318/A67L8336 Block Diagram (256K X 36) ZZ MODE LOGIC MODE ADV/LD CLK LOGIC CEN CLK A0-A17 BURST LOGIC ADDRESS COUNTER CLR WRITE ADDRESS REGISTER ADDRESS REGISTERS 9 9 ADV/LD R/W BW1 BW2 BW3 BW4 WRITE REGISTRY & CONTROL LOGIC 9 9 WRITE ADDRESS REGISTER BYTEa WRITE DRIVER 9 BYTEb WRITE DRIVER 9 256K x 9 x 4 MEMORY BYTEc WRITE DRIVER 9 BYTEd WRITE DRIVER 9 SENSE AMPS ARRAY DATA-IN REGISTERS CE CHIP ENABLE LOGIC CE2 CE2 PIPELINED ENABLE LOGIC OUTPUT REGISTERS & OUTPUT BUFFERS I/Os DATA-IN REGISTERS OUTPUT ENABLE LOGIC OE PRELIMINARY (July, 2005, Version 0.0) 4 AMIC Technology, Corp. A67L9318/A67L8336 Block Diagram (512K X 18) ZZ MODE LOGIC MODE ADV/LD CLK LOGIC CEN CLK A0-A18 BURST LOGIC ADDRESS COUNTER CLR WRITE ADDRESS REGISTER ADDRESS REGISTERS 9 ADV/LD R/W BW1 WRITE REGISTRY & CONTROL LOGIC BW2 WRITE ADDRESS REGISTER BYTEa WRITE DRIVER 9 512K X 9 X 2 MEMORY 9 BYTEb WRITE DRIVER 9 SENSE AMPS ARRAY DATA-IN REGISTERS CE CHIP ENABLE LOGIC CE2 CE2 PIPELINED ENABLE LOGIC OUTPUT REGISTERS & OUTPUT BUFFERS I/OS DATA-IN REGISTERS OUTPUT ENABLE LOGIC OE PRELIMINARY (July, 2005, Version 0.0) 5 AMIC Technology, Corp. A67L9318/A67L8336 Pin Description Pin No. LQFP (X18) LQFP (X36) 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83 83 37 36 35, 34, 33, 32, 100, 99, 82, 81, 45, 46, 47, 48, 49, 50, 83 44 93 ( BW1) 94 ( BW2 ) Symbol Description A0 A1 A2 - A9 Synchronous Address Inputs : These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two lest significant bits (LSB) of the address field and set the internal burst counter if burst is desired. A11 - A17 A18 A10 93 ( BW1) 94 ( BW2 ) 95 ( BW3 ) 96 ( BW4 ) BW1 BW2 BW3 89 89 CLK 98 98 CE Synchronous Chip Enable : This active low input is used to enable the device. This input is sampled only when a new external address is loaded (ADV/ LD LOW). 92 92 CE2 Synchronous Chip Enable : This active low input is used to enable the device and is sampled only when a new external address is loaded (ADV/ LD LOW). This input can be used for memory depth expansion. 97 97 CE2 Synchronous Chip Enable : This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/ LD LOW). This input can be used for memory depth expansion. 86 86 OE Output Enable : This active low asynchronous input enables the data I/O output drivers. 85 85 ADV/ LD Synchronous Address Advance/Load : When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, R/ W is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. 87 87 CEN Synchronous Clock Enable : This active low input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. PRELIMINARY (July, 2005, Version 0.0) BW4 Synchronous Byte Write Enables : These active low inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address, BWs are associated with addresses and apply to subsequent data. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; BW4 controls I/Od pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock are rising edge. 6 AMIC Technology, Corp. A67L9318/A67L8336 Pin Description (continued) Pin No. Symbol Description LQFP (X18) LQFP (X36) 64 64 ZZ Snooze Enable : This active high asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. 88 88 R/ W Read/Write : This active input determines the cycle type when ADV/ LD is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. 74, 73, 72, 69, 68, 63, 62, 59, 58, 24, 23, 22, 19, 18 13, 12, 9, 8 51, 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79, 80 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 I/Oa SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins; Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must meet setup and hold times around CLK rising edge. 31 31 MODE Mode : This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42,43 51, 52, 53, 56, 57, 75, 78, 79, 95, 96 38,39,42,43 NC No Connect : These pins can be left floating or connected to GND to minimize thermal impedance. 15, 41, 65, 91 15, 41, 65, 91 VCC Power Supply : See DC Electrical Characteristics and Operating Conditions for range. 14, 16, 66 14, 16, 66 VCC These pins do not have to be connected directly to VCC as long as the input voltage is ≥ VIH. This input is not connected to VCC bus internally. 4, 11, 20, 27, 54, 61, 70, 77 4, 11, 20, 27, 54, 61, 70, 77 VCCQ 17, 40, 90 17, 40, 90 VSS 5,10,21,26, 55,60,71,76 5,10,21,26, 55,60,71,76 VSSQ PRELIMINARY (July, 2005, Version 0.0) I/Ob I/Oc I/Od Isolated Output Buffer Supply : See DC Electrical Characteristics and Operating Conditions for range. Ground : GND. Isolated Output Buffer Ground 7 AMIC Technology, Corp. A67L9318/A67L8336 Truth Table (Notes 5 - 7) Operation Address Used None CE CE2 CE2 ZZ ADV/ LD L R/ W BWx OE CEN CLK I/O Notes Deselected Cycle, H X X L X X X L L→H High-Z Power-down Deselected Cycle, None X H X L L X X X L L→H High-Z Power-down Deselected Cycle, None X X L L L X X X L L→H High-Z Power-down Continue Deselect None X X X L H X X X L L→H High-Z 1 Cycle READ Cycle External L L H L L H X L L L→H Q (Begin Burst) READ Cycle Next X X X L H X X L L L→H Q 1,7 (Continue Burst) NOP/Dummy READ External L L H L L H X H L L→H High-Z 2 (Begin Burst) Dummy READ Next X X X L H X X H L L→H High-Z 1,2,7 (Continue Burst) WRITE Cycle External L L H L L L L X L L→H D 3 (Begin Burst) WRITE Cycle Next X X X L H X L X L L→H D 1,3,7 (Continue Burst) NOP/WRITE Abort None L L H L L L H X L L→H High-Z 2,3 (Begin Burst) WRITE Abort Next X X X L H X H X L L→H High-Z 1,2,3,7 (Continue Burst) IGNORE Clock Edge Current X X X L X X X X H L→ H 4 (Stall) SLEEP Mode None X X X H X X X X X X High-Z Notes: 1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first. 2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE Abort means a WRITE command is given, but no operation is performed. 3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements. 4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle. 5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals ( BW1, BW2 , BW3 and BW4 ) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BW1enables WRITEs to Byte “a” (I/Oa pins); BW2 enables WRITEs to Byte “b” (I/Ob pins); BW3 enables WRITEs to Byte “c” (I/Oc pins); BW4 enables WRITEs to Byte “d” (I/Od pins). 7. The address counter is incremented for all Continue Burst cycles. PRELIMINARY (July, 2005, Version 0.0) 8 AMIC Technology, Corp. A67L9318/A67L8336 Partial Truth Table for READ/WRITE Commands (X18) Operation R/ W BW1 BW2 READ H X X WRITE Byte “a” L L H WRITE Byte “b” L H L WRITE all bytes L L L WRITE Abort/NOP L H H Note : Using and BYTE WRITE(s), any one or more bytes may be written. Partial Truth Table for READ/WRITE Commands (X36) Operation R/ W BW1 BW2 BW3 BW4 READ H X X X X WRITE Byte “a” L L H H H WRITE Byte “b” L H L H H WRITE Byte “c” L H H L H WRITE Byte “d” L H H H L WRITE all bytes L L L L L WRITE Abort/NOP L H H H H Note : Using R/ W and BYTE WRITE(s), any one or more bytes may be written. Linear Burst Address Table (MODE = LOW) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10 Interleaved Burst Address Table (MODE = HIGH or NC) First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal) X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00 PRELIMINARY (July, 2005, Version 0.0) 9 AMIC Technology, Corp. A67L9318/A67L8336 Absolute Maximum Ratings* *Comments Power Supply Voltage (VCC) . . . . . . . . . . -0.3V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Operating Temperature (Topr) . . . . . . . . . . . 0°C to 70°C Storage Temperature (Tbias) . . . . . . . . . . -10°C to 85 °C Storage Temperature (Tstg) . . . . . . . . . . -55°C to 125°C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics and Operating Conditions (0°C ≤ TA ≤ 70°C, VCC, VCCQ = +3.3V± 5% unless otherwise noted) Symbol Parameter Conditions Min. Max. Unit Note VIH Input High Voltage 1.7 VCC+0.3 V 1,2 VIL Input Low Voltage -0.3 0.8 V 1,2 ILI Input Leakage Current 0V ≤ VIH ≤ VCC -2.0 TBD µA ILO Output Leakage Current Output(s) disabled, -2.0 TBD µA 0V ≤ VIN≤ VCC VOH Output High Voltage IOH = -1.0mA VOL Output Low Voltage IOL = 1.0mA VCC Supply Voltage Isolated Output Buffer Supply VCCQ 2.0 V 1,3 0.4 V 1,3 3.135 3.465 V 1 3.135 VCC V 1,4 Conditions Typ. Max. Unit Note Capacitance Symbol Parameter CI Control Input Capacitance TA = 25°C; f = 1MHz 3 4 pF 6 CO Input/Output Capacitance (I/O) VCC = 3.3V 4 5 pF 6 CA Address Capacitance 3 3.5 pF 6 Note : 1. All voltages referenced to VSS (GND). 2. Overshoot : VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA Undershoot : VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA Power-up : VIH ≤ +3.465V and VCC ≤ 3.135V for t ≤ 200ms 3. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 4. VCC and VCCQ can be externally wired together to the same power supply. 5. This parameter is sampled. PRELIMINARY (July, 2005, Version 0.0) 10 AMIC Technology, Corp. A67L9318/A67L8336 ICC Operating Condition and Maximum Limits Max. Symbol Parameter ICC Unit Conditions TBD mA Device selected; All inputs ≤ VIL or ≥ VIH; Cycle time ≥ tKC (MIN); VCC = MAX; Outputs open TBD TBD mA Device deselected; VCC = MAX; All inputs ≤ VSS+0.2 or ≥ VCC0.2; Cycle time ≥ tKC (MIN) TBD TBD TBD mA TBD TBD TBD TBD mA TBD TBD TBD TBD mA -2.6 -2.8 -3.2 -3.5 -3.8 -4.2 Power Supply Current : Operating TBD TBD TBD TBD TBD ISB Standby TBD TBD TBD TBD ISB1 Standby TBD TBD TBD ISB2 Standby TBD TBD ISB2Z SLEEP Mode TBD TBD PRELIMINARY (July, 2005, Version 0.0) 11 Device deselected; VCC = MAX; All inputs ≤VSS+0.2 or ≥ VCC0.2; All inputs static; CLK frequency=0 ZZ ≤ 0.2V Device deselected; VCC = MAX; All inputs ≤ VIL; or ≥ VIH; All inputs static; CLK frequency=MAX ZZ ≥ VCC-0.2V ZZ ≥ VIH AMIC Technology, Corp. A67L9318/A67L8336 AC Characteristics (Note 4) (0°C ≤ TA ≤ 70°C, VCC = +3.3V± 5%) -2.6 Symbol -2.8 -3.2 -3.5 -3.8 -4.2 Unit Parameter Min Max Min Max Min Max Min Max Min Max Min Max Note Clock tKHKH Clock cycle time 4.0 - 4.4 - 5.0 - 6.0 - 6.7 - 7.5 - ns tKF Clock frequency - 250 - 227 - 200 - 166 - 150 - 133 MH tKHKL Clock HIGH time 1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns tKLKH Clock LOW time 1.7 - 2.0 - 2.0 - 2.2 - 2.5 - 3.0 - ns - 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns Output Times tKHQV Clock to output valid tKHQX Clock to output invalid 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns tKHQX1 Clock to output in Low-Z 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns 1,2,3 tKHQZ Clock to output in High-Z 1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.5 ns 1,2,3 tGLQV OE to output valid - 2.6 - 2.8 - 3.2 - 3.5 - 3.8 - 4.2 ns 4 tGLQX OE to output in Low-Z 0 - 0 - 0 - 0 - 0 - 0 - ns 1,2,3 tGHQZ OE to output in High-Z - 2.6 - 2.8 - 3.0 - 3.0 - 3.0 - 3.5 ns 1,2,3 Setup Times tAVKH Address 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 5 tEVKH Clock enable ( CEN ) 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 5 tCVKH Control signals 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 5 tDVKH Data-in 1.2 - 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns 5 Hold Times tKHAX Address 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns 5 tKHEX Clock enable ( CEN ) 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns 5 tKHCX Control signals 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns 5 tKHDX Data-in 0.3 - 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns 5 Notes: 1. This parameter is sampled. 2. Output loading is specified with C1=5pF as in Figure 2. 3. Transition is measured ±200mV from steady state voltage. 4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for turnaround timing. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADV/ LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK (when ADV/ LD is LOW) to remain enabled. PRELIMINARY (July, 2005, Version 0.0) 12 AMIC Technology, Corp. A67L9318/A67L8336 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise and Fall Times 1.0ns Input Timing Reference Levels 1.25V Output Reference Levels 1.25V Output Load See Figures 1 and 2 +3.3V 319Ω Q Q ZO=50Ω 50Ω 353Ω 5pF VT=1.5V Figure 1 Output Load Equivalent PRELIMINARY (July, 2005, Version 0.0) Figure 2 Output Load Equivalent 13 AMIC Technology, Corp. A67L9318/A67L8336 SLEEP Mode SLEEP Mode is a low current “Power-down” mode in which the device is deselected and current is reduced to ISB2Z. This duration of SLEEP Mode is dictated by the length of time the ZZ is in a HIGH state. After entering SLEEP Mode, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is asynchronous, active high input that causes the device to enter SLEEP Mode. When the ZZ pin becomes logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP Mode is not guaranteed to successfully complete. Therefore, SLEEP Mode (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SLEEP Mode during tRZZ, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode. SLEEP Mode Electrical Characteristics (VCC, VCCQ = +3.3V±5%) Symbol ISB2Z Parameter Current during SLEEP Mode Conditions Min. Max. Unit ZZ ≥ VIH - 60 mA Note tZZ ZZ active to input ignored 0 2(tKHKH) ns 1 tRZZ ZZ inactive to input sampled 0 2(tKHKH) ns 1 tZZI ZZ active to snooze current - 2(tKHKH) ns 1 tRZZI ZZ inactive to exit snooze current 0 ns 1 Note : 1. This parameter is sampled. SLEEP Mode Waveform CLK tZZ tRZZ ZZ tZZI I SUPPLY IISB2Z tRZZI ALL INPUTS (except ZZ) DESELECT or READ Only Output (Q) High-Z : Don't Care PRELIMINARY (July, 2005, Version 0.0) 14 AMIC Technology, Corp. A67L9318/A67L8336 READ/WRITE Timing 1 2 tKHKH 3 6 4 5 A3 A4 7 8 9 A5 A6 A7 10 CLK tEVKH tKHEX tKHKL tKLKH CEN tCVKH tKHCX CE ADV/ LD R/W BWx ADDRESS A2 A1 tAVKH tKHAX tKHQV tDVKH I/O tKHDX D(A1) D(A2) tKHQX1 D(A2+1) tKHQX Q(A3) tGLQV Q(A4) tKHQZ Q(A4+1) D(A5) Q(A6) WRITE D(A7) DESELECT tKHQX tGHQZ tGLQX OE COMMAND WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) : Don't Care : Undefined Note : 1. For this waveform, ZZ is tied LOW. 2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most recent data may be from the input data register. PRELIMINARY (July, 2005, Version 0.0) 15 AMIC Technology, Corp. A67L9318/A67L8336 NOP, STALL and Deselect Cycles 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/ LD R/W BWx ADDRESS A5 tKHQZ I/O D(A1) Q(A2) Q(A3) D(A4) Q(A5) tKHQX COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL NOP READ Q(A5) : Don't Care DESELECT CONTINUE DESELECT : Undefined Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a “pause.” A WRITE is not performed during this cycle. 2. For this waveform, ZZ and OE are tied LOW. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register. PRELIMINARY (July, 2005, Version 0.0) 16 AMIC Technology, Corp. A67L9318/A67L8336 Ordering Information Part No. Configure Cycle Time / Access Time Package A67L9318E-4.2 7.5ns / 4.2ns 100L LQFP A67L9318E-4.2F 7.5ns / 4.2ns 100L Pb-Free LQFP A67L9318E-3.8 6.7ns / 3.8ns 100L LQFP A67L9318E-3.8F 6.7ns / 3.8ns 100L Pb-Free LQFP A67L9318E-3.5 6.0ns / 3.5ns 100L LQFP 6.0ns / 3.5ns 100L Pb-Free LQFP A67L9318E-3.2 5.0ns / 3.2ns 100L LQFP A67L9318E-3.2F 5.0ns / 3.2ns 100L Pb-Free LQFP A67L9318E-2.8 4.4ns / 2.8ns 100L LQFP A67L9318E-2.8F 4.4ns / 2.8ns 100L Pb-Free LQFP A67L9318E-2.6 4.0ns / 2.6ns 100L LQFP A67L9318E-2.6F 4.0ns / 2.6ns 100L Pb-Free LQFP A67L8336E-4.2 7.5ns / 4.2ns 100L LQFP A67L8336E-4.2F 7.5ns / 4.2ns 100L Pb-Free LQFP A67L8336E-3.8 6.7ns / 3.8ns 100L LQFP A67L8336E-3.8F 6.7ns / 3.8ns 100L Pb-Free LQFP A67L8336E-3.5 6.0ns / 3.5ns 100L LQFP 6.0ns / 3.5ns 100L Pb-Free LQFP A67L8336E-3.2 5.0ns / 3.2ns 100L LQFP A67L8336E-3.2F 5.0ns / 3.2ns 100L Pb-Free LQFP A67L8336E-2.8 4.4ns / 2.8ns 100L LQFP A67L8336E-2.8F 4.4ns / 2.8ns 100L Pb-Free LQFP A67L8336E-2.6 4.0ns / 2.6ns 100L LQFP A67L8336E-2.6F 4.0ns / 2.6ns 100L Pb-Free LQFP A67L9318E-3.5F 512K X 18 A67L8336E-3.5F 256K X 36 PRELIMINARY (July, 2005, Version 0.0) 17 AMIC Technology, Corp. A67L9318/A67L8336 Package Information LQFP 100L Outline Dimensions unit: inches/mm HE A2 A1 D E 80 51 50 100 31 1 L1 L HD D 81 y 30 e b c θ Symbol A1 Dimensions in inches Dimensions in mm Min. Nom. Max. Min. Nom. Max. 0.002 - 0.006 0.05 - 0.15 A2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.009 0.012 0.015 0.22 0.30 0.38 c 0.004 - 0.008 0.09 - 0.20 HE 0.866 BSC E 0.787 BSC 20.00 BSC HD 0.630 BSC 16.00 BSC D 0.551 BSC 14.00 BSC e 0.026 BSC L 0.018 L1 0.024 22.00 BSC 0.65 BSC 0.030 0.45 0.039 REF 0.60 0.75 1.00 REF y - - 0.004 - - 0.10 θ 0° 3.5° 7° 0° 3.5° 7° Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. PRELIMINARY (July, 2005, Version 0.0) 18 AMIC Technology, Corp.