Rev 0; 4/05 Triple NV Low Step Size Variable Resistor Plus Memory Features The DS3906 is intended for low resistance, small stepsize applications. It contains three nonvolatile (NV), lowtemperature coefficient, variable digital resistors that are capable of ohm and subohm increments when used in parallel with a fixed external resistor. All three of the DS3906’s resistors have 64 positions (plus a high-Z state) with a pseudo-log response cleverly chosen to have a linear equivalent resistance when paired with an external resistor (see graphs below). The DS3906 also contains 16 bytes of user EEPROM that, in addition to the resistors, are controlled through an I2C™-compatible serial interface. Three address pins allow up to eight DS3906s to be placed on the same I2C bus. The DS3906 can also be factory cutomized to provide a variety of transfer functions depending on user requirements. Contact [email protected] for additional information. Applications ♦ Three Programmable Resistors for Low Step-Size Applications (Ohm and Subohm) ♦ Resistor Settings are NV ♦ 16-Byte NV User Memory (EEPROM) ♦ I2C-Compatible Serial Interface ♦ Up to 8 Devices Can be Multidropped on the Same I2C Bus ♦ Low Power Consumption ♦ Wide Operating Voltage (2.7V to 5.5V) ♦ Operating Temperature Range: -40°C to +85°C Ordering Information TEMP RANGE PACKAGE DS3906U PART -40°C to +85°C 10-Pin µSOP DS3906U+ -40°C to +85°C 10-Pin µSOP +Denotes lead-free package. Add “/T&R” for Tape-and-Reel orders Low Ohm, Fine Resolution Driver Control for LED Display Panels Pin Configuration TOP VEIW Low Ohm, Fine Resolution Instrumentation Control A1 1 Typical Operating Circuit appears at end of data sheet. 10 A2 SDA 2 9 A0 SCL 3 8 H0 7 H1 6 H2 VCC 4 GND 5 DS3906 10-PIN µSOP Resistor Plots RESISTOR 0 AND 1 RESISTANCE vs. POSITION (WITH AND WITHOUT EXTERNAL RESISTOR) 180 R0 350 REXT0 300 140 R0, 1 || (REXT = 105Ω) 120 1500 100 100 80 R0, 1 || (REXT = 50Ω) 60 500 R0, 1 WITHOUT REXT (Ω) 2000 DS3906 R1 REXT1 REFFECTIVE = R2 || REXT (Ω) 2500 R0, 1 || (REXT = 150Ω) 160 1600 R2 || (REXT = 400Ω) 1200 200 1000 150 R2 || (REXT = 250Ω) 800 100 R2 WITHOUT REXT 40 20 20 R0, 1 WITHOUT REXT 0 0 16 32 48 RESISTOR POSITION (dec) 0 64 R2 REXT2 1400 R2 || (REXT = 310Ω) 250 R2 WITHOUT REXT (Ω) 3000 200 REFFECTIVE = R0, 1 || REXT (Ω) RESISTOR 2 RESISTANCE vs. POSITION (WITH AND WITHOUT EXTERNAL RESISTOR) 600 50 0 400 0 16 32 48 64 RESISTOR POSITION (dec) I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips Corp. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3906 General Description DS3906 Triple NV Low Step Size Variable Resistor Plus Memory ABSOLUTE MAXIMUM RATINGS Voltage on VCC, SDA, SCL, and H0-H2 Pins Relative to Ground.............................................-0.5V to +6.0V Voltage on A0, A1, and A2 Relative to Ground .....-0.5V to VCC + 0.5V, not to exceed +6.0V Resistor Current ....................................................................5mA Operating Temperature Range ...........................-40°C to +85°C EEPROM Programming Temperature Range .........0°C to +70°C Storage Temperature Range ............................-55°C to +125°C Soldering Temperature...................See J-STD-020 Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER SYMBOL MAX UNITS +2.7 +5.5 V VIH 0.7 x VCC VCC + 0.3 V VIL -0.3 0.3 x VCC V -0.3 +5.5 V 5 mA MAX UNITS Supply Voltage VCC Input Logic 1 Input Logic 0 Resistor Inputs Resistor Current CONDITIONS (Note 1) H0, H1, H2 VCC = 2.7V to 5.5V MIN TYP IR DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL Standby Current (Note 2) ISTBY Input Leakage for All Pins IL Low-Level Output Voltage (SDA) I/O Capacitance VOL SDA CONDITIONS MIN TYP 3V 130 5V 160 (Note 3) 250 -1.0 +1.0 3mA sink current 0 0.4 6mA sink current 0 0.6 CI/O µA µA V 10 pF MAX UNITS +20 % LSB ANALOG RESISTOR CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP Resistor Tolerance From nominal values in Table 3 INL (Note 4) -2 +2 DNL (Note 4) -0.5 +0.5 Temperature Coefficient At position 3Fh (Note 8) Resistor High-Z Resistors 2 RHIGH-Z -20 60 5.5 Guaranteed monotonic by design _____________________________________________________________________ LSB ppm/°C MΩ Triple NV Low Step Size Variable Resistor Plus Memory DS3906 AC ELECTRICAL CHARACTERISTICS (See Figure 2) (VCC = +2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS TYP UNITS 400 kHz fSCL Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs tHD:STA 0.6 µs tLOW 1.3 µs Low Period of SCL High Period of SCL 0 MAX SCL Clock Frequency Hold Time (Repeated) Start Condition (Note 5) MIN tHIGH 0.6 Data Hold Time tHD:DAT 0 Data Set-up Time tSU:DAT 100 ns Start Set-up time tSU:STA 0.6 µs SDA and SCL Rise Time tR (Note 6) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 6) 20 + 0.1CB 300 ns Stop Set-up Time tSU:STO µs 0.9 0.6 µs µs SDA and SCL Capacitive Loading CB (Note 6) 400 pF EEPROM Write Time tWR (Note 7) 20 ms MAX UNITS NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.7V to 5.5V) PARAMETER EEPROM Writes SYMBOL CONDITIONS 0°C to +70°C. The room temperature specification is at least 4x better than specification over 0°C to +70°C. MIN TYP 50,000 Note 1: All voltages referenced to ground. Note 2: ISTBY is specified with SDA = SCL = VCC, resistor pins floating, and inputs tied to VCC or GND. Note 3: The DS3906 will not obstruct the SDA and SCL lines if VCC is switched off as long as the voltages applied to these input do not violate their minimum and maximum input voltage levels. Note 4: Tested with external resistor of 87Ω for R0 and R1 and 258Ω for R2 at 25°C. Note 5: Timing shown is for fast mode (400kHz) operation. This device is also backward compatible with I2C standard mode timing. Note 6: CB⎯total capacitance of one bus line in picofarads. Note 7: The EEPROM write time begins after a stop condition occurs. Note 8: Guaranteed by design. _____________________________________________________________________ 3 Typical Operating Characteristics (VCC = +5.0V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 120 100 80 60 VCC = 3.3V 120 100 80 60 40 40 20 20 SDA/SCL = VCC ADDRESS PINS CONNECTED TO GND 3.70 3.20 4.20 4.70 5.20 80 60 VCC = SDA = 5V ADDRESS PINS CONNECTED TO GND 20 0 -40 -15 10 35 85 60 0 100 150 200 250 300 350 400 50 SCL FREQUENCY (kHz) RESISTORS (R0,1) vs. RESISTOR SETTING RESISTOR R2 vs. RESISTOR SETTING RESISTANCE (R0,1⎥⎥ REXT) vs. RESISTOR SETTING RESISTOR (R2) (Ω) 1500 1000 1000 800 600 400 500 80 200 0 60 70 RESISTANCE (R2⎥⎥ REXT) vs. RESISTOR SETTING DS3906 toc07 200 REXT = 258Ω 150 100 50 0 0 10 50 30 20 40 RESISTOR SETTING (dec) 60 50 40 30 20 0 0 250 REXT = 87Ω 60 70 10 20 30 40 50 RESISTOR SETTING (dec) 60 0 70 10 50 30 20 40 RESISTOR SETTING (dec) RESISTOR R0,1 TEMPERATURE COEFFICIENT (-40°C TO +25°C) vs. RESISTOR SETTING 250 DS3906 toc08 50 RESISTOR SETTING (dec) RESISTOR R0,1 TEMPERATURE COEFFICIENT (ppm/°C) 40 70 10 0 30 20 DS3906 toc06 1400 90 RESISTANCE (R0,1⎥⎥ REXT) (Ω) DS3906 toc05 DS3906 toc04 1600 1200 2000 RESISTANCE (R2⎥⎥ REXT) (Ω) 100 TEMPERATURE (°C) 2500 10 120 SUPPLY VOLTAGE (V) 3000 0 140 40 0 2.70 DS3902 toc03 160 140 0 4 180 SUPPLY CURRENT (µA) 140 VCC = 5V 160 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 160 200 DS3906 toc02 180 SUPPLY CURRENT vs. SCL FREQUENCY 180 DS3906 toc01 200 RESISTORS (R0,1) (Ω) DS3906 Triple NV Low Step Size Variable Resistor Plus Memory 200 150 -40°C TO +25°C 100 50 0 -50 0 10 _____________________________________________________________________ 50 30 20 40 RESISTOR SETTING (dec) 60 70 60 70 Triple NV Low Step Size Variable Resistor Plus Memory 250 200 150 100 50 0 50 30 20 40 RESISTOR SETTING (dec) 60 5 0 -5 -10 -15 -20 -25 70 0 10 50 30 20 40 RESISTOR SETTING (dec) 60 +25°C TO +85°C DS3906 toc11 160 140 120 100 80 60 40 20 0 70 0 50 30 20 40 RESISTOR SETTING (dec) 10 60 70 R0,1 RESISTANCE AT POSITION 2Fh vs. POWER-UP VOLTAGE 2000 1500 RESISTOR R2 AT POSITION 1Fh 1000 500 5000 R0,1 RESISTANCE AT POSITION 2Fh (Ω) DS3906 toc12 RESISTANCE vs. SUPPLY VOLTAGE RESISTOR R0,1 AT POSITION 2Fh >5.5MΩ 4500 RESISTORS R0,1 4000 3500 EEPROM RECALL 3000 2500 2000 1500 PROGRAMMED VALUE 1000 500 0 0 3.20 3.70 4.20 4.70 1 3 2 5 4 SUPPLY VOLTAGE (V) POWER-SUPPLY VOLTAGE (V) R2 RESISTANCE AT POSITION 1Fh vs. POWER-UP VOLTAGE R0,1 RESISTANCE AT POSITION 2Fh vs. POWER-UP VOLTAGE RESISTOR R2 >5.5MΩ 3000 EEPROM RECALL 2500 2000 1500 PROGRAMMED VALUE 1000 500 0 500 R0,1 RESISTANCE AT POSITION 2Fh (Ω) 4000 3500 0 5.20 DS3906 toc14 2.70 450 DS3906 toc15 10 RESISTANCE (Ω) 0 -40°C TO +25°C 180 DS3906 toc13 300 10 RESISTOR R2 TEMPERATURE COEFFICIENT (+25°C TO +85°C) vs. RESISTOR SETTING RESISTOR R2 TEMPERATURE COEFFICIENT (ppm/°C) +25°C TO +85°C 15 DS3906 toc10 350 RESISTOR R2 TEMPERATURE COEFFICIENT (-40°C TO +25°C) vs. RESISTOR SETTING RESISTOR R2 TEMPERATURE COEFFICIENT (ppm/°C) DS3906 toc09 400 R2 RESISTANCE AT POSITION 1Fh (Ω) RESISTOR R0,1 TEMPERATURE COEFFICIENT (ppm/°C) RESISTOR R0,1 TEMPERATURE COEFFICIENT (+25°C TO +85°C) vs. RESISTOR SETTING >5.5MΩ RESISTOR R0,1 400 350 EEPROM RECALL 300 250 200 150 PROGRAMMED VALUE 100 50 0 0 1 2 3 4 POWER-UP VOLTAGE (V) 5 0 5 4 3 2 1 0 POWER-DOWN VOLTAGE (V) _____________________________________________________________________ 5 DS3906 Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5.0V, TA = +25°C, unless otherwise noted.) INL vs. RESISTOR SETTING FOR (R0⎥⎥ REXT) (R0⎥⎥ REXT) REXT = 87Ω 1.5 3000 1.0 DS3906 toc17 3500 >5.5MΩ RESISTOR R2 2.0 DS3906 toc16 4000 DNL vs. RESISTOR SETTING FOR (R0⎥⎥ REXT) DS3906 toc18 R2 RESISTANCE AT POSITION 1Fh vs. POWER-UP VOLTAGE (R0⎥⎥ REXT) REXT = 87Ω 0.8 0.6 1.0 0.4 EEPROM RECALL 2000 1500 0.5 DNL (LSB) 2500 INL (LSB) 0 -0.5 PROGRAMMED VALUE 1000 0.2 0 -0.2 -0.4 -1.0 -0.6 500 -1.5 0 -2.0 4 5 3 2 0 1 -0.8 0 POWER-DOWN VOLTAGE (V) 10 20 30 40 50 RESISTOR SETTING (dec) -1.0 60 0 50 DNL vs. RESISTOR SETTING FOR (R1⎥⎥ REXT) 1.0 DS3906 toc19 (R1⎥⎥ REXT) REXT = 87Ω 1.5 40 RESISTOR SETTING (dec) INL vs. RESISTOR SETTING FOR (R1⎥⎥ REXT) 2.0 30 20 10 DS3906 toc20 R2 RESISTANCE AT POSITION 1Fh (Ω) (R1⎥⎥ REXT) REXT = 87Ω 0.8 0.6 1.0 0.5 DNL (LSB) INL (LSB) 0.4 0 -0.5 0.2 0 -0.2 -0.4 -1.0 -0.6 -1.5 -0.8 -2.0 -1.0 10 20 30 40 50 60 10 20 30 40 50 60 RESISTOR SETTING (dec) INL vs. RESISTOR SETTING FOR (R2⎥⎥ REXT) DNL vs. RESISTOR SETTING FOR (R2⎥⎥ REXT) 1.0 DS3906 toc21 2.0 (R2⎥⎥ REXT) REXT = 258Ω 1.5 0 RESISTOR SETTING (dec) DS3906 toc22 0 (R2⎥⎥ REXT) REXT = 258Ω 0.8 0.6 1.0 0.4 0.5 DNL (LSB) INL (LSB) DS3906 Triple NV Low Step Size Variable Resistor Plus Memory 0 -0.5 0.2 0 -0.2 -0.4 -1.0 -0.6 -1.5 -0.8 -2.0 -1.0 0 6 10 20 30 40 50 RESISTOR SETTING (dec) 60 0 10 _____________________________________________________________________ 30 40 50 20 RESISTOR SETTING (dec) 60 60 Triple NV Low Step Size Variable Resistor Plus Memory PIN NAME 1 A1 FUNCTION 2 SDA I2C Serial Data Open-Drain Input/Output 3 SCL I2C Serial Clock Input 4 VCC Power Supply Voltage 5 GND 6 H2 High Terminal of Resistor 2 7 H1 High Terminal of Resistor 1 8 H0 High Terminal of Resistor 0 9 A0 10 A2 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. Ground I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. Block Diagram VCC EEPROM RHIZ CONTROL H0 VCC Detailed Description The DS3906 contains three variable resistors plus a user EEPROM. The block diagram illustrates these in addition to the registers that control the resistors. The following sections provide detailed information about the DS3906. Memory Organization F8h DS3906 RESISTOR 0 MSB GND 6 LSB RES 0 2.54kΩ RHIZ CONTROL H1 SCL SDA A0 A1 A2 F9h I2C INTERFACE RESISTOR 1 MSB 6 LSB USER EEPROM 16 BYTES (00h-0Fh) FAh MSB RESISTOR 2 6 LSB Resistor Registers/Settings RES 1 2.54kΩ RHIZ CONTROL H2 RES 2 1.45kΩ The DS3906 contains 16 bytes of User EEPROM plus 3 NV resistor registers. Refer to Table 1. Communication with the memory/registers is achieved through the I2Ccompatible serial interface and is described in subsequent sections. Each of the three resistors in the DS3906 has its own control register used to set the resistor position. Refer to the block diagram and Table 2. Each resistor has 64 positions plus a high impedance state. The nominal resistance values for each position is listed in Table 3. Resistors 0 and 1 have the same full-scale resistance, which is different than resistor 2. As shown in Table 3, the resistors have a pseudo-log response (resistance vs. position) when used without an external parallel resistor. Valid resistor settings are 00h to 3Fh. Writing a value greater than 3Fh to any of the resistor registers _____________________________________________________________________ 7 DS3906 Pin Description DS3906 Triple NV Low Step Size Variable Resistor Plus Memory makes the corresponding resistor go High-Z. Plots for both resistor sizes are shown on the front page of this data sheet. It can be seen that, when an external resistor is connected in parallel with the DS3906’s resistors, the effective resistance is linear and capable of achieving sub-ohm and ohm steps. The resistor settings are stored in EEPROM memory. It is important to point out that the DS3906 EEPROM is organized in 2-byte pages. This is transparent when reading from the device or when performing single byte writes. However, this limits the maximum number of bytes that can be written in one I2C transaction to two. Furthermore, the multiple byte writes must begin on even memory addresses (00h, 02h, …., F8h, etc). Additional information is provided later in the I 2 C Communication section . Example communication transactions are provided in Figure 3. Table 1. DS3906 Memory Map ADDRESS TYPE NAME 00h to 0Fh EEPROM User memory F8h EEPROM Resistor 0 F9h EEPROM Resistor 1 FAh EEPROM Resistor 2 FACTORY DEFAULT FUNCTION 16 bytes of general-purpose user EEPROM. 00h 3Fh Resistor 0-2 settings. See Table 2 and the Resistor Registers/Settings section. FBh-FFh 3Fh 3Fh Reserved Table 2. DS3906 Resistor Registers ADDRESS VARIABLE RESISTOR POSITION 3FH RESISTANCE (kΩ) F8h Resistor 0 2.54 F9h Resistor 1 2.54 FAh Resistor 2 1.45 NUMBER OF POSITIONS* 64 (00h to 3Fh) + High-Z * Writing a value greater than 3Fh to any of the resistor registers makes the corresponding resistor go High-Z. Position 3Fh is the maximum position. 8 _____________________________________________________________________ Triple NV Low Step Size Variable Resistor Plus Memory DS3906 Table 3. DS3906 Resistor Settings (without external resistor) POSITION NOMINAL RESISTOR VALUES WITHOUT EXT RESISTOR (25°C) POSITION NOMINAL RESISTOR VALUES WITHOUT EXT RESISTOR (25°C) Dec Hex Resistors 0, 1 Resistor 2 Dec Hex Resistors 0, 1 Resistor 2 0 00 175.0 469.7 32 20 396.1 768.4 1 01 178.8 476.4 33 21 409.1 781.7 2 02 182.7 483.2 34 22 422.9 795.4 3 03 186.8 490.1 35 23 437.5 809.4 4 04 190.9 497.2 36 24 452.9 823.9 5 05 195.2 504.4 37 25 469.3 838.7 6 06 199.6 511.7 38 26 486.7 853.9 7 07 204.2 519.2 39 27 505.2 869.6 8 08 208.9 526.8 40 28 525.0 885.7 9 09 213.7 534.6 41 29 546.1 902.3 10 0A 218.8 542.5 42 2A 568.8 919.4 11 0B 223.9 550.6 43 2B 593.1 936.9 12 0C 229.3 558.8 44 2C 619.2 955.1 13 0D 234.9 567.3 45 2D 647.5 973.7 14 0E 240.6 575.9 46 2E 678.1 993.0 15 0F 246.6 584.6 47 2F 711.4 1012.8 16 10 252.8 593.6 48 30 747.7 1033.3 17 11 259.2 602.8 49 31 787.5 1054.5 18 12 265.9 612.1 50 32 831.3 1076.4 19 13 272.8 621.7 51 33 879.6 1099.0 20 14 280.0 631.5 52 34 933.3 1122.4 21 15 287.5 641.5 53 35 993.4 1146.6 22 16 295.3 651.7 54 36 1060.9 1171.7 23 17 303.5 662.2 55 37 1137.5 1197.7 24 18 312.0 672.9 56 38 1225.0 1224.7 25 19 320.8 683.8 57 39 1326.0 1252.7 26 1A 330.1 695.0 58 3A 1443.8 1281.7 27 1B 339.8 706.5 59 3B 1583.0 1311.9 28 1C 350.0 718.3 60 3C 1750.0 1343.3 29 1D 360.7 730.3 61 3D 1954.2 1376.0 30 1E 371.9 742.7 62 3E 2209.4 1410.1 31 1F 383.7 755.4 63 3F 2537.5 1445.6 _____________________________________________________________________ 9 DS3906 Triple NV Low Step Size Variable Resistor Plus Memory External Resistor Selection/Considerations Using an external resistor in parallel with any of the DS3906’s resistors makes the effective resistance linear with small increments from position to position. Typical values for the external resistors are 87Ω for Resistor 0 and 1 and 258Ω for Resistor 2. The effective resistance will be the most linear when these values are used. Of course these values may be tweaked to achieve the desired step size and range. The effects of changing REXT is shown on the front page. Likewise, a series resistor may be used to further customize the desired response. If the DS3906’s transfer function does not meet the applications needs, contact the factory at the email address provided on the front page to inquire about custom resistance values. I2C Slave Address and Address Pins The DS3906’s I2C slave address is determined by the state of the A0, A1, and A2 address pins as shown in MSB 1 LSB 0 1 0 A2 A1 A0 R/W READ/WRITE BIT SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2. Figure 1. DS3906 Slave Address Byte Figure 1. Address pins tied to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins tied to VCC result in a ‘1’ in the corresponding bit positions. I2C communication is described in detail in the following section. I2C Serial Interface Description I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions. Slave Devices: Slave devices send and receive data at the master’s request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic high states. When the bus is idle it often initiates a low power mode for slave devices. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing. SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 2. I2C Timing Diagram 10 ____________________________________________________________________ tSU:STO Triple NV Low Step Size Variable Resistor Plus Memory Bit Read: At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 2) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 2) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7-bits and the R/W bit in the least significant bit. The DS3906’s slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 1. Address pins tied to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins tied to VCC result in a ‘1’ in the corresponding bit positions. When the R/W bit is 0 (such as in A0h), the master is indicating it writes data to the slave. If R/W = 1, (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS3906 assumes the master is communicating with another I2C device and ignore the communication until the next start condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: The DS3906 is capable of writing up to 2 bytes (1-page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 2-byte page. Pages begin on even addresses (00h, 02h, 04h, etc). Attempts to write more than 2 bytes of memory without at once without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. To write multiple bytes to a slave in one transaction, the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address (must be even), writes two data bytes, and generates a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. ____________________________________________________________________ 11 DS3906 Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition, See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (see Figure 2). Data is shifted into the device during the rising edge of the SCL. DS3906 Triple NV Low Step Size Variable Resistor Plus Memory Acknowledge Polling: Any time an EEPROM page is written, the DS3906 requires the EEPROM write time (tW) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3906, which allows communication to continue as soon as the DS3906 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM Write Cycles: When EEPROM writes occur, the DS3906 internally writes the whole EEPROM page (2bytes) even if only a single byte write was performed. Writes that do not modify all 2 bytes on the page are valid and do not corrupt any of other bytes on the same page. Because the whole page is written, even bytes on the page that were not modified during the transaction are still subject to a write cycle. The DS3906’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature. It is capable of handling many additional writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a start condition, writes the slave address byte (R/W =0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. See Figure 3 for a read example using the repeated start condition to specify the starting memory location. TYPICAL I2C WRITE TRANSACTION MSB START 1 LSB 0 1 0 A2 A1 A0 R/W MSB SLAVE ACK b7 READ/ WRITE SLAVE ADDRESS* LSB b6 b5 b4 b3 b2 b1 b0 MSB SLAVE ACK b7 LSB b6 b5 b4 REGISTER/MEMORY ADDRESS b3 b2 b1 b0 SLAVE ACK STOP DATA *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2. EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND) A0h F9h A) SINGLE BYTE WRITE -WRITE RESISTOR 1 TO 00h START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 ACK B) SINGLE BYTE READ -READ RESISTOR 0 START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE ACK ACK A0h F8h A0h C) SINGLE BYTE WRITE -WRITE FIRST BYTE OF USER EEPROM TO FFh SLAVE SLAVE START 1 0 1 0 0 0 0 0 00000 000 ACK ACK 00000000 START 1 0 1 0 0 0 0 0 00000 000 STOP DATA 1 0 1 0 0 0 0 1 SLAVE ACK 00h 00h 00h SLAVE SLAVE 000 00000 ACK ACK SLAVE ACK STOP REPEATED START STOP 00h SLAVE ACK 00000000 SLAVE ACK STOP LOCATION 00h A1h 1 0 1 0 0 0 0 1 SLAVE DATA ACK Figure 3. I2C Communication Examples 12 MASTER NACK RES 0 FFh 111 1 1 1 1 1 A0h E) TWO BYTE READ -READ TWO BYTES OF USER EEPROM STARTING FROM 00h 00h SLAVE ACK SLAVE ACK A1h REPEATED START SLAVE ACK START 1 0 1 0 0 0 0 0 A0h D) TWO BYTE WRITE -WRITE TWO BYTES OF USER EEPROM TO 00h SLAVE 0 0 0 0 0 0 0 0 ACK ____________________________________________________________________ LOCATION 01h MASTER ACK DATA MASTER NACK STOP Triple NV Low Step Size Variable Resistor Plus Memory Application Information Power Supply Decoupling To achieve best results, it is highly recommended that a decoupling capacitor is used on the I.C. power supply pins. Typical values of decoupling capacitors are 0.01µF and 0.1µF. Use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the VCC and GND pins of the I.C. to minimize lead inductance. High Resistor Terminal Voltage It is permissible to have a voltage on the resistor-high terminals that is higher than the voltage connected to VCC. For instance, connecting VCC to 3.0V while one or more of the resistor high terminals are connected to 5.0V allows a 3V system to control a 5V system. The 5.5V maximum still applies to the limit on the resistor high terminals regardless of the voltage present on VCC. Typical Operating Circuit GREEN LED PANEL BLUE LED PANEL RED LED PANEL 300Ω 300Ω 300Ω 300Ω LED DRIVERS 300Ω 300Ω 300Ω 300Ω 300Ω 300Ω 300Ω LED DRIVERS 300Ω LED DRIVERS H0 VCC R0 REXT0 = 105Ω VCC 0.1µF H1 4.7kΩ FROM SYSTEM CONTROLLER DS3906 R1 4.7kΩ SCL SDA A0 A1 A2 GND REXT1 = 105Ω H2 R2 REXT2 = 310Ω DESIGN NOTES: 1. IN THIS APPLICATION A NUMBER OF LED DRIVERS ARE SET USING THE DS3906'S VARIABLE RESISTORS. 2. THE PARALLEL COMBINATION OF THE DS3906 VARIABLE RESISTOR R0 AND 105Ω (REXT0) IS EQUIVALENT TO A VARIABLE RESISTOR WITH LINEAR STEP INCREMENTS OF 0.6Ω RANGING FROM 66Ω TO 101Ω. THE SAME APPLIES FOR RESISTOR 1 (R1). THE PARALLEL COMBINATION OF R2 AND 310Ω (REXT2) IS EQUIVALENT TO A VARIABLE RESISTOR WITH LINEAR STEP INCREMENTS OF 1Ω RANGING FROM 187Ω TO 255Ω. 3. VALUES LARGER THAN THE SHOWN EXTERNAL RESISTORS (REXT0, REXT1, AND REXT2) RESULT IN LARGER STEP INCREMENTS AND RESISTOR VALUES LOWER THAN THE SHOWN VALUES RESULT IN SMALLER STEP INCREMENTS. REFER TO THE RESISTOR TABLES AND COMPUTE EQUIVALENT RESISTANCE TO FIND OUT THE RANGES. ____________________________________________________________________ 13 DS3906 Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a stop condition. DS3906 Triple NV Low Step Size Variable Resistor Plus Memory Package Information Chip Topology TRANSISTOR COUNT: 16,200 SUBSTRATE CONNECTED TO GROUND For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.