TDA7575B 2 x 75W multifunction dual-bridge power amplifier with integrated digital diagnostics Features ■ Multipower bcd technology ■ MOSFET output power stage ■ DMOS power output ■ New high-efficiency (class AB) ■ Single-channel 1driving capability ■ High output power capability 2x28 W/4 @ 14.4 V, 1 kHz, 10 % THD ■ Max. output power 2x75 W/2 1x150 W/1 ■ Single-channel 1 driving capability ■ 84 W undistorted power ■ Full I2C bus driving with 4 address possibilities: – Standby – Play/mute – Gain 12/26 dB – Full digital diagnostic (AC and DC loads) PowerSO36 (slug up) ■ Possibility to disable the I2C bus ■ Differential inputs ■ Full fault protection ■ DC offset detection ■ Two independent short circuit protections ■ Diagnostic on clipping detector with selectable threshold (2 % / 10 %) ■ Clipping detector as diagnostic pin when I2C bus is disabled ■ Standby/mute pins ■ ESD protection Table 1. Flexiwatt27 Description The TDA7575B is a new MOSFET dual bridge amplifier specially intended for car radio applications. Thanks to the DMOS output stage the TDA7575B has a very low distortion allowing a clear powerful sound. Among the features, its superior efficiency performance coming from the internal exclusive structure, makes it the most suitable device to simplify the thermal management in high power sets.The dissipated output power under average listening condition is in fact reduced up to 50% when compared to the level provided by conventional class AB solutions. This device is equipped with a full diagnostic array that communicates the status of each speaker through the I2C bus. The TDA7575B has also the possibility of driving loads down to 1 paralleling the outputs into a single channel. It is also possible to disable the I2C and control the TDA7575B by means of the usual standby and mute pins. Device summary Order code Package Packing TDA7575B Flexiwatt27 Tube TDA7575BPD PowerSO36 (slug up) Tube TDA7575BPDTR PowerSO36 (slug up) Tape and reel September 2013 Doc ID 14103 Rev 3 1/32 www.st.com 1 Contents TDA7575B Contents 1 Block and pins diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 5.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 1 W capability setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6 I2C abilitation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 7 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.6 Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.7 I2C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 Doc ID 14103 Rev 3 TDA7575B List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Double fault table for turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Doc ID 14103 Rev 3 3/32 List of figures TDA7575B List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. 4/32 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Quiescent drain current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Distortion vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Distortion vs. output voltage (LD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Cross talk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Cross talk vs. frequency (LD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CMRRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output attenuation vs. supply voltage (vs. dependent muting) . . . . . . . . . . . . . . . . . . . . . . 13 Output attenuation vs. mute pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power dissipation vs. output power (4 - SINE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power dissipation vs. output power (2 - SINE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power dissipation vs. average output power (Audio program simulation, 4) . . . . . . . . . . 14 Power dissipation vs. average output power (Audio program simulation, 2) . . . . . . . . . . 14 ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 14 Application circuit (TDA7575B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application circuit (TDA7575BPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing diagram on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Timing acknowledge clock pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Turn-on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SVR and output behavior - case 1: without turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . 23 SVR and output pin behavior - case 2: with turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . 24 Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Restart timing without diagnostic enable (permanent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 27 Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 27 PowerSO36 (slug up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 29 Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 30 Doc ID 14103 Rev 3 TDA7575B 1 Block and pins diagrams Block and pins diagrams Figure 1. Block diagram ADDRESS A B VS CLK DATA VCC CD_OUT CLIP DETECTOR I2CBUS IN1+ OUT1+ IN1OUT1SHORT CIRCUIT PROTECTION IN2+ OUT2+ IN2- OUT2SHORT CIRCUIT PROTECTION SVR S_GND ST-BY/HE PW_GND TAB I2C EN 1Ω MUTE D01AU1269 Figure 2. OUT1+ Pins connection diagram (top view) 1 36 TAB 27 TAB 26 PWGND 25 A 24 OUT2+ N.C. OUT1+ 35 2 IN1+ VCC 34 3 IN1- 23 VCC 33 4 MUTE 22 OUT2- B 32 5 ST_BY 21 VCC PWGND 31 6 SGND 20 IN2+ 19 IN2- PWGND 30 7 DATA 18 I2CEN OUT1- 29 8 CK 17 1Ω OUT1- 28 9 N.C. 16 CD_OUT OUT2- 27 10 N.C. 15 SVR 14 CK OUT2- 26 11 N.C. 13 DATA PWGND 25 12 N.C. 12 SGND PWGND 24 13 SVR 11 STT-BY A 23 14 CD-OUT 10 MUTE VCC 22 15 VCC 21 OUT2+ OUT2+ 9 IN1- 1-OHM 8 IN1+ 16 I2C-EN 7 VCC 20 17 IN2- 6 OUT1- 19 18 IN2+ 5 N.C. 4 OUT1+ D01AU1270 3 B PowerSO36 (slug up) 2 PWGND 1 TAB D03IN1512 Flexiwatt27 Doc ID 14103 Rev 3 5/32 Electrical specifications TDA7575B 2 Electrical specifications 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit Vop Operating supply voltage 18 V VS DC supply voltage 28 V Peak supply voltage (for t = 50 ms) 50 V CK pin voltage 6 V Data pin voltage 6 V IO Output peak current (not repetitive t = 100 ms) 8 A IO Output peak current (repetitive f > 10 Hz) 6 A Power dissipation Tcase = 70 °C 86 W -55 to 150 °C Vpeak VCK VDATA Ptot Tstg, Tj Storage and junction temperature 2.2 Thermal data Table 3. Thermal data Symbol Rth j-case 2.3 Parameter Thermal resistance junction-to-case Max PowerSO36 Flexiwatt 27 Unit 1 1 °C/W Electrical characteristics VS = 14.4 V; f = 1 kHz; RL = 4 ; Tamb= 25 °C unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit 8 - 18 V 50 130 200 mA Max. power 35 40 - W THD = 10 % THD = 1 %; BTL mode 25 28 22 - W RL = 2 ; THD 10 % RL = 2 ; THD 1 % RL = 2 ; Max. power(1) 45 50 37 75 - W Power amplifier VS Supply voltage range - Id Total quiescent drain current (1) Po 6/32 Output power Doc ID 14103 Rev 3 70 TDA7575B Table 4. Electrical specifications Electrical characteristics (continued) Symbol Po THD Parameter Output power Total harmonic distortion Test condition Min. Typ. Max. Unit 80 140 84 150 - W Po = 1-12 W; STD mode HE mode; Po = 1-2 W HE mode; Po = 4-8 W - 0.03 0.03 0.5 0.1 0.1 % Po = 1-12 W, f = 10 kHz - 0.15 0.5 % RL = 2; HE mode; Po = 3 W - 0.03 0.5 % Single channel configuration (1 pin > 2.5 V); RL = 1; Po = 4-30 W - 0.02 0.1 % Single channel configuration (1 pin > 2.5 V); RL = 1 ; THD 3 % Max. power(1) CT Cross talk Rg = 600 Po = 1 W 60 75 - dB RIN Input impedance - 60 100 130 k GV1 Voltage gain 1 (default) - 25 26 27 dB Voltage gain match 1 - -1 0 1 dB Voltage gain 2 - 11 12 13 dB GV2 Voltage gain match 2 - -1 0 1 dB EIN1 Output noise voltage gain 1 Rg = 600 ; Gv = 26 dB filter 20 to 22 kHz - 40 60 V EIN2 Output noise voltage gain 2 Rg = 600 ; Gv = 12d B filter 20 to 22 kHz - 15 25 V SVR Supply voltage rejection f = 100 Hz to 10 kHz; Vr = 1 Vpk; Rg = 600 50 60 - dB BW Power bandwidth (-3 dB) 100 - - KHz ASB Standby attenuation - 90 100 - dB ISB Standby current consumption Vst-by = 0 V - 2 10 A AM Mute attenuation - 80 90 VOS Offset voltage Mute and play -45 0 45 mV VAM Min. supply mute threshold - 7 7.5 8 V Input CMRR VCM = 1 Vpk-pk; Rg = 0 56 60 - - 1 Vrms 1.5 4 - V/s -10 - +10 mV -10 - +10 mV GV1 GV2 CMRR VMC Maximum common mode input f = 1 kHz level SR Slew rate VOS - During mute on/off output offset voltage ITU R-ARM weighted see Figure 23 During standby on/off output offset voltage Doc ID 14103 Rev 3 dB dB 7/32 Electrical specifications Table 4. TDA7575B Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit TON Turn on delay D2 (IB1) 0 to 1 - 15 40 ms TOFF Turn off delay D2 (IB1) 1 to 0 - 15 40 ms VOFF Standby pin for standby - 0 - 1.5 V VSB Standby pin for standard bridge - 3.5 - 5 V VHE Standby pin for high-efficiency - 7 - 18 V Standby pin current 1.5 < Vst-by/HE < 18 V 7 160 200 A Standby pin current Vst-by < 1.5 V -10 0 10 A IO Vm Mute pin voltage for mute mode - 0 - 1.5 V Vm Mute pin voltage for play mode - 3.5 - 18 V Im Mute pin current (standby) Vmute = 0 V, Vst-by < 1.5V -5 0 5 A Im Mute pin current (operative) 0 V < Vmute < 18 V, Vst-by > 3.5 V - 65 100 A 0 - 1.5 V - 2.5 - 18 V VI2C I2C VI2C I2C I2C I2C pin current (standby) 0V < I2C EN < 18V, Vstby < 1.5V -5 0 5 A I2C I2C 7 11 15 A I 2C pin voltage for I2C disabled - pin voltage for I2C enabled pin current (operative) EN <18V, Vst-by>3.5V V1 1 pin voltage for 2ch mode - 0 - 1.5 V V1 1 pin voltage for 1 mode - 2.5 - 18 V I1 1 pin current (standby) 0 V < 1 <18 V, Vs-tby < 1.5 V -5 0 5 A I1 1 pin current (operative) 1 < 18 V, Vst-by > 3.5 V 7 11 15 A Low logic level 0 - 1.5 V High logic level 2.5 - 18 V La A pin voltage Ha Ia A pin current (standby) 0V < A < 18V , Vstby < 1.5 V -5 0 5 A Ia A pin current (operative) A<18V, Vst-by > 3.5V 7 11 15 A Low logic level 0 - 1.5 V High logic level 2.5 - 18 V Lb B pin voltage Hb Ib B pin current (standby) 0 V < B < 18 V, Vs-tby < 1.5 V -5 0 5 A Ib B pin current (operative) B < 18 V, Vst-by > 3.5 V 7 11 15 A TW Thermal warning - - 150 - °C TPI Thermal protection intervention - - 170 - °C -15 0 15 A ICDH Clip pin high leakage current CD off, 0 V < VCD < 5.5 V ICDL Clip pin low sink current CD on; VCD < 300 mV CD Clip detect THD level 1 mA D0 (IB1) = 0 0.8 1.3 2.5 % D0 (IB1) = 1 5 10 15 % (*) Standby pin high enables I2C bus; Standby pin low puts the device in standby condition. (see “prog” for more details) 8/32 Doc ID 14103 Rev 3 TDA7575B Table 4. Symbol Electrical specifications Electrical characteristics (continued) Parameter Test condition Min. Typ. Max. Unit - - 1.2 V Vs -0.9 - - V Turn-on diagnostics (Power amplifier mode) Pgnd Pvs Short to GND det. (below this Power amplifier in standby limit, the output is considered in condition short circuit to GND) Short to Vs det. (above this limit, the output is considered in short circuit to VS) Normal operation thresholds.(within these limits, the output is considered without faults). - 1.8 - Vs -1.5 V Lsc Shorted load det. - - - 0.5 Lop Open load det. - 130 - - Lnop Normal load det. - 1.5 - 70 Pnop Turn-on diagnostics (Line driver mode) Pgnd Short to GND det. (below this limit, the output is considered in short circuit to GND) - - 1.2 V Pvs Short to Vs det. (above this limit, the Output is considered in Short Circuit to VS) Vs -0.9 - - V Pnop Normal operation thresholds.(within these limits, the output is considered without faults). 1.8 - Vs -1.5 V - - 1.5 Power amplifier in standby Lsc Shorted load det. Lop Open load det. 400 - - Lnop Normal load det. 4.5 - 200 - - 1.2 V Permanent diagnostics (Power amplifier mode or line driver mode) Pgnd Short to GND det. (below this Power amplifier in Mute or Play limit, the output is considered in condition, one or more short short circuit to GND) circuits protection activated Pvs Short to Vs det. (above this limit, the Output is considered in Short Circuit to VS) - Vs 0.9 - - V Pnop Normal operation thresholds.(Within these limits, the Output is considered without faults). - 1.8 - Vs -1.5 V Pow. amp. mode - - 0.5 Line driver mode - - 1.5 Lsc Shorted load det. Doc ID 14103 Rev 3 9/32 Electrical specifications Table 4. TDA7575B Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit VO Offset detection Power amplifier in play condition AC input signals = 0 ±1.5 ±2 ±2.5 V INLH Normal load current detection VO < (VS - 5)pk IB2 (D0) = 0 500 - - mA INLL Normal load current detection VO < (VS - 5)pk IB2 (D0) = 1 250 - - mA IOLH Open load current detection VO < (VS - 5)pk IB2 (D0) = 0 - - 250 mA IOLL Open load current detection VO < (VS - 5)pk IB2 (D0) =1 - - 125 mA 2 I C bus interface fSCL Clock frequency - - - 400 kHz VIL Input low voltage - - - 1.5 V VIH Input high voltage - 2.3 - - V 1. Saturated sqare wave output. 10/32 Doc ID 14103 Rev 3 TDA7575B Electrical characteristics curves 3 Electrical characteristics curves Figure 3. Quiescent drain current vs. supply voltage Figure 4. Id (mA) Po (W) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 160 150 Vi=0 NO LOADS 140 130 120 110 100 90 80 70 8 Output power vs. supply voltage 10 12 14 16 18 Po-max RL=4 Ohm f=1 KHz THD=10% THD=1% 8 9 10 11 12 Vs (V) Figure 5. Output power vs. supply voltage Figure 6. Po (W) 130 120 110 100 90 80 70 60 50 40 30 20 10 0 Po-max THD=10% THD=1% 9 Figure 7. 10 11 12 13 Vs (V) 14 15 16 17 18 Distortion vs. output power 16 17 18 Output power vs. supply voltage Po-max RL=2 Ohm f=1 KHz THD=10% THD=1% 8 9 Figure 8. THD (%) 10 15 Po (W) 130 120 110 100 90 80 70 60 50 40 30 20 10 0 RL=2 Ohm f=1 KHz 8 13 14 Vs (V) 10 11 12 13 Vs (V) 14 15 16 17 18 Distortion vs. output power THD (%) 10 HI-EFF mode Vs=14.4V RL=2 Ohm HI-EFF mode Vs=14.4V RL=4 Ohm 1 1 f=10 KHz f=10 KHz 0.1 0.1 f=1 KHz f=1 KHz 0.01 0.01 0.1 1 10 100 0.1 Po (W) Doc ID 14103 Rev 3 1 Po (W) 10 100 11/32 Electrical characteristics curves Figure 9. TDA7575B Distortion vs. output power Figure 10. Distortion vs. output power THD (%) THD (%) 10 10 STD mode Vs=14.4V RL=4 Ohm 1 STD mode Vs=14.4V RL=2 Ohm 1 f=10 KHz f=10 KHz 0.1 0.1 f=1 KHz f=1 KHz 0.01 0.01 0.001 0.001 0.1 1 10 100 0.1 1 Po (W) Figure 11. Distortion vs. output power 100 Figure 12. Distortion vs. frequency THD (%) THD (%) 10 10 Po (W) 10 STD mode Vs=14.4V RL=1 Ohm Vs=14.4V STD mode 1 1 1Ω - 40W 2Ω - 24W 4Ω - 12W f=10 KHz 0.1 0.1 0.01 f=1 KHz 0.01 0.001 0.1 1 10 100 10 100 Po (W) Figure 13. Distortion vs. output voltage (LD mode) THD (%) 10000 100000 Figure 14. Cross talk vs. frequency CROSSTALK (dB) -20 10 LD mode Vs=14.4V RL=100 Ohm 1 1000 f (Hz) -30 STD mode RL=2 Ohm Rg=600 Ohm -40 -50 -60 0.1 -70 f=10 KHz 0.01 -80 -90 f=1 KHz 0.001 -100 0 1 2 3 4 5 6 7 8 9 10 11 12 10 Vout 12/32 100 1000 f (Hz) Doc ID 14103 Rev 3 10000 100000 TDA7575B Electrical characteristics curves Figure 15. Cross talk vs. frequency (LD mode) Figure 16. CMRRR vs. frequency CMRR (dB) CROSSTALK (dB) -20 -40 -30 LD mode Vo=1 Vrms RL=100 Ohm -40 Vcm=1 Vpp -50 -50 -60 -70 -60 -80 -90 -70 -100 10 100 1000 10000 10 100000 100 1000 f (Hz) f (Hz) Figure 17. Output attenuation vs. supply voltage (vs. dependent muting) 10000 100000 Figure 18. Output attenuation vs. mute pin voltage OUT ATTN (dB) OUT ATTN (dB) 20 20 0 dB=1 Vrms RL=2 Ohm 0 0 dB=2 Vrms RL=2 Ohm 0 -20 -20 -40 -40 -60 -60 -80 -80 -100 -100 -120 5 6 7 8 9 1 10 1.5 2 Vs (V) 2.5 3 3.5 4 MUTE PIN V (V) Figure 19. Power dissipation vs. output power Figure 20. Power dissipation vs. output power (4 - SINE) (2 - SINE) Ptot (W) Ptot (W) 35 60 Vs=14.4V RL=2 x 4 Ohm f=1 KHz 30 25 Vs=14.4V RL:=2 x 2 Ohm f=1 KHz 50 40 STD STD 20 30 15 20 10 HI-EFF HI-EFF 10 5 0 0 0.1 1 10 100 0.1 Po (W) 1 10 100 Po (W) Doc ID 14103 Rev 3 13/32 Electrical characteristics curves TDA7575B Figure 21. Power dissipation vs. average output power (Audio program simulation, 4) Figure 22. Power dissipation vs. average output power (Audio program simulation, 2) Ptot (W) Ptot (W) 30 35 Vs=14 V RL=2 x 4 GAUSSIAN NOISE 25 Vs=14V RL=2 x 2 Ohm GAUSSIAN NOISE 30 20 START CLIP START 20 15 HI-EFF 15 STD 10 10 5 HI-EFF 5 0 0 0 1 2 3 4 5 0 Figure 23. ITU R-ARM frequency response, weighting filter for transient pop Output attenuation (dB) 10 0 -10 -20 -30 -40 -50 100 1000 Hz 14/32 1 2 3 4 5 Po (W) Po (W) 10 STD 25 CLIP 10000 100000 AC00343 Doc ID 14103 Rev 3 6 7 8 9 10 TDA7575B 4 Application circuits Application circuits Figure 24. Application circuit (TDA7575B) VS I2C BUS A B CLK CD_OUT DATA C8 2200μF C7 0.1μF R1 47KΩ V VCC 25 3 14 13 7-21 16 C1 0.22μF IN1+ 8 OUT1+ 4 IN1- 9 6 IN2+ 20 24 IN2- 19 OUT1- C2 0.22μF C3 0.22μF OUT2+ 22 OUT2- C4 0.22μF 11 15 12 1 2-26 PW_GND S_GND TAB MUTE C5 10μF C6 1μF ST-BY/HE D05AU1615 I2C BUS ENABLE 18 10 17 R2 47KΩ 1Ω SETTING Figure 25. Application circuit (TDA7575BPD) VS I2C BUS A B CLK CD_OUT DATA C8 2200μF C7 0.1μF R1 47KΩ V VCC 23 32 8 7 21-2-33-34 14 C1 0.22μF IN1+ 2 IN1- 3 28-29 IN2+ 18 19-20 IN2- 17 OUT1+ 35-36 OUT1- C2 0.22μF C3 0.22μF OUT2+ 26-29 OUT2- C4 0.22μF 13 5 6 24-25-30-31 S_GND PW_GND C5 10μF D05AU1616 1 TAB MUTE C6 1μF ST-BY/HE Doc ID 14103 Rev 3 I2C BUS ENABLE 16 4 15 R2 47KΩ 1Ω SETTING 15/32 I2C bus interface 5 TDA7575B I2C bus interface Data transmission from microprocessor to the TDA7575B and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 5.1 Data validity As shown by Figure 26, the data on the SDA line must be stable during the high period of the clock. The high and low state of the data line can only change when the clock signal on the SCL line is low. 5.2 Start and stop conditions As shown by Figure 27 a start condition is a high to low transition of the SDA line while SCL is high. The stop condItion Is A Low To High Transition of the SDA line while SCL is high. 5.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 5.4 Acknowledge The transmitter(*) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see Figure 28). The receiver(**) the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. (*) Transmitter = master (P) when it writes an address to the TDA7575B = slave (TDA7575B) when the µP reads a data byte from TDA7575B (**) Receiver = slave (TDA7575B) when the µP writes an address to the TDA7575B = master (P) when it reads a data byte from TDA7575B Figure 26. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID 16/32 CHANGE DATA ALLOWED Doc ID 14103 Rev 3 D99AU1031 TDA7575B I2C bus interface Figure 27. Timing diagram on the I2C bus SCL I2CBUS SDA D99AU1032 START STOP Figure 28. Timing acknowledge clock pulse SCL 1 2 3 7 8 9 SDA MSB START 5.5 D99AU1033 ACKNOWLEDGMENT FROM RECEIVER 1 capability setting It is possible to drive 1 load paralleling the outputs into a single channel. In order to implement this feature, outputs are to be connected on the board as follows: ● OUT1+ (pin 35 and pin 36) shorted to OUT2+ (pin 19 and pin 20) ● OUT1- (pin 28 and pin 29) shorted to OUT2- (pin 26 and pin 27). It is recommended to minimize the impedance on the board between OUT2 and the load in order to minimize THD distortion. It is also recommended to control the maximum mismatch impedance between VCC pins (pin 21/pin 22 respect to pin 33/pin 34) and between PWGND pins (pin 24/pin 25 respect to pin 30/pin 31), mismatch that must not exceed a value of 20 m With 1 feature settled the active input is IN2 (pin 17 and pin 18), therefore IN1 pins should be let floating. It is possible to set the load capability acting on 1 pin as follows: 1 pin (pin 15) < 1.5 V: two channels mode (for a minimum load of 2 ) 1 pin (pin 15) > 2.5 V: one channel mode (for 1 load). It is to remember that 1 Ohmfunction is a hardware selection. Therefore it is recommended to leave 1pin floating or shorted to GND to set the two channels mode configuration, or to short 1 pin to VCC to set the one channel (1) configuration. Doc ID 14103 Rev 3 17/32 I2C bus interface 5.6 TDA7575B I2C abilitation setting It is possible to disable the I2C interface by acting on I2C pin (pin 16) and control the TDA7575B by means of the usual standby and mute pins. In order to activate or deactivate this feature, I2C pin must be set as follows: ● I2C pin (pin 16) < 1.5V: I2C bus interface deactivated ● I2C pin (pin 16) > 2.5V: I2C bus interface activated It is also possible to let I2C pin floating to deactivate the I2C bus interface, or to short I2C pin to VCC to activate it. In particular: ● I2C enabled: I2C pin (pin 16) > 2.5 V – STD mode: Vst-by (pin 5) > 3.5 V, IB2(D1)=0 – HE mode: Vst-by (pin 5) > 3.5 V, IB2(D1)=1 – Play mode: Vmute (pin 4) >3.5 V, IB1 (D2) = 1 The amplifier can always be switched off by putting Vst-by to 0V , but with I2C enabled it can be turn on only through I2C (with Vst-by > 3.5 V). ● I2C disabled: I2C pin (pin 16) < 1.5 V – STD mode: 3.5V < standby (pin 5) < 5 – HE mode: Vstby (pin 5) > 7 V – Play mode: Vmute (pin 4) > 3.5 V For both STD and HE mode the play/mute mode can be set acting on Vmute pin. When I2C bus is disabled, when a fault is detected pin 14 (CD-OUT) is pulled down by the internal logic circuitry. The faults detected are the short circuit to ground, to VCC and across the load (after an aver current detection). 18/32 Doc ID 14103 Rev 3 TDA7575B 6 Software specifications Software specifications All the functions of the TDA7575B are activated by I2C interface. The bit 0 of the "Address Byte" defines if the next bytes are write instruction (from P to TDA7575B) or read instruction (from TDA7575B to µP). Table 5. Address selection Bit Address A6 1 A5 1 A4 0 A3 1 A2 0 A1 B A0 A R/W X If R/W = 0, the P sends 2 "instruction bytes": IB1 and IB2. Table 6. IB1 Bit Instruction decoding bit D7 0 D6 Diagnostic enable (D6 = 1) Diagnostic defeat (D6 = 0) D5 Offset detection enable (D5 = 1) Offset detection defeat (D5 = 0) D4 Gain = 26 dB (D4 = 0) Gain = 12 dB (D4 = 1) D3 0 D2 Mute (D2 = 0) Unmute (D2 = 1) D1 0 D0 CD 2% (D0 = 0) CD 10% (D0 = 1) Doc ID 14103 Rev 3 19/32 Software specifications Table 7. TDA7575B IB2 Bit Instruction decoding bit D7 0 D6 0 D5 0 D4 Standby on - Amplifier not working - (D4 = 0) Standby off - Amplifier working - (D4 = 1) D3 Power amplifier mode diagnostic (D3 = 0); Line driver mode diagnostic (D3 = 1) D2 Current detection diagnostic enabled (D2 = 1) Current detection diagnostic defeat (D2 = 0) D1 Power amplifier working in standard mode (D1 = 0) Power amplifier working in high efficiency mode (D1 = 1) D0 Current detection threshold high (D7 =0) Current detection threshold low (D7 =1) If R/W = 1, the TDA7575B sends 2 "Diagnostics Bytes" to P: DB1 and DB2. Table 8. DB1 Bit Instruction decoding bit D7 Thermal warming (if Tchip 150°C, D7 = 1) D6 Diag. cycle not activated or not terminated (D6 = 0) Diag. cycle terminated (D6 = 1) D5 Channel 1 current detection IB2 (D0) = 0 Output peak current < 250 mA - Open load (D5 = 1) Output peak current > 500 mA - Normal load (D5 = 0) D4 Channel 1 Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) D3 Channel 1 Normal load (D3 = 0) Short load (D3 = 1) D2 Channel 1 Turn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Offset diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) D1 Channel 1 No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) D0 Channel 1 No short to GND (D1 = 0) Short to GND (D1 = 1) 20/32 Channel LF current detection IB2 (D0) = 1 Output peak current < 125 mA - Open load (D5 = 1) Output peak current > 250 mA - Normal load (D5 = 0) Doc ID 14103 Rev 3 TDA7575B Table 9. Software specifications DB2 Bit Instruction decoding bit D7 Offset detection not activated (D7 = 0) Offset detection activated (D7 = 1) D6 Current sensor not activated (D6 = 0) Current sensor activated (D6 = 1) D5 Channel LR Current detection IB2 (D0) = 0 Output peak current < 250 mA - Open load (D5 = 1) Output peak current > 500 mA - Normal load (D5 = 0) D4 Channel 2 Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) D3 Channel 2 Normal load (D3 = 0) Short load (D3 = 1) D2 Channel 2 Turn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) D1 Channel 2 No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) D0 Channel 2 No short to GND (D1 = 0) Short to GND (D1 = 1) Channel LR Current detection IB2 (D0) = 1 Output peak current < TBD mA - Open load (D5 = 1) Output peak current > TBD mA - Normal load (D5 = 0) Doc ID 14103 Rev 3 21/32 Software specifications 6.1 TDA7575B Examples of bytes sequence 1 - Turn-on diagnostic - Write operation Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP L 2 - Turn-on diagnostic - Read operation Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK STOP The delay from 1 to 2 can be selected by software, starting from T.B.D. ms 3a - Turn-on of the power amplifier with mute on, diagnostic defeat. Start Address byte with D0 = 0 ACK IB1 ACK X000XXXX IB2 ACK STOP ACK STOP ACK STOP XXX1XX1X 3b - Turn-off of the power amplifier Start Address byte with D0 = 0 ACK IB1 ACK X0XXXXXX IB2 XXX0XXXX 4 - Offset detection procedure enable Start Address byte with D0 = 0 ACK IB1 ACK XX1XX1XX IB2 XXX1XXXX 5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4). Start 22/32 Address byte with D0 = 1 ACK DB1 ACK DB2 ACK STOP ● The purpose of this test is to check if a D.C. offset (2 V typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins. ● The delay from 4 to 5 can be selected by software, starting from T.B.D. ms Doc ID 14103 Rev 3 TDA7575B Diagnostics functional description 7 Diagnostics functional description 7.1 Turn-on diagnostic It is activated at the turn-on (stand-by out) under I2C bus request. Detectable output faults are: – Short to GND – Short TO Vs – Short across the speaker – Open speaker To verify if any of the above misconnections are in place, a subsonic (inaudible) current pulse (Figure 29) is internally generated, sent through the speaker(s) and sunk back. The Turn On diagnostic status is internally stored until a successive diagnostic pulse is requested (after a I2C reading). If the "stand-by out" and "diag. enable" commands are both given through a single programming step, the pulse takes place first (power stage still in stand-by mode, low, outputs = high impedance). Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The previous Turn On state is kept until a short appears at the outputs. Figure 29. Turn-on diagnostic: working principle I (mA) Vs~5V Isource Isource CH+ Isink CHIsink ~100mS t (ms) Measure time Fig. Figure 30 and Figure 31 show SVR and OUTPUT waveforms at the turn-on (stand-by out) with and without Turn-on diagnostic. Figure 30. SVR and output behavior - case 1: without turn-on diagnostic Vsvr Out Permanent diagnostic acquisition time (100mS Typ) Bias (power amp turn-on) I2CB DATA Diagnostic Enable (Permanent) t FAULT event Read Data Permanent Diagnostics data (output) permitted time Doc ID 14103 Rev 3 23/32 Diagnostics functional description TDA7575B Figure 31. SVR and output pin behavior - case 2: with turn-on diagnostic Vsvr Out Turn-on diagnostic acquisition time (100mS Typ) Diagnostic Enable (Turn-on) Permanent diagnostic acquisition time (100mS Typ) Turn-on Diagnostics data (output) permitted time Bias (power amp turn-on) permitted time I2CB DATA FAULT event Diagnostic Enable (Permanent) Read Data t Permanent Diagnostics data (output) permitted time The information related to the outputs status is read and memorized at the end of the current pulse top. The acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for short to GND / Vs the fault-detection thresholds remain unchanged from 26 dB to 12 dB gain setting. They are as follows: Figure 32. Short circuit detection thresholds S.C. to GND 0V x 1.2V Normal Operation 1.8V x VS-1.5V S.C. to Vs VS-0.9V D02AU1341 VS Concerning short across the speaker / open speaker, the threshold varies from 26 dB to 12 dB gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The values in case of 26 dB gain are as follows: Figure 33. Load detection thresholds - high gain setting S.C. across Load 0V x 0.5Ω Normal Operation 1.5Ω x Open Load 130Ω 70Ω Infinite D01AU1254 If the line-driver mode (Gv= 12 dB and line driver mode diagnostic = 1) is selected, the same thresholds will change as follows: Figure 34. Load detection thresholds - high gain setting S.C. across Load 0Ω 1.5Ω x Normal Operation 4.5Ω 200Ω x Open Load 400Ω infinite D01AU1252 24/32 Doc ID 14103 Rev 3 TDA7575B 7.2 Diagnostics functional description Permanent diagnostics Detectable conventional faults are: – Short to GND – Short to Vs – Short across the speaker The following additional features are provided: – Output offset detection The TDA7575B has 2 operating statuses: 1. RESTART mode. The diagnostic is not enabled. Each audio channel operates independently from each other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output status is made every 1 ms (fig. 30). Restart takes place when the overload is removed. 2. DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload (such to cause the intervention of the short-circuit protection) occurs to the speakers outputs. Once activated, the diagnostics procedure develops as follows (fig. 31): – To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output status is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and the channel returns back active. – Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration of about 100 ms is started. – After a diagnostic cycle, the audio channel interested by the fault is switched to RESTART mode. The relevant data are stored inside the device and can be read by the microprocessor. When one cycle has terminated, the next one is activated by an I2C reading. This is to ensure continuous diagnostics throughout the carradio operating time. – To check the status of the device a sampling system is needed. The timing is chosen at microprocessor level (over than half a second is recommended). Figure 35. Restart timing without diagnostic enable (permanent) each 1ms time, a sampling of the fault is done Out 1mS 1-2mS 1mS 1mS 1mS t Overcurrent and short circuit protection intervention (i.e. short circuit to GND) Short circuit removed Figure 36. Restart timing with diagnostic enable (permanent) 1mS 100mS 1mS 1mS t Overcurrent and short circuit protection intervention (i.e. short circuit to GND) Short circuit removed Doc ID 14103 Rev 3 25/32 Diagnostics functional description 7.3 TDA7575B Output DC offset detection Any DC output offset exceeding ± 2 V are signalled out. This inconvenient might occur as a consequence of initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the speakers at risk of overheating. This diagnostic has to be performed with low-level output AC signal (or Vin = 0). The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command): ● Start = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1 ● Stop = Actual reading operation Excess offset is signalled out if persistent throughout the assigned testing time. This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process. 7.4 AC diagnostic It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more in general, presence of capacitively (AC) coupled loads. This diagnostic is based on the notion that the overall speaker's impedance (woofer + parallel tweeter) will tend to increase towards high frequencies if the tweeter gets disconnected, because the remaining speaker (woofer) would be out of its operating range (high impedance). The diagnostic decision is made according to peak output current thresholds, and it is enabled by setting (IB2-D2) = 1. Two different detection levels are available: ● ● HIgh current threshold IB2 (D7) = 0 – Iout > 500 mApk = normal status – Iout < 250 mApk = open tweeter Low current threshold IB2 (D7) = 1 – Iout > 250 mApk = normal status – Iout < 125 mApk = open tweeter To correctly implement this feature, it is necessary to briefly provide a signal tone (with the amplifier in "play") whose frequency and magnitude are such to determine an output current higher than 500mApk with IB2(D7)=0 (higher than 250mApk with IB2(D7)=1) in normal conditions and lower than 250 mApk with IB2(D7)=0 (lower than 125 mApk with IB2(D7)=1) should the parallel tweeter be missing. The test has to last for a minimum number of 3 sine cycles starting from the activation of the AC diagnostic function IB2<D2>) up to the I2C reading of the results (measuring period). To confirm presence of tweeter, it is necessary to find at least 3 current pulses over the above threholds over all the measuring period, else an "open tweeter" message will be issued. The frequency / magnitude setting of the test tone depends on the impedance characteristics of each specific speaker being used, with or without the tweeter connected (to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals are recommended for their negligible acoustic impact and also to maximize the impedance module's ratio between with tweeter-on and tweeter-off. 26/32 Doc ID 14103 Rev 3 TDA7575B Diagnostics functional description Figure 37 shows the load impedance as a function of the peak output voltage and the relevant diagnostic fields. This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process. Figure 37. Current detection high: load impedance |Z| vs. output peak voltage Load |z| (Ohm) 50 Iout (peak) <250mA 30 20 Low current detection area (Open load) D5 = 1 of the DBx byres Iout (peak) >500mA 10 IB2(D0) = 0 High current detection area (Normal load) D5 = 0 of the DBx bytes 5 3 2 1 1 2 3 4 5 6 7 8 Vout (Peak) Figure 38. Current detection low: load impedance |Z| vs. output peak voltage Load |z| (Ohm) 50 Iout (peak) <125mA 30 20 Low current detection area (Open load) D5 = 1 of the DBx byres Iout (peak) >250mA 10 IB2(D0) = 1 High current detection area (Normal load) D5 = 0 of the DBx bytes 5 3 2 1 0.5 1 1.5 2 2.5 3 3.5 4 Vout (Peak) 7.5 Multiple faults When more misconnections are simultaneously in place at the audio outputs, it is guaranteed that at least one of them is initially read out. The others are notified after successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled. This is true for both kinds of diagnostic (turn-on and permanent). The table below shows all the couples of double-fault possible. It should be taken into account that a short circuit with the 4 speaker unconnected is considered as double fault. Doc ID 14103 Rev 3 27/32 Diagnostics functional description Table 10. TDA7575B Double fault table for turn-on diagnostic S. GND (sc) S. GND (sk) S. Vs S. Across L. Open L. S. GND (sc) S. GND S. GND S. Vs + S. GND S. GND S. GND S. GND (sk) / S. GND S. Vs S. GND Open L. (*) S. Vs / / S. Vs S. Vs S. Vs S. Across L. / / / S. Across L. N.A. Open L. / / / / Open L. (*) S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2 outputs is shorted to ground (test-current source side= so, test-current sink side = sk). More precisely, in both the channels SO = CH+, and SK = CH-. In permanent diagnostic the table is the same, with only a difference concerning open load (*), which is not among the recognizable faults. Should an open load be present during the device's normal working, it would be detected at a subsequent turn-on diagnostic cycle (i.e. at the successive car radio turn-on). 7.6 Faults availability All the results coming from I2C bus, by read operations, are the consequence of measurements inside a defined period of time. If the fault is stable throughout the whole period, it will be sent out. This is true for DC diagnostic (turn-on and permanent), for offset detector. To guarantee always resident functions, every kind of diagnostic cycles (turn-on, permanent, offset) will be reactivate after any I2C reading operation. So, when the micro reads the I2C, a new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e. The device is in turn-on state, with a short to GND, then the short is removed and micro reads I2C. The short to GND is still present in bytes, because it is the result of the previous cycle. If another I2C reading operation occurs, the bytes do not show the short). In general to observe a change in diagnostic bytes, two I2C reading operations are necessary. 7.7 I2C programming/reading sequences A correct turn on/off sequence respectful of the diagnostic timings and producing no audible noises could be as follows (after battery connection): ● Turn-on: (Standby OUT + DIAG enable) --- 500 ms (min) --- muting OUT ● Turn-off: Muting IN --- 20 ms --- (DIAG disable + standby IN) Car radio installation: DIAG enable (write) --- 20 0ms --- I2C read (repeat until all faults disappear). – Offset test: device in play (no signal) – Offset enable - 30 ms - I2C reading (repeat I2C reading until high-offset message disappears). 28/32 Doc ID 14103 Rev 3 TDA7575B 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 39. PowerSO36 (slug up) mechanical data and package dimensions DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s MIN. 3.270 3.100 0.800 0.030 0.220 0.230 15.800 9.400 13.900 10.900 5.800 2.900 0 15.500 0.800 - mm TYP. 0.200 1.000 0.650 11.050 - MAX. 3.410 3.180 1.000 -0.040 0.380 0.320 16.000 9.800 14.500 11.100 2.900 6.200 3.200 0.075 15.900 1.100 1.100 10˚ 8˚ MIN. 0.1287 0.1220 0.0315 0.0012 0.0087 0.0091 0.6220 0.3701 0.5472 0.4291 0.2283 0.1142 0 0.6102 0.0315 - inch TYP. 0.0079 0.0394 0.0256 0.4350 - MAX. 0.1343 0.1252 0.0394 -0.0016 0.0150 0.0126 0.6299 0.3858 0.5709 0.4370 0.1142 0.2441 0.1260 0.0031 0.6260 0.0433 0.0433 10˚ 8˚ OUTLINE AND MECHANICAL DATA PowerSO36 (SLUG UP) (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”). (2) No intrusion allowed inwards the leads. 7183931 G Doc ID 14103 Rev 3 29/32 Package information TDA7575B Figure 40. Flexiwatt27 (vertical) mechanical data and package dimensions DIM. MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 0.031 1.014 1.139 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N L3 R L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 30/32 Doc ID 14103 Rev 3 TDA7575B 9 Revision history Revision history Table 11. Document revision history Date Revision Changes 30-Oct-2007 1 Initial release. 17-Dec-2009 2 Updated Figure 39: PowerSO36 (slug up) mechanical data and package dimensions on page 29. 17-Sep-2013 3 Updated Disclaimer. Doc ID 14103 Rev 3 31/32 TDA7575B Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 32/32 Doc ID 14103 Rev 3