TDA7561 MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DMOS POWER OUTPUT HIGH OUTPUT POWER CAPABILITY 4x25W/ 4W @ 14.4V, 1KHZ, 10% THD, 4x35W EIAJ MAX. OUTPUT POWER 4x60W/2W FULL I2C BUS DRIVING: – ST-BY – INDEPENDENT FRONT/REAR SOFT PLAY/ MUTE – SELECTABLE GAIN 26dB - 12dB (FOR LOW NOISE LINE OUTPUT FUNCTION) – I2C BUS DIGITAL DIAGNOSTICS FULL FAULT PROTECTION DC OFFSET DETECTION FOUR INDEPENDENT SHORT CIRCUIT PROTECTION CLIPPING DETECTOR ESD PROTECTION MULTIPOWER BCD TECHNOLOGY MOSFET OUTPUT POWER STAGE FLEXIWATT25 package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7561 has a very low distortion allowing a clear powerful sound.This device is equipped with a full diagnostics array that communicates the status of each speaker through the I2C bus.The possibility to control the configuration and behaviour of the device by means of the I2C bus makes TDA7561 a very flexible machine. DESCRIPTION The TDA7561 is a new BCD technology QUAD BRIDGE type of car radio amplifier in Flexiwatt25 BLOCK DIAGRAM CLK REFERENCE IN RF THERMAL PROTECTION & DUMP VCC1 DATA VCC2 I2C BUS CD_OUT CLIP DETECTOR MUTE1 MUTE2 F OUT RF+ 12/26dB OUT RF- IN RR SHORT CIRCUIT PROTECTION & DIAGNOSTIC R OUT RR+ 12/26dB OUT RR- IN LF SHORT CIRCUIT PROTECTION & DIAGNOSTIC F OUT LF+ 12/26dB OUT LF- IN LR SHORT CIRCUIT PROTECTION & DIAGNOSTIC R OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION & DIAGNOSTIC SVR D00AU1229 December 2002 AC_GND RF RR LF LR TAB S_GND PW_GND 1/19 TDA7561 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vop Operating Supply Voltage 18 V VS DC Supply Voltage 28 V Peak Supply Voltage (for t = 50ms) 50 V CK pin Voltage 6 V Data Pin Voltage 6 V IO Output Peak Current (not repetitive t = 100ms) 8 A IO Output Peak Current (repetitive f > 10Hz) 6 A 85 W -55 to 150 °C Value Unit 1 °C Vpeak VCK VDATA Ptot Tstg, Tj Power Dissipation Tcase = 70°C Storage and Junction Temperature THERMAL DATA Symbol Rth j-case Parameter Thermal Resistance Junction to case Max. PIN CONNECTION 25 DATA 24 PW_GND RR 23 OUT RR- 22 CK OUT RR+ 20 VCC2 19 OUT RF- 18 PW_GND RF 17 OUT RF+ 16 AC GND 15 IN RF 14 IN RR 13 S GND 12 IN LR 11 IN LF 10 SVR 9 OUT LF+ 8 PW_GND LF 7 OUT LF- 6 VCC1 OUT LR+ 4 CD-OUT 3 OUT LR- 2 PW_GND LR 1 TAB D99AU1037 2/19 TDA7561 Figure 1. Test and Application Circuit C8 0.1µF C7 3300µF Vcc1 Vcc2 6 DATA 20 17 18 25 I2C BUS 19 CLK 22 21 C1 0.22µF IN RF 23 C2 0.22µF 9 14 + OUT RR + 8 C3 0.22µF 7 IN LF OUT RF 24 15 IN RR + 11 5 OUT LF + 2 C4 0.22µF IN LR 12 S-GND 13 3 16 10 4 1 OUT LR TAB 47K C5 1µF C6 10µF V D00AU1212 CD OUT 3/19 TDA7561 ELECTRICAL CHARACTERISTCS (Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz;Tamb = 25°C; unless otherwise specified). Symbol Parameter Test Condition Min. Typ. Max. Unit 18 V 300 mA POWER AMPLIFIER VS Supply Voltage Range Id Total Quiescent Drain Current PO Output Power 8 150 EIAJ (VS = 13.7V) 32 35 W THD = 10% 22 25 W 20 W THD = 1% THD Total Harmonic Distortion CT Cross Talk RIN GV1 RL = 2Ω; EIAJ (VS = 13.7V) 50 55 W RL = 2Ω; THD 10% 32 38 W RL = 2Ω; THD 1% 30 W RL = 2Ω; MAX POWER 60 W PO = 1W to 10W; 0.04 0.1 % GV = 12dB; VO = 0.1 to 5VRMS 0.02 0.05 % 50 60 Input Impedance 80 100 130 KΩ Voltage Gain 1 25 26 27 dB Voltage Gain Match 1 -1 1 dB Voltage Gain 2 11 13 dB ∆GV2 Voltage Gain Match 2 -1 1 dB EIN1 Output Noise Voltage 1 Rg = 600Ω, 20Hz to 22kHz 35 80 µV EIN2 Output Noise Voltage 2 Rg = 600Ω; GV = 12dB 20Hz to 22kHz 12 20 µV SVR Supply Voltage Rejection f = 100Hz to 10kHz; Vr = 1Vpk; Rg = 600Ω BW Power Bandwidth 100 ASB Stand-by Attenuation 90 ISB Stand-by Current AM Mute Attenuation VOS Offset Voltage VAM Min. Supply Mute Threshold TON Turn on Delay TOFF Turn off Delay ∆GV1 GV2 4/19 f = 1KHz to 10KHz, RG = 600Ω 50 12 dB 60 dB KHz 110 25 dB 100 µA 80 100 -100 0 100 mV 7 7.5 8 V D2/D1 (IB1) 0 to 1 20 40 ms D2/D1 (IB1) 1 to 0 20 40 ms Mute & Play dB TDA7561 ELECTRICAL CHARACTERISTCS (continued) (Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz;Tamb = 25°C; unless otherwise specified). Symbol Parameter Test Condition CDLK Clip Det High Leakage Current CD off CDSAT Clip Det Sat. Voltage CD on; ICD = 1mA CDTHD Clip Det THD level Min. Typ. Max. Unit 0 15 µA 150 300 mV 1 2 % 1.2 V TURN ON DIAGNOSTICS 1 (Power Amplifier Mode) Pgnd Short to GND det. (below this limit, the Output is considered in Short Circuit to GND) Pvs Short to Vs det. (above this limit, the Output isconsidered in Short Circuit to VS) Pnop Power Amplifier in st-by condition Vs -1.2 Normal operation thresholds. (Within these limits, the Output is considered without faults). 1.8 Lsc Shorted Load det. Lop Open Load det. 130 Lnop Normal Load det. 1.5 V Vs -1.8 V 0.5 Ω Ω 70 Ω 1.2 V TURN ON DIAGNOSTICS 2 (Line Driver Mode) Pgnd Short to GND det. (below this limit, the Output is considered in Short Circuit to GND) Pvs Short to Vs det. (above this limit, the Output isconsidered in Short Circuit to VS) Vs -1.2 Pnop Normal operation thresholds. (Within these limits, the Output is considered without faults). 1.8 Power Amplifier in st-by Lsc Shorted Load det. Lop Open Load det. 400 Lnop Normal Load det. 4.5 V Vs -1.8 V 1.5 & & 200 & 1.2 V PERMANENT DIAGNOSTICS 2 (Power Amplifier Mode or Line Driver Mode) Pgnd Short to GND det. (below this limit, the Output is considered in Short Circuit to GND) Power Amplifier in Mute or Play, one or more short circuits protection activated Pvs Short to Vs det. (above this limit, the Output is considered in Short Circuit to VS) Vs -1.2 Pnop Normal operation thresholds. (Within these limits, the Output is considered without faults) 1.8 V Vs -1.8 V 5/19 TDA7561 ELECTRICAL CHARACTERISTCS (continued) (Refer to the test circuit, VS = 14.4V; RL = 4Ω; f = 1KHz;Tamb = 25°C; unless otherwise specified). Symbol LSC Parameter Test Condition Shorted Load det. Offset Detection VO Min. Max. Unit Power Amplifier mode 0.5 Ω Line Driver mode 1.5 Ω 2.5 V Power Amplifier in play, AC Input signals = 0 Typ. 1.5 2 I2C BUS INTERFACE fSCL Clock Frequency VIL Input Low Voltage VIH Input High Voltage 400 1.5 V Figure 4. Output Power vs. Supply Voltage (4Ω) Po (W) Id (mA) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 250 230 Vin = 0 NO LOADS 190 170 150 130 110 90 70 50 8 V 2.3 Figure 2. Quiescent Current vs. Supply Voltage 210 KHz 10 12 Vs (V) 14 16 18 Figure 3. Output Power vs. Supply Voltage (2Ω) Po-max RL = 2 Ohm f = 1 KHz THD= 10 % THD= 1 % 8 9 10 11 12 Vs (V) 13 14 15 Figure 5. Distortion vs. Output Power (2Ω) THD (%) Po (W) 10 70 65 60 Po-max 55 Vs = 14.4 V RL = 4 Ohm RL = 4 Ohm f = 1 KHz 50 1 45 THD= 10 % 40 35 f = 10 KHz 30 0.1 25 20 f = 1 KHz THD= 1 % 15 10 5 8 6/19 9 10 11 12 13 Vs (V) 14 15 16 17 18 0.01 0.1 1 10 Po (W) 16 TDA7561 Figure 6. Distortion vs. Output Power (2Ω) Figure 9. Crosstalk vs. Frequency THD (%) CROSSTALK (dB) 10 90 80 Vs = 14.4 V RL = 2 Ohm 70 1 60 Vs = 14.4 V RL = 4 Ohm Po = 4 W Rg = 600 Ohm f = 10 KHz 50 f = 1 KHz 0.1 40 30 0.01 0.1 1 20 10 10 100 f (Hz) Po (W) 1000 10000 Figure 10. Supply Voltage Rejection vs.Frequency Figure 7. Distortion vs. Frequency (4Ω) THD (%) SVR (dB) 10 90 80 Vs = 14.4 V RL = 4 Ohm Po = 4 W 70 1 60 50 0.1 Rg = 600 Ohm Vripple = 1 Vpk 40 30 0.01 10 100 f (Hz) 1000 10000 20 10 100 f (Hz) 1000 10000 Figure 11. Power Dissipation & Efficiency vs.Output Power (4Ω, SINE) Figure 8. Distortion vs. Frequency (2Ω) n (%) Ptot (W) THD (%) 90 90 10 80 Vs = 14.4 V RL = 2 Ohm Po = 8 W 70 1 80 n Vs = 14.4 V RL = 4x4 Ohm f= 1 KHz SINE 70 60 60 50 50 Ptot 0.1 0.01 10 100 1000 f (Hz) 10000 40 40 30 30 20 20 10 10 0 0 2 4 6 8 10 12 14 Po (W) 16 18 20 22 24 0 26 7/19 TDA7561 Figure 13. Power Dissipation vs. Average Ouput Power (Audio Program Simulation, 2Ω) Figure 12. Power Dissipation vs. Average Ouput Power (Audio Program Simulation, 4Ω) Ptot (W) Ptot (W) 45 90 40 80 Vs = 14.4 V RL = 4x4 Ohm GAUSSIAN NOISE 35 Vs = 14.4 V RL = 4x2 Ohm GAUSSIAN NOISE 70 CLIP START 30 60 CLIP START 50 25 40 20 30 15 20 10 10 0 5 0 1 2 3 4 5 0 1 2 3 Po (W) 4 Po (W) 5 6 7 8 DIAGNOSTICS FUNCTIONAL DESCRIPTION: a) TURN-ON DIAGNOSTIC. It is activated at the turn-on (stand-by out) under I2Cbus request. Detectable output faults are: - SHORT TO GND - SHORT TO Vs - SHORT ACROSS THE SPEAKER - OPEN SPEAKER To verify if any of the above misconnections are in place, a subsonic (inaudible) current pulse (fig. 14) is internally generated, sent through the speaker(s) and sunk back.The Turn On diagnostic status is internally stored until a successive diagnostic pulse is requested (after a I2C reading). If the "stand-by out" and "diag. enable" commands are both given through a single programming step, the pulse takes place first (power stage still in stand-by mode, low, outputs = high impedance). Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The previous Turn On state is kept until a short appears at the outputs. Figure 14. Turn - On diagnostic: working principle Vs~5V Isource I (mA) Isource Isink CH+ CH- Isink ~100ms Measure time 8/19 t (ms) TDA7561 Fig. 15 and 16 show SVR and OUTPUT waveforms at the turn-on (stand-by out) with and without TURN-ON DIAGNOSTIC. Figure 15. SVR and Output behaviour (CASE 1: without turn-on diagnostic) Vsvr Out Permanent diagnostic acquisition time (100mS Typ) t Diagnostic Enable (Permanent) Bias (power amp turn-on) FAULT event Read Data Permanent Diagnostics data (output) permitted time I2CB DATA Figure 16. SVR and Output pin behaviour (CASE 2: with turn-on diagnostic) V s vr Out Tu rn - o n d i a g n o s t ic a c q u is itio n tim e (1 0 0 m S Typ ) P e r m a n e n t d ia g n o s tic a c q u i s itio n tim e (1 0 0 m S Ty p ) t D ia g n o s tic E n a b le (Tu r n -o n ) Tu r n - o n D ia g n o s tic s d a ta (o u t p u t) p e rm itt e d ti m e B ia s (p o w e r a m p t u rn -o n ) p e r m i tte d t im e FA U LT e v e nt D ia g n o s tic E n a b l e (P e rm a n e n t ) R e a d D a ta P e r m a n e n t D ia g n o s t ic s d a ta (o u tp u t ) p e r m itt e d t im e I2 C B D ATA The information related to the outputs status is read and memorized at the end of the current pulse top. The acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for SHORT TO GND / Vs the fault-detection thresholds remain unchanged from 26 dB to 12 dB gain setting. They are as follows: S.C. to GND 0V 1.2V x Normal Operation 1.8V VS-1.8V x S.C. to Vs VS-1.2V D01AU1253 VS 9/19 TDA7561 Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies from 26 dB to 12 dB gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The values in case of 26 dB gain are as follows: S.C. across Load 0V x 0.5Ω Normal Operation 1.5Ω x Open Load 130Ω 70Ω Infinite D01AU1254 If the Line-Driver mode (Gv= 12 dB and Line Driver Mode diagnostic = 1) is selected, the same thresholds will change as follows: S.C. across Load 0Ω 1.5Ω x Normal Operation 4.5Ω 200Ω x Open Load 400Ω infinite D01AU1252 b) PERMANENT DIAGNOSTICS. Detectable conventional faults are: - SHORT TO GND - SHORT TO Vs - SHORT ACROSS THE SPEAKER The following additional features are provided: - OUTPUT OFFSET DETECTION The TDA7561 has 2 operating statuses: 1) RESTART mode. The diagnostic is not enabled. Each audio channel operates independently from each other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output status is made every 1 ms (fig. 17). Restart takes place when the overload is removed. 2) DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload (such to cause the intervention of the short-circuit protection) occurs to the speakers outputs . Once activated, the diagnostics procedure develops as follows (fig. 18): - To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output status is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and the channel returns back active. - Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration of about 100 ms is started. - After a diagnostic cycle, the audio channel interested by the fault is switched to RESTART mode. The relevant data are stored inside the device and can be read by the microprocessor. When one cycle has terminated, the next one is activated by an I2C reading. This is to ensure continuous diagnostics throughout the car-radio operating time. - To check the status of the device a sampling system is needed. The timing is chosen at microprocessor level (over half a second is recommended). 10/19 TDA7561 Figure 17. Restart timing without Diagnostic Enable (Permanent) Each 1mS time, a sampling of the fault is done Out 1-2mS 1mS 1mS 1mS 1mS t Overcurrent and short circuit protection intervention (i.e. short circuit to GND) Short circuit removed Figure 18. Restart timing with Diagnostic Enable (Permanent) 1mS 100mS 1mS 1mS t Overcurrent and short Short circuit removed (i.e. short circuit to GND) OUTPUT DC OFFSET DETECTION. Any DC output offset exceeding ±2V are signalled out. This inconvenient might occur as a consequence of initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the speakers at risk of overheating. This diagnostic has to be performed with low-level output AC signal (or Vin = 0). The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command):START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1STOP = Actual reading operation Excess offset is signalled out if persistent throughout the assigned testing time. This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process. MULTIPLE FAULTS. When more misconnections are simultaneously in place at the audio outputs, it is guaranteed that at least one of them is initially read out. The others are notified after successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled. This is true for both kinds of diagnostic (Turn on and Permanent). The table below shows all the couples of possible double-fault. It should be taken into account that a short circuit with the 4 ohm speaker unconnected is considered as double fault. Double fault table for Turn On Diagnostic S. GND (sk) S. Vs S. Across L. Open L. S. GND (so) S. GND S. GND (so) S. GND S. Vs + S. GND S. GND S. GND S. GND (sk) / S. GND S. Vs S. GND Open L. (*) S. Vs / / S. Vs S. Vs S. Vs S. Across L. / / / S. Across L. N.A. Open L. / / / / Open L. (*) 11/19 TDA7561 S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2 outputs is shorted to ground (test-current source side= so, test-current sink side = sk). More precisely, so = CH+, sk = CH-. In Permanent Diagnostic the table is the same, with only a difference concerning Open Load(*) , which is not among the recognisable faults. Should an Open Load be present during the device's normal working, it would be detected at a subsequent Turn on Diagnostic cycle (i.e. at the successive Car Radio Turn on). FAULTS AVAILABILITY All the results coming from I2Cbus, by read operations, are the consequence of measurements inside a defined period of time. If the fault is stable throughout the whole period, it will be sent out. To guarantee always resident functions, every kind of diagnostic cycles (Turn on, Permanent, Offset) will be reactivate after any I2C reading operation. So, when the micro reads the I2C, a new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e. The device is in Turn On state, with a short to Gnd, then the short is removed and micro reads I2C. The short to Gnd is still present in bytes, because it is the result of the previous cycle. If another I2C reading operation occurs, the bytes do not show the short). In general to observe a change in Diagnostic bytes, two I2C reading operations are necessary. I2C PROGRAMMING/READING SEQUENCE A correct turn on/off sequence respectful of the diagnostic timings and producing no audible noises could be as follows (after battery connection): TURN-ON: (STAND-BY OUT + DIAG ENABLE) --- 500 ms (min) --- MUTING OUT TURN-OFF: MUTING IN --- 20 ms --- (DIAG DISABLE + STAND-BY IN) Car Radio Installation: DIAG ENABLE (write) --- 200 ms --- I2C read (repeat until All faults disappear). OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30ms - I2C reading (repeat I2C reading until high-offset message disappears). I2C BUS INTERFACE Data transmission from microprocessor to the TDA7561 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown by fig. 19, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown by fig. 20 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 12/19 TDA7561 Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 21). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock pulse. * Transmitter = master (µP) when it writes an address to the TDA7561 = slave (TDA7561) when the µP reads a data byte from TDA7561 ** Receiver = slave (TDA7561) when the µP writes an address to the TDA7561 = master (µP) when it reads a data byte from TDA7561 Figure 19. Data Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 20. Timing Diagram on the I2CBUS SCL I2CBUS SDA D99AU1032 START STOP Figure 21. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 ACKNOWLEDGMENT FROM RECEIVER 13/19 TDA7561 SOFTWARE SPECIFICATIONS All the functions of the TDA7561 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from µP to TDA7561) or read instruction (from TDA7561 to µP). Chip Address: D7 D0 1 1 0 1 1 X = 0 Write to device X = 1 Read from device If R/W = 0, the mP sends 2 "Instruction Bytes": IB1 and IB2. IB1 D7 X D6 Diagnostic enable (D6 = 1) Diagnostic defeat (D6 = 0) D5 Offset Detection enable (D5 = 1) Offset Detection defeat (D5 = 0) D4 Front Channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) D3 Rear Channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) D2 Mute front channels (D2 = 0) Unmute front channels (D2 = 1) D1 Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) D0 X D7 X D6 used for testing D5 used for testing D4 Stand-by on - Amplifier not working - (D4 = 0) Stand-by off - Amplifier working - (D4 = 1) D3 Power amplifier mode diagnostic (D3 = 0) Line driver mode diagnostic (D3 = 1) D2 X D1 X D0 X IB2 14/19 0 0 X D8 Hex TDA7561 If R/W = 1, the TDA7561 sends 4 "Diagnostics Bytes" to µP: DB1, DB2, DB3 and DB4. DB1 D7 Thermal Warning active (D7 = 1) D6 Diag. cycle not activated or not terminated (D6 = 0) Diag. cycle terminated (D6 = 1) D5 X D4 Channel LFTurn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) D3 Channel LF Normal load (D3 = 0) Short load (D3 = 1) D2 Channel LFTurn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Offset diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) D1 Channel LFNo short to Vcc (D1 = 0)Short to Vcc (D1 = 1) D0 Channel LFNo short to GND (D1 = 0)Short to GND (D1 = 1) D7 Offset detection not activated (D7 = 0) Offset detection activated (D7 = 1) D6 X D5 X D4 Channel LRTurn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) D3 Channel LRNormal load (D3 = 0) Short load (D3 = 1) D2 Channel LRTurn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) D1 Channel LR No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) D0 Channel LR No short to GND (D1 = 0) Short to GND (D1 = 1) DB2 15/19 TDA7561 DB3 D7 Stand-by status (= IB1 - D4) D6 Diagnostic status (= IB1 - D6) D5 X D4 Channel RFTurn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) D3 Channel RFNormal load (D3 = 0) Short load (D3 = 1) Channel RF Turn-on diag.: D2 No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) D1 Channel RFNo short to Vcc (D1 = 0) Short to Vcc (D1 = 1) D0 Channel RFNo short to GND (D1 = 0) Short to GND (D1 = 1) D7 X D6 X D5 X D4 Channel RR Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) D3 Channel RR Normal load (D3 = 0) Short load (D3 = 1) DB4 Channel RR Turn-on diag.: D2 No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) D1 Channel RRNo short to Vcc (D1 = 0)Short to Vcc (D1 = 1) D0 Channel RRNo short to GND (D1 = 0)Short to GND (D1 = 1) 16/19 TDA7561 Examples of bytes sequence 1 - Turn-On diagnostic - Write operation Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP 2 - Turn-On diagnostic - Read operation Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP ACK STOP ACK STOP ACK STOP The delay from 1 to 2 can be selected by software, starting from T.B.D. ms 3a - Turn-On of the power amplifier with 26dB gain, mute on, diagnostic defeat. Start Address byte with D0 = 0 ACK IB1 ACK X000000X IB2 XXX1X0XX 3b - Turn-Off of the power amplifier Start Address byte with D0 = 0 ACK IB1 ACK X0XXXXXX IB2 XXX0XXXX 4 - Offset detection procedure enable Start Address byte with D0 = 0 ACK IB1 ACK XX1XX11X IB2 XXX1X0XX 5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4). Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP ■ The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leackage current or humidity between pins. ■ The delay from 4 to 5 can be selected by software, starting from T.B.D. ms 17/19 TDA7561 DIM. A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 MIN. 4.45 1.80 0.75 0.37 0.80 23.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 24.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 24.25 29.30 0.029 0.014 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 0.031 0.935 1.138 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 0.945 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 0.955 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt25 (1): dam-bar protusion not included (2): molding protusion included H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N L3 R L L1 V1 V2 R2 D R1 L5 R1 R1 E G G1 F V M B C V FLEX25ME 18/19 M1 TDA7561 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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