Technical Data Sheet

PD84001
RF power transistor the LdmoST plastic family
Features
■
Excellent thermal stability
■
Common source configuration
■
Broadband performances POUT = 1 W
with 15 dB gain @ 870 MHz
■
Plastic package
■
ESD protection
■
Supplied in tape and reel
■
In compliance with the 2002/95/EC european
directive
SOT-89
Figure 1.
Pin connection
Description
Source
The PD84001 is a common source N-channel,
enhancement-mode lateral field-effect RF power
transistor. It is designed for high gain, broad band
commercial and industrial applications. It
operates at 7 V in common source mode at
frequencies of up to 1 GHz.
PD84001’s superior gain and efficiency makes it
an ideal solution for portable radio and UHF RFID
reader.
Table 1.
Source
Gate
Drain
Device summary
Order code
Marking
Package
Packaging
PD84001
8401
SOT-89
Tape and reel
August 2008
Rev 4
1/18
www.st.com
18
Contents
PD84001
Contents
1
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4
Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
2/18
6.1
Thermal pad and via design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PD84001
Electrical data
1
Electrical data
1.1
Maximum ratings
Table 2.
Absolute maximum ratings (TCASE = +25 °C)
Symbol
Value
Unit
V(BR)DSS
Drain-source voltage
18
V
VGS
Gate-source voltage
-0.5 to +15
V
1.5
A
6
W
150
°C
-65 to +150
°C
Value
Unit
21
°C/W
ID
PDISS
TJ
TSTG
1.2
Parameter
Drain current
Power dissipation
Max. operating junction temperature
Storage temperature
Thermal data
Table 3.
Symbol
RthJC
Thermal data
Parameter
Junction - case thermal resistance
3/18
Electrical characteristics
PD84001
2
Electrical characteristics
2.1
Static
Table 4.
Static (TCASE = +25 oC)
Symbol
2.2
Test conditions
Min.
VDS = 28 V
1
μA
IGSS
VGS = 5 V
VDS = 0 V
1
μA
VGS(Q)
VDS = 10 V
ID = 250 μA
5.0
V
VDS(ON)
VGS = 10 V
ID = 0.4 A
CISS
VGS = 0 V
VDS = 7 V
COSS
VGS = 0 V
CRSS
VGS = 0 V
2.0
3.0
0.6
V
f = 1 MHz
14.7
pF
VDS = 7 V
f = 1 MHz
13.3
pF
VDS = 7 V
f = 1 MHz
1.3
pF
Dynamic
Dynamic
Test conditions
Min.
Typ.
Max.
Unit
POUT
VDD = 7.5 V, IDQ = 50 mA, PIN = 17 dBm, f = 870 MHz
30
31
dBm
GPS
VDD = 7.5 V, IDQ = 50 mA, POUT = 30 dBm, f = 870 MHz
13
15
dB
VDD = 7.5 V, IDQ = 50 mA PIN = 17 dBm, f = 870 MHz
55
60
%
hD
Load
VDD = 7.5 V, IDQ = 50 mA, POUT = 1 W, f = 870 MHz
mismatch All phase angles
20:1
VSWR
ESD protection characteristics
Table 6.
ESD protection characteristics
Test conditions
Class
Human body model
2
Machine model
M3
Moisture sensitivity level
Table 7.
4/18
Unit
VGS = 0 V
Symbol
2.4
Max.
IDSS
Table 5.
2.3
Typ.
Moisture sensitivity level
Test methodology
Rating
J-STD-020B
MSL 3
PD84001
3
Impedance
Impedance
Figure 2.
Current conventions
Table 8.
Impedance data
Freq. (MHz)
ZGS (Ω)
ZDL(Ω)
920
4.0 + j4.3
3.7 + j6.2
900
3.6 + j4.3
3.9 + j5.5
880
3.3 + j4.1
4.1 + j4.7
860
3.1 + j3.7
4.3 + j4.0
840
2.9 + j3.4
4.5 + j3.2
820
2.8 + j3.0
4.8 + j2.4
800
2.7 + j2.5
5.0 + j1.6
5/18
Typical performance
4
Typical performance
Figure 3.
VGS vs ID
6/18
PD84001
Figure 4.
DC output characteristics
PD84001
Typical performance
Figure 5.
CRSS vs VDS
Figure 6.
CISS vs VDS
20
3.2
3.0
18
2.8
2.6
16
2.4
14
2.2
Ciss (pF)
Crss (pF)
2.0
1.8
1.6
1.4
1.2
12
10
8
6
1.0
0.8
4
0.6
0.4
2
0.2
0
0.0
0
1
2
3
4
5
6
CRSS
7
8
9
10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Vds (V)
CISS
Figure 7.
Vds (V)
COSS VS VDS
Coss vs Vds
28
26
24
22
Coss (pF)
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3 4
5
COSS
6
7
8
9 10 11 12 13 14 15
Vds (V)
7/18
Typical performance
Figure 8.
PD84001
Gain vs output power and
frequency
Figure 9.
Output power vs input power and
frequency
34
20
32
18
30
Pout (dBm)
Gain (dB)
16
14
12
10
28
26
24
Vdd = 7.5V
Idq = 50m A
22
8
20
6
18
18
20
22
24
26
28
30
32
34
0
2
4
6
8
Pout (dBm)
840 MHz
870 MHz
900 MHz
840 MHz
12
14
16
18
20
870 MHz
900 MHz
Figure 11. Gain and efficiency vs frequency
70
18
80
60
16
70
50
14
60
12
50
10
40
Gain (dB)
Nd (%)
Figure 10. Efficiency vs output power and
frequency
40
30
Vdd = 7.5V
Idq = 50m A
20
Pin = 17dBm
Vdd = 7.5V
Idq = 50m A
8
10
18
20
22
24
26
28
30
32
Pout (dBm)
840 MHz
8/18
10
Pin (dBm)
870 MHz
34
6
810
820
830
840
850
860
870
880
Freq (MHz)
900 MHz
Gain
Nd
890
900
30
910
20
920
PD84001
Typical performance
Figure 12. Input return loss vs frequency
Figure 13. Output power vs input power and
VDD
0
34
-4
30
Pout (dBm)
Input Return Loss (dB)
32
Pin = 17dBm
Vdd = 7.5V
Idq = 50m A
-2
-6
28
26
24
Freq = 870 MHz
Idq = 50m A
22
-8
20
-10
810 820 830 840 850 860 870 880 890 900 910 920
18
0
2
4
6
8
Freq (MHz)
10
12
14
16
18
20
Pin (dBm)
9V
7.5V
6V
70
34
60
32
50
30
0.4
28
0.3
30
26
0.2
20
24
0.1
Pout (dBm)
Nd (%)
Figure 14. Efficiency vs output power and VDD Figure 15. Output power and drain current vs
drain supply voltage
40
10
18
20
22
24
26
28
30
Pout (dBm)
9V
7.5V
32
34
0.6
Freq = 870 MHz
Pin = 17dBm
Idq = 50m A
0.5
22
0
2
3
4
5
6
7
8
9
10
Vdd (V)
6V
Pout
ID
9/18
Typical performance
PD84001
y
26
90
24
80
22
70
20
60
Freq = 520 MHz
Vdd = 7.5V
18
50
16
40
14
30
12
20
10
10
8
0
-5
0
5
10
15
20
25
30
Pin (dBm)
10/18
Gain-70mA
Gain-200mA
Gain-50mA
Gain-100mA
Eff-70mA
Eff-200mA
Eff-50mA
Eff-100mA
Efficiency (%)
Gain (dB)
Figure 16. Gain and efficiency vs pin
PD84001
5
Test circuit
Test circuit
Figure 17. Test circuit schematic / 840-900 MHz
11/18
Package mechanical data
6
PD84001
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
12/18
PD84001
Package mechanical data
Table 9.
SOT-89 mechanical data
Dim.
mm.
Min
Typ
Inch
Max
Min
Typ
Max
A
1.4
1.6
55.1
63.0
B
0.44
0.56
17.3
22.0
B1
0.36
0.48
14.2
18.9
C
0.35
0.44
13.8
17.3
C1
0.35
0.44
13.8
17.3
D
4.4
4.6
173.2
181.1
D1
1.62
1.83
63.8
72.0
E
2.29
2.6
90.2
102.4
e
1.42
1.57
55.9
61.8
e1
2.92
3.07
115.0
120.9
H
3.94
4.25
155.1
167.3
L
0.89
1.2
35.0
47.2
Figure 18. Package dimensions
13/18
Package mechanical data
6.1
PD84001
Thermal pad and via design
Thernal vias are required in the PCB layout to effectively conduct heat away from the
package. The via pattern has been designed to address thermal, power dissipation and
electrical requirements of the device.
The via pattern is based on thru-hole vias with 0.203 mm to 0.330 mm finished hole size on
a 0.5 mm to 1.2 mm grid pattern with 0.025 plating on via walls. If micro vias are used in a
design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar
results.
Figure 19. Pad layout details
SOT-89
14/18
PD84001
6.2
Package mechanical data
Soldering profile
Figure 20 shows the recommeded solder for devices that have Pb-free terminal plating and
where a Pb-free solder is used.
Figure 20. Recommended solder profile
Figure 21 shows the recommeded solder for devices with Pb-free terminal plating used with
leaded solder, or for devices with leaded terminal plating used with a leaded solder.
Figure 21. Recommended solder profile for leaded devices
15/18
Package mechanical data
Figure 22. Reel information
16/18
PD84001
PD84001
7
Revision history
Revision history
Table 10.
Document revision history
Date
Revision
Changes
06-Dec-2006
1
Initial release
16-May-2007
2
Marking updated
05-Jun-2007
3
Part number update
25-Aug-2008
4
Updated Table 4 on page 4
17/18
PD84001
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