RENESAS M65665CSP

M65665CFP/SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
REJ03F0011-0100Z
Rev.2.00
Sep.04.2003
Description
The M65665CFP/SP is a PIP (Picture in Picture) signal processing LSI, whose sub-picture input is composite signal or
component signals(Y/C or Y/U/V) for NTSC.
The built-in field memory (168k-bit RAM) , V-chip data slicer and analog circuitries lead the high quality PIP system
low cost and small size.
Features
•
•
•
•
•
Internal V-chip data slicer (for sub-picture)
Vertical filter for sub-picture ( Y signal )
Base band com filter (2 Line)
Single sub-picture ( selectable picture size : 1/9 , 1/16 )
Sub-picture processing specification ( 1/9 , 1/16 size) :
Quantization bits Y, B-Y, R-Y : 7 bits
Horizontal sampling 229 pixels (Y), 57 pixels (B-Y, R-Y)
Vertical lines 69/ 52 lines
• Frame ( sub-picture ) on/off
• Built-in analog circuits :
Two 8-bit A/D converters (for sub-picture signal)
Three 8-bit D/A converters (for Y, U and V of sub-picture)
Auto Slicer(Sync Sep.), Sync-tip-clamp, VCXO, OSD switch, etc..
I
• I C BUS control ( parallel/serial control) :
PIP on/off , Frame on/off ( programmable luma level),
Sub-picture size ( 1/9, 1/16 ),
PIP position ( free position ), Picture freeze ,
Y delay adjustment, Chroma level, Tint, Black level, Contrast ...etc..
Application
NTSC color TV
Recommended Operating Conditions
Supply voltage range --------------------- 3.2 to 3.5 V
Recommended supply voltage --------------------- 3.3 V
Rev.2.00, Sep.04.2003, page 1 of 17
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18
Rev.2.00, Sep.04.2003, page 2 of 17
SWM
SDATA
SCLK
DVdd
DVss
BGPS
SCK
BGPM
FSC
TEST5
5
6
7
8
9
10
11 12 13 14 15 16 17 18
VRT
4
Yin(ADC)
3
SWM
OSD_SEL
SDATA
SCLK
DVdd
DVss
BGPS
SCK
BGPM
FSC
TEST5
CIN(ADC)
AVss(ADC)
VRT
Yin(ADC)
VRB
AVdd(VCXO)
CVBSIN(ADC)
Uin(ADC)
FILTER
AVdd(ADC)
Vin(ADC)
BIAS
CSYNCS
X'tal(NTSC)
Pin Configuration of M65665CSP (Top View)
X'tal(PAL-M)
SWMG
TESTEN
2
RESET
X'tal(PAL-N)
AVss(VCXO)
HD
VD
Vdd(DAC)
OSD_BIN
V(B)OUT
VZ
OSD_GIN
U(G)OUT
AGnd(DAC)
OSD_RIN
Y(R)OUT
1
VRB
Uin(ADC)
Vin(ADC)
AVdd(ADC)
CSYNCS
RESET
SWMG
TESTEN
1
OSD_SEL
CIN(ADC)
AVss(ADC)
CVBSIN(ADC)
AVdd(VCXO)
FILTER
BIAS
X'tal(NTSC)
X'tal(PAL-M)
X'tal(PAL-N)
AVss(VCXO)
HD
VD
Vdd(DAC)
OSD_BIN
V(B)OUT
VZ
OSD_GIN
U(G)OUT
AGnd(DAC)
OSD_RIN
Y(R)OUT
M65665CFP/SP
Pin Configuration of M65665CFP (Top View)
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
M65665CFP
XXXXXX
19 20 21
42 Pin SSOP
Package :
42P2R
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
XXXXXX
M65665CSP
19 20 21
42 Pin SDIP
Package :
42P4B
MUX
Rev.2.00, Sep.04.2003, page 3 of 17
AVDD
A/D
19
18 17 22 33 32
DEMUX
&
Encoder
AGND
Demod.
&
TINT
B.P.F.
26
27
B.Gate
&
P.D.
28
SW
VCXO
29
30
I2C BUS
Analog Switch
37
RESET
TESTEN
41 38 35 2
DVDD DGND
V-CHIP
Data Slicer
Sync.
Slice(analog)
Sync. Auto
Slice(analog)
Sync.
Sep.(digital)
I2C BUS
Sub-DAC
DAC
I2C BUS
Sub-DAC
DAC
I2C BUS
Sub-DAC
DAC
1
4
3
SDA
SW
36
SCL
A/D
Timing
Gen.
V
U
Y
39
Main HD
24 20
Comb
Filter
Main VD
L.P.F.
Sub picture(C)
Vertical
Filter
42
Sub picture(V)
21
Sub picture
(Y(Y/U/V))
Sub picture(U)
Sub picture
(CVBS or Y(Y/C))
+
OSD_SEL
Bexttin
Gextin
Rextin
PIP SW
V/B OUTPUT
U/G OUTPUT
Y/R OUTPUT
M65665CFP/SP
Block Diagram
14
Output Control & RGB Matrix
PIP
Field
Memory
I 2C
I/F
12
11
10
9
8
7
13
15
Ext.
C-sync
6
5
40
31
23
34
25
16
M65665CFP/SP
Absolute Maximum Ratings
(Vss=0 V)
Limits
Parameter
Symbol
Min.
Max.
Unit
Supply voltage (3.3V)
Input voltage (except for 5V input)
VDD3
VI3
−0.3
−0.3
4.2
VDD3+0.3
V
V
Input voltage (5V)
Output voltage
VI5
VO
−0.3
−0.3
5.25
VDD3+0.3
V
V
Output current (*1)
Operating temperature
IO
Topr
IOH=−4
−10
IOL=4
70
mA
deg.
Storage temperature
Tstg
−50
125
deg.
Conditions
Note : 1. Output current per output terminal. But Pd limits all current.
THERMAL DERATING (MAXIMUM RATING)
POWER DISSIPATION Pd (mW)
2000
1600
1350
M
65
1200
1100
M6
5
800
750
600
66
5C
66
5C
SP
FP
400
0
0
25
50
70
75
100
125
AMBIENT TEMPERATURE Ta (deg.)
Recommended Operating Conditions
(Ta = 25 °C, unless otherwise noted)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
Operating frequency
VDD3
fopr
3.2

3.3
14.32
3.5

V
MHz
“H” Input voltage
(CMOS interface)
“L” Input voltage
(CMOS interface)
VIH
VDD3×0.7

VDD3
V
VIL
0

VDD3×0.3
V
Output current
(output buffer)
Output load
capacitance
IO


2
mA
COL


20
pF
Rev.2.00, Sep.04.2003, page 4 of 17
Conditions
Include pin capacitance (7pF)
M65665CFP/SP
DC Characteristics
(Ta = 25 deg. unless otherwise noted)
(VSS=0V)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
VIL
0

0.81
V
VDD=2.7V
VIH
2.52

3.6
V
VDD=3.6V
IIL3
−10

10
µA
VDD=3.6V,VI=0V
IIH3
−10

10
µA
VDD=3.6V,VI=3.6V
VT-
0.8

1.65
V
VDD=3.3V
VT+
1.4

2.7
V
Hysteresis
L
VH
IIL5
0.3
−100


1.2
10
V
µA
VDD=3.6V,VI=0V
CMOS output voltage
H
L
IIH5
VOL
−10



10
0.05
µA
V
VDD=3.6V,VI=3.6V
VDD=3.3V,|IO|=1µA
CMOS output current
H
L
VOH
IOL
3.25
2




V
mA
VDD=3.3V,VOL=0.4V
Output leakage current
H
L
IOH
IOZL

−10


−2
10
mA
µA
VDD=3.3V,VOL=2.6V
VDD=3.6V,VO=0V
H
IOZH
CI
−10


7
10
15
µA
pF
VDD=3.6V,VO=3.6V
f=1MHz,VDD=0V
CO
CIO


7
7
15
15
pF
pF
IDD

140

mA
Input voltage
(3.3V CMOS interface)
L
H
Input current
(3.3V CMOS interface)
L
H
−
+
Input voltage schmitt
(5.0V CMOS interface)
Input current
(5.0V CMOS interface)
Input pin capacitance
Output pin capacitance
Bi-directional pin
capacitance
Operating current
3.3V supply
Rev.2.00, Sep.04.2003, page 5 of 17
M65665CFP/SP
Pin Description
Pin No.
Name
I/O
Function
1
SWM
CMOS output
PIP switch output
2
OSD_SEL
CMOS input
Output OSD select
3
4
SDATA
SCLK
CMOS input/output (5V)*1
CMOS input (5V)*1
IIC SDA input/output
IIC SCL input
5
6
DVdd
DVss
Digital Vdd
Digital Vss
VDD for digital part
VSS for digital part
7
8
BGPS
SCK
CMOS output
CMOS input
Test output
Test input
connect to GND
9
10
BGPM
FSC
CMOS output
CMOS input
Test output
Test input
connect to GND
11
12
TEST5
TESTEN
CMOS input
CMOS input
Test input
Test input
connect to GND
connect to GND
13
14
SWMG
RESET
CMOS input
CMOS input
PIP switch output enable
Power on reset input
connect to VDD
15
16
CSYNCS
AVdd(ADC)
CMOS input
Analog Vdd
Sub picture external c-sync input
Vdd for internal ADC
17
18
VIN(ADC)
UIN(ADC)
Analog
Analog
Sub picture V input of ADC
Sub picture U input of ADC
19
20
VRB
YIN(ADC)
Analog
Analog
Low level reference voltage output of ADC
Sub picture Y input of ADC
21
22
VRT
CIN(ADC)
Analog
Analog
High level reference voltage output of ADC
Sub picture C input of ADC
23
24
AVss(ADC)
CVBSIN(ADC)
Analog Vss
Analog
VSS for internal ADC
Sub picture CVBS input of ADC
25
26
AVdd(VCXO)
FILTER
Analog Vdd
Analog
Vdd for VCXO
VCXO filter voltage connection
27
28
BIAS
X'tal(NTSC)
Analog
Analog
VCXO bias voltage connection
X'tal of NTSC connection
29
30
TEST
TEST
Analog
Analog
TEST
TEST
31
32
AVss(VCXO)
HD
Analog Vss
CMOS input (5V)*1
Vss for VCXO
Main picture HD input
33
34
VD
Vdd(DAC)
CMOS input (5V)*1
Analog Vdd
Main picture VD input
Vdd for DAC
35
36
OSD_BIN
V(B)OUT
Analog
Analog
OSD input of B
Sub picture V or B output
37
38
VZ
OSD_GIN
Analog
Analog
Voltage reference output of DAC
OSD input of G
39
40
U(G)OUT
AVss(DAC)
Analog
Analog Vss
Sub picture U or G output
Vss for DAC
41
42
OSD_RIN
Y(R)OUT
Analog
Analog
OSD input of R
Sub picture Y or R output
Note : 1. (5V) means 5V I/F tolerant
Rev.2.00, Sep.04.2003, page 6 of 17
Remarks
connect to GND
connect to GND
M65665CFP/SP
Basic Application Example
When using any or all of the information contained in this diagrams, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products.
Dig.
Ana.
Digital +3.3V power supply
Digital GND
Analog +3.3V power supply
Analog GND
20 pin input level
Sub CVBS and Y(Y/C) input
24 pin input level
0.47u
white peak
1.0Vpp
(max)
0.66V(max)
3.3 K
0.033u
Ana.
0.1u
pedestal
18 p
0.01u
23
20
0.1u
24
19
0.01u
18
0.1u
17
0.1u
16
26
27
0.22u
sync tip
21
25
3.3 M
0
X1
28
29
31
36 pin output level
pedestal
33
OSD B input
0.1u
PIP V(B) output
0.01u
0.7Vpp (typ)
0.01u
39 pin output level
OSD G input
PIP U(G) output
0.7Vpp (typ)
0.1u
0.01u
0.7V (typ)
back ground
pedestal
35
36
37
38
39
40
42 pin output level
white peak
34
OSD R input
PIP Y(R) output
Rev.2.00, Sep.04.2003, page 7 of 17
0.1u
41
0.01u
42
Sub U input
Sub V input
pedestal
17 pin input level
0.7Vpp (typ)
pedestal
10u
14
13
12
10K
11
10
15 pin input when CSYNC
of sub picture is fed from
external.
3.3V
9
0V
8
7
2 pin input level
6
5
Dig.
pedestal
32
Main HD input
Main VD input
Ana.
32 pin /33 pin input level
3.3V-5.0V
0V
18 pin input level
0.7Vpp (typ)
Dig.
30
sync tip
Sub Y(Y/U/V) input
15
Dig.
X1 : SIWARD 1-781-377-21(14.31818MHz)
pedestal
22
+
0.01u
M65665CFP/SP
Sub C(Y/C) input
Ana.
22 pin input level
pedestal
0.7Vpp(typ)
white peak
1.0Vpp
(max)
0.66V
(max)
3.3V
0V
4
I2C BUS Clock input
3
I2C BUS DATA input /output
OSD selection input
PIP SW output 1 pin output level
2
1
3.3V
0V
M65665CFP/SP
TV System Block Diagram
< Y/U/V PIP Mixing system >
Y
Y/C
Separation C
Composite
Video Signal
Y
Y
Video
Signal
Processing
C
Y/C Separated
Video Signal
Y/U/V
Component
Video Signal
U
Y
U
V
G
B
Deflection
Unit
M65665CFP/SP
PIP Signal
Processing
Matrix
V
CV/Y
Y
C
R
Y
U
V
SWM
HD
Yoke
VD
< R/G/B PIP&OSD Mixing system >
Y
Y/C
Separation C
Composite
Video Signal
Y
R
Video
Signal
Processing
C
Y/C Separated
Video Signal
Y/U/V
Component
Video Signal
Y
C
Y
U
V
Rev.2.00, Sep.04.2003, page 8 of 17
G
B
CV/Y
M65665CFP/SP
PIP Signal
Processing
OSD_R
OSD_G
OSD_B
OSD_F.B.
R
G
B
SWM
Deflection
Unit
HD
VD
Yoke
M65665CFP/SP
I2C Register Information
When using any or all of the information contained in this table, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products.
Address
00h
Bit
Symbol
Read/
Write
Reset
Value
1/9 Ref.
Value
Remarks
<7>
DISP
W/R
0
1h
Sub picture display : [0] off , [1] on
<6>
SIZE_V
W/R
0
0
Sub picture vertical size : [0] 1/9 , [1] 1/16
<5>
SIZE_H
W/R
0
0
Sub picture horizontal size : [0] 1/9 , [1] 1/16
<4>
WEN
W/R
0
1h
Sub picture : [0] Still , [1] Moving
<3>
BGC
W/R
0
0
Back ground display : [0] off , [1] on
<2>
BGCS
W/R
0
0
Sub picture mute : [0] off , [1] on
<1>
FREE_RUN
W/R
0
0
VCXO oscilation : [0] Lock , [1] Free run
<0>

W/R
0
0
For test : 0 set only
01h
<7:0>
VXA<7:0>
W/R
0
20h
Sub picture vertical position
02h
<7:0>
HXA<7:0>
W/R
0
20h
Sub picture horizontal position
03h
<7>
DECODE
W/R
0
0
Sub picture color decoder reset : [1] reset
<6:0>
CONTRAST<6:0>
W/R
0
32h
Sub picture Y or R DAC output amplitude control
<7>
KILLER
W/R
0
0
Sub picture color killer : [0] enable , [1] disable
<6:0>
U_DAC<6:0>
W/R
0
32h
Sub picture U or G DAC output amplitude control
<7>
GRC
W/R
0
1h
Frame display : [0] off , [1] on
<6>
YUVN_RGB_SEL
W/R
0
0
PIP output mode selection : [0] YUV , [1] RGB
<5:0>
TINT<5:0>
W/R
0
0
Sub picture TINT control
<7:6>
EXT_SC_SEL<1:0>
W/R
0
1h
Sub picture c-sync sep. selection :
[0] int. digital , [1] int. auto slice , [2] ext.(18 pin) , [3] int.
analog
Sub picture int. c-sync sep. threshhold setting.
04h
05h
06h
07h
08h
09h
0Ah
0Bh
<5:4>
DCONT<1:0>
W/R
0
0
<3:0>
HT<3:0>
W/R
0
Ah
Sub picture display timing adjust
<7:6>
INPUT_SEL<1:0>
W/R
0
2h
Sub picture input selection : [0] YC , [1] N.A. , [2] CVBS , [3]
YUV
<5:0>
BG_START<5:0>
W/R
0
0Fh
Sub picture Burst Gate Pulse position setting
<7:4>
ADJ<3:0>
W/R
0
4h
Main/Sub switch delay control
<3:0>
YDL<3:0>
W/R
0
Ah
Sub picture Y/C delay adjust
<7:5>
BGBY<2:0>
W/R
0
0
Back ground U level setting
<4:0>
Y_OFFSET<4:0>
W/R
0
0Fh
Sub picture Y bright control
<7>
VCHIP ONLY
W/R
0
1h
V-chip decode mode : [0] off , [1] on
<6:4>
BGRY<2:0>
W/R
0
0
Back ground V level setting
<3:0>
BGY<3:0>
W/R
0
6h
Back ground Y level setting
<7:4>
PEDESTV<3:0>
W/R
0
0
Sub picture V pedestal level (2's comp)
<3:0>
PEDESTU<3:0>
W/R
0
0
Sub picture U pedestal level (2's comp)
Rev.2.00, Sep.04.2003, page 9 of 17
M65665CFP/SP
Address
Bit
Symbol
Read/
Write
Reset
Value
1/9 Ref.
Value
Remarks
0Ch
<7>
UV_FILTER_OFF
W/R
0
1h
Sub picture U,V output filter [0] on , [1] off
<6>
SET_ACC
W/R
0
0
Address 0Dh,0Eh setting mode : [0] fixed value, [1] released
to MCU
<5:4>

W/R
0
0
For test : 0 set only
<3>
SET_SIZE
W/R
0
0
Address 11h<6:0>,12h-14h setting mode : [0] fixed value,
[1] released to MCU
<2>
SET_VCHIP
W/R
0
0
Address 15h-17h setting mode : [0] fixed value, [1] released
to MCU
<1:0>
SYNC_DELAY<1:0>
W/R
0
0
Sub picture sync. delay control
Sub picture color control parameter when YUV input
0Dh
0Eh
0Fh
<7:4>
YUV_COL<3:0>
W/R
0
0
<3>
C_GAIN_SEL
W/R
0
0
Sub picture chroma : [0] X1 , [1] X2
<2>
WDOF_KILLER_ON
W/R
0
0
Sub picture killer on when burst PLL is unlock : [0] off , [1]
on
<1>
SET_YUV
W/R
0
0
For test : 0 set only
<0>
CVF
W/R
0
0
Internal chroma comb filter : [0] on , [1] off
<7>
BITSEL
W/R
0
0
Sub picture Y clamp time constant : [0] X2 , [1] X1
<6>
AFCBITSEL
W/R
0
0
Sub picture AFC time constant : [0] X2 , [1] X1
<5:0>
ACC_LEVEL<5:0>
W/R
0
15h
Sub picture color decoder amplitude
<7>


W/R
0
0
For test : 0 set only
<6>
W/R
0
0
For test : 0 set only
<5>

W/R
0
0
For test
<4>
INV_RFF
W/R
0
0
Invert main picture field definition : [0] normal , [1] invert
<3>
INV_WFF
W/R
0
0
Invert sub picture field definition : [0] normal , [1] invert
<2>

W/R
0
0
For test : 0 set only
<1>
RFF_FIX
W/R
0
0
Main picture field fix : [0] not fix , [1] fix
<0>

W/R
0
1h
For test
Rev.2.00, Sep.04.2003, page 10 of 17
M65665CFP/SP
Address
Bit
Symbol
Read/
Write
Reset
Value
1/9 Ref.
Value
Remarks
10h
<7:6>
NO_BST_LVL<1:0>
W/R
0
0
For test
<5:4>
BW_DET_LVL<1:0>
W/R
0
0
BW det. threshold setting : [0] off , [1] 16mV , [2] 32mV ,
[3] 64mV
<3:0>
W/R
0
0
For test
<7>


W/R
0
0
For test : 0 set only
<6:0>
HYA<6:0>
W/R
0
37h
Sub picture horizontal display pixel
<7:0>
VYA<7:0>
W/R
0
44h
Sub picture vertical display line number
11h
12h
13h
<7:2>
HX<5:0>
W/R
0
1Eh
Sub picture horizontal capture position (coarse)
<1:0>
HP<1:0>
W/R
0
0
Sub picture horizontal capture position (fine)
<7:6>
MVC<1:0>
W/R
0
0
Sub picture c-sync input mask period :
[0] 48usec , [1] 44usec , [2] 53usec , [3] off
<5:0>
VXS<5:0>
W/R
0
29h
Sub picture sample start line
<7>

W/R
0
0
For test : 0 set only
<6>
PLUS
W/R
0
0
For test : 0 set only
<5>

W/R
0
0
For test : 0 set only
<4:0>
LINE_NUM<4:0>
W/R
0
11h
Data slicer line selection
16h
<7:0>
STB_DLY<7:0>
W/R
0
40h
Data slicer start bit detection parameter
17h
<7:0>
L_LEVEL<7:0>
W/R
0
82h
Data slicer data slice parameter
18h
<7>
EDGE_ON
W/R
0
1h
Frame data independent control : [0] disable , [1] enable
<6:4>
BGBY_EDGE<2:0>
W/R
0
0
Frame data independent B-Y data setting
<3:0>
BGY_EDGE<3:0>
W/R
0
Ch
Frame data independent Y data setting
14h
15h
19h
<7:5>
BGRY_EDGE<2:0>
W/R
0
0
Frame data independent R-Y data setting
<4>
HPFOFF
W/R
0
0
Sub picture Y output HPF : [0] on , [1] off
<3:0>
FREE_RUN_ADJ<3:0>
W/R
0
0
Frequency adjustment control when free run mode (2's
comp)
1Ah
<7:0>

W/R
0
0
For test
1Bh
<7:6>
EXPORT<1:0>
W/R
0
0
Ext. port (7 pin) : [0] "0" output , [1] "1" output , [2 or 3]
Sub BGP
<5>
INV_UV
W/R
0
0
Invert U,V output value : [0] normal , [1] invert
<4>
AFC_OFF
W/R
0
0
Sub picture AFC : [0] on , [1] off
<3:0>

W/R
0
0
For test
1Ch
<7>
PINOE
W/R
0
0
For test
<6:0>
V_DAC<6:0>
W/R
0
32h
Sub picture V or B DAC output amplitude control
1Dh
<7:0>
PINOE<7:0>
W/R
0
E6h
For test
1Eh
<7:0>

W/R
0
0
For test : 0 set only
Rev.2.00, Sep.04.2003, page 11 of 17
M65665CFP/SP
Address
Bit
Symbol
Read/
Write
1Fh
<7:6>

R
20h
Reset
Value
1/9 Ref.
Value
Remarks
Test use (Read only)
<5>

R
Test use (Read only)
<4>
SUB_UNLOCK
R
VCXO is : [0] Lock , [1] Unlock (Read only)
<3>

R
Test use (Read only)
<2>
RDOF
R
Main picture V sync is [0] present , [1] not present (Read
only)
<1>
SUB_BW
R
Sub picture burst is : [0] not present , [1] present (Read
only)
<0>
WDOF
R
Sub picture V sync is [0] present , [1] not present (Read
only)
<7>
KILLERSTATUS
R
Sub picture killer status : [0] not active , [1] active (Read
only)
<6>

R
Test use (Read only)
<5>
WDOF
R
Sub picture V sync is [0] present , [1] not present (Read
only)
<4>
EDS_ACK2
R
EDS data flag of even field : [0] no EDS , [1] EDS (Read
only)
<3>
EDS_ACK1
R
EDS data flag of odd field : [0] no EDS , [1] EDS (Read
only)
<2>
SIGNAL_OK
R
Test use (Read only)
<1>
READ_REQB
R
Read request of even field : [0] no , [1] requesting (Read
only)
<0>
READ_REQA
R
Read request of odd field : [0] no , [1] requesting (Read
only)
21h
<7:0>
PDB<15:8>
R
Even field Sliced data upper 8bit (Read only)
22h
<7:0>
PDB<7:0>
R
Even field Sliced data lower 8bit (Read only)
23h
<7:0>
PDA<15:8>
R
Odd field Sliced data upper 8bit (Read only)
24h
<7:0>
PDA<7:0>
R
Odd field Sliced data lower 8bit (Read only)
Rev.2.00, Sep.04.2003, page 12 of 17
M65665CFP/SP
The relation of input signal 32-pin (Main-HD) and 33-pin (Main-VD) is shown below
prohibition time of
changing 33-pin signal
0
32-pin input
(Main-HD)
33-pin input
-10µsec
(Main-VD)
[Even to Odd]
+10µsec
+41.75µsec
+21.75µsec
33-pin input
(Main-VD)
[Odd to Even]
20µs
+53.5µsec
20µs
20µs
20µs
20µs
20µs
VD input
4H
1H
end of vertical equalization pulse
20µs
20µs
20µs
20µs
20µs
20µs
VD input
31.75µs
Driving Method and Operating Specification for Serial Interface Data
(1) Serial data transmission completion and start
A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial
transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the
serial transmission and waits for the following CLK and DATA inputs.
(2) Serial data transmission
The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. Onebyte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for
acknowledge detection. (In writing state, SDATA outputs ‘L' under these two conditions ; 1) the coincidence of two
address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In reading state, SDATA
outputs ‘L' with the address coincidence and SDATA becomes high-impedance for detecting acknowledge input from
the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while
CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false
operation because of undistinguished condition from the completion / start of serial data transfer). After the beginning
of serial data transmission, the total number of data bytes that can be transferred are not limited.
(3) The byte format of data transmission (The sequence of data transmission)
a. The byte format during data writing to M65665CFP/SP are shown as follows.
In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards,
the internal register address (1 byte) and writing data (by 1 byte unit) are transferred successively. Several bytes of
Rev.2.00, Sep.04.2003, page 13 of 17
M65665CFP/SP
writing data can be handled in the one transmission. In this operation, the setting data are written into the address
register whose address is increased one in initially transferred internal register address.
b. The byte format during data reading from M65665CFP/SP are shown as follows.
Before data reading from M65665CFP/SP, whose internal address need to be set by the data reading/transmitting. After
the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is
necessary. Continuously, the slave address 25h (00100101b) is sent, and then the read out data are available on SDATA
as ‘L’/‘high-impedance’ pattern. Several bytes of reading data can be handled in the one transmission, too. In this
operation, the setting data also are written into the address register whose address is increased one in initially
transferred internal register address.
The examples of serial byte transmission format
(1) The writing operation of the setting data (AAh) into M65665CFP/SP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
S
24h
A
00h
A
AAh
A E
S : Operation of serial transmission start
A : Acknowledge detection
E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65665CFP/SP internal address of 04h to 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
S
24h
A
04h
A
FFh
A
80h
A
EEh
25h
A
$$h
A'
A E
(3) The reading operation of the setting data from M65665CFP/SP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
S
24h
A
00h
A E S
A' : Bus free operation by the master (micro processor)
Rev.2.00, Sep.04.2003, page 14 of 17
M65665CFP/SP
(4) The reading operation of the setting data from M65665CFP/SP internal address of 04h to 06h.
Transmission
Activation
Confirmation
of bus free
(DATA='H')
S
24h
A
04h
A E S
25h
A
$$h A" $$h A"
$$h
A'
A" : Output 'L' operation by the master (micro processor)
Timing Diagram
1
2
3
4
5
6
7
8
9
1
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
SCLK
(4 pin)
SDATA
(3 pin)
SDATA (3 pin)
(Read data)
Rev.2.00, Sep.04.2003, page 15 of 17
Bit7
(MSB)
e
SEATING PLANE
D
b1
b
21
Lead Material
Alloy 42/Cu Alloy
1
Weight(g)
4.1
22
JEDEC Code
−
MMP
42
EIAJ Package Code
SDIP42-P-600-1.78
A
L
b2
E
A2
Rev.2.00, Sep.04.2003, page 16 of 17
A1
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
Symbol
Plastic 42pin 600mil SDIP
c
Dimension in Millimeters
Min
Nom
Max
−
−
5.5
0.51
−
−
−
3.8
−
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
36.5
36.7
36.9
12.85
13.0
13.15
−
1.778
−
−
15.24
−
3.0
−
−
0˚
−
15˚
e1
42P4B
M65665CFP/SP
Package Dimensions
HE
G
1
42
Z1
e
z
y
Detail G
D
JEDEC Code
−
MMP
b
21
22
Weight(g)
−
Detail F
A2
Lead Material
Cu Alloy+42 Alloy
L1
EIAJ Package Code
SSOP42-P-450-0.80
E
Rev.2.00, Sep.04.2003, page 17 of 17
A
c
A1
F
L
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
Symbol
e1
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
−
−
2.4
−
0.05
−
−
2.0
−
0.4
0.25
0.3
0.2
0.13
0.15
17.3
17.7
17.5
8.2
8.4
8.6
−
−
0.8
12.23
11.63
11.93
0.7
0.3
0.5
−
−
1.765
−
0.75
−
−
0.9
−
0.15
−
−
0˚
10˚
−
−
0.5
−
−
−
11.43
−
1.27
−
Recommended Mount Pad
e
Plastic 42pin 450mil SSOP
I2
42P2R-E
M65665CFP/SP
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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