RENESAS M61538FP

M61538FP
6-Channel Electronic Volume
REJ03F0103-0100Z
Rev.1.0
Mar.23.2004
Description
The M61538FP is 6ch electronic volume. This IC is controlled by 2-wire serial bus and is suitable for Home Audio
System.
Features
• Electronic Volume
•
•
•
•
0 to –95dB, –∞/1dBstep
6-Channel independent Electronic Volume
MUC I/F Controlled by serial data from microcomputer
Low Noise 0.85µVrms: typ. [Volume = 0dB, Rg = 0Ω, IHF-A]
Low Distortion 0.0012%: typ. [Vi:0.3Vrms, f:1kHz, BW:400Hz to 30kHz]
Power Supply ±Power supplies or Single power supply
Applications
• Receiver, AV Amp, Mini Stereo etc.
Recommended Operating Condition
• Supply Voltage Range
 ±Power supplies VCC: +4.5 to +7.5V [Typ: 7V], VEE: –4.5 to –7.5V[Typ: –7V],
DVDD: +2.7 to + 5.5V [Typ:5V]
 Single power supply VCC: +9 to +12V[Typ: 10V], DVDD: 4.5 to +5.5V[Typ: 5V]
System Block Diagram
(±Power supplies used)
LIN
LOUT
RIN
ROUT
CIN
COUT
SWIN
SWOUT
SLIN
SLOUT
SRIN
SROUT
Logic
CLOCK DATA
Rev.1.0, Mar.23.2004, page 1 of 11
DGND DVDD
VCC AGND VEE
M61538FP
Block Diagram and Pin Configuration
LIN 13
12 AGND
25K Vol
AGND 14
RIN 15
11 LOUT
10 ROUT
25K Vol
9 COUT
AGND 16
CIN 17
25K
8 DGND
Vol
7 CLOCK
VCC 18
MCU I/F
Logic
VEE 19
SWIN 20
5 DVDD
25K Vol
4 SWOUT
AGND 21
SLIN 22
3 SLOUT
25K Vol
2 SROUT
AGND 23
SRIN 24
6 DATA
1 AGND
25K Vol
(Top View)
Pin Description
(±Power supplies used)
PIN No.
Name
Function
1, 23
2
AGND
SROUT
Analog ground of SW/SL/SR volume
Output pin of SR channel
3
4
SLOUT
SWOUT
Output pin of SL channel
Output pin of SW channel
5
6, 7
DVDD
DATA, CLOCK
Digital Power supply (Typ: 5V)
Input pin of Control data/clock
8
9
DGND
COUT
Digital ground
Output pin of C channel
10
11
ROUT
LOUT
Output pin of R channel
Output pin of L channel
12, 14
13
AGND
LIN
Analog ground of L/R/C volume
Input pin of L channel
15
16, 21
RIN
AGND
Input pin of R channel
Analog ground of all channels
17
18
CIN
VCC
Input pin of C channel
Positive Power supply (Typ: +7V)
19
20
VEE
SWIN
Negative Power supply (Typ: –7V)
Input pin of SW channel
22
24
SLIN
SRIN
Input pin of SL channel
Input pin of SR channel
Rev.1.0, Mar.23.2004, page 2 of 11
M61538FP
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Unit
Condition
Analog Power supply
VCC-VEE
16
V
VCC-VEE (±Power supplies used)
Digital Power supply
Power dissipation
DVDD-DGND
Pd
7
1.0
V
W
DVDD-DGND
Ta ≤ 25°C
Thermal derating
Operating temperature
K
Topr
10.0
–20 to +75
mW/°C
°C
Ta > 25°C
Storage temperature
Tstg
−40 to +125
°C
Note: VEE ≤ DGND < DVDD ≤ VCC
Thermal Deratings (Maximum Rating)
POWER DISSIPATION pd (W)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-40
0
40
75
80
120
AMBIENT TEMPERATURE Ta (°C)
Rev.1.0, Mar.23.2004, page 3 of 11
150
M61538FP
Recommended Operating Conditions
(Ta = 25°C, unless otherwise noted)
Limits
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Analog supply voltage (Positive)
VCC
4.5
7
Analog supply voltage (Negative)
VEE
–7.5
–7
7.5
V
±Power supplies used
–4.5
V
±Power supplies used
Analog supply voltage
VCC
9
2.7
10
5
12
5.5
V
V
Single power supply used
±Power supplies used,
DGND = 0V
Digital supply voltage
VDD
4.5
5
5.5
V
VIH
DVDD
×0.7
—
DVDD
V
Single power supply used,
DGND = 0V
DGND = 0V
Logic “H” level input voltage
Logic “L” level input voltage
VIL
DGND
—
DVDD
×0.3
V
DGND = 0V
Notes: 1. VEE ≤ DGND < DVDD ≤ VCC
2. Apply VCC, VEE and DVDD at the same time.
Relationship between Data and Clock
Data signal is read at the rising edge of CLOCK.
DATA
D0
D1
D2
D3
Make "H" at the timing which
DATA of D0-D15 make latch.
D13
D14
D15
CLOCK
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
Rev.1.0, Mar.23.2004, page 4 of 11
M61538FP
Clock and Data Timings
(D0 ~ D15)
LATCH
t cr
DATA
75%
25%
tSLD
tHLD tSHD
tSLD
tHHD
tHLD
75%
50%
25%
CLOCK
tr
tf
tWHC
tWLC
Timing Definition of Digital Block
Limits
Parameter
Symbol
Min
Typ
Max
CLOCK cycle time
CLOCK pulse width (“H” level)
tcr
tWHC
8
3.2
—
—
—
—
CLOCK pulse width (“L” level)
Rising time of clock and data
tWLC
tr
3.2
—
—
—
—
0.8
Falling time of clock and data
DATA setup time (Rising time of clock)
tf
tSHD
—
1.6
—
—
0.8
—
DATA setup time (Falling time of clock)
DATA hold time (“H” level)
tSLD
tHHD
1.6
1.6
—
—
—
—
DATA hold time (“L” level)
tHLD
1.6
—
—
Rev.1.0, Mar.23.2004, page 5 of 11
Units
µs
M61538FP
Power on Reset
This IC built-in the power on reset function.
The voltage of DVDD (5 pin) -DGND (8 pin) less than 2.6V, the serial DATA can not accept.
DVDD(5pin) - DGND(8pin)
(V)
2.6V
(S)
Reset time
After reset is canceled, the serial DATA can accept.
Release of reset.
Data Control Specification
Three types of input format can be selected by changing the D14/D15 slot setting status.
(Initialize all data of the 3 formats when power supply (DVDD) turn on.)
(1)
D0a D1a D2a D3a D4a D5a D6a D7a D8a D9a D10a D11a D12a D13a D14 D15
L Channel volume
(2)
R Channel volume
SW Channel volume
0
1
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14 D15
SL Channel volume
(4)
0
D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14 D15
C Channel volume
(3)
0
SR Channel volume
1
0
D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14 D15
Test Mode
Rev.1.0, Mar.23.2004, page 6 of 11
1
1
M61538FP
Setting Code
L/R/C/SW/SL/SR Channel Volume
It’s initial setting when DVDD turn on.
L
D0a
D1a
D2a
D3a
D4a
D5a
D6a
L
D0a
D1a
D2a
D3a
D4a
D5a
D6a
R
D7a
D8a
D9a
D10a
D11a
D12a
D13a
R
D7a
D8a
D9a
D10a
D11a
D12a
D13a
C
D0b
D1b
D2b
D3b
D4b
D5b
D6b
C
D0b
D1b
D2b
D3b
D4b
D5b
D6b
SW
D7b
D8b
D9b
D10b
D11b
D12b
D13b
SW
D7b
D8b
D9b
D10b
D11b
D12b
D13b
SL
D0c
D1c
D2c
D3c
D4c
D5c
D6c
SL
D0c
D1c
D2c
D3c
D4c
D5c
D6c
SR
D7c
D8c
D9c
D10c
D11c
D12c
D13c
SR
D7c
D8c
D9c
D10c
D11c
D12c
D13c
0dB
0
0
0
0
0
0
0
-48dB
0
1
1
0
0
0
0
-1dB
0
0
0
0
0
0
1
-49dB
0
1
1
0
0
0
1
-2dB
0
0
0
0
0
1
0
-50dB
0
1
1
0
0
1
0
-3dB
0
0
0
0
0
1
1
-51dB
0
1
1
0
0
1
1
-4dB
0
0
0
0
1
0
0
-52dB
0
1
1
0
1
0
0
-5dB
0
0
0
0
1
0
1
-53dB
0
1
1
0
1
0
1
-6dB
0
0
0
0
1
1
0
-54dB
0
1
1
0
1
1
0
-7dB
0
0
0
0
1
1
1
-55dB
0
1
1
0
1
1
1
-8dB
0
0
0
1
0
0
0
-56dB
0
1
1
1
0
0
0
-9dB
0
0
0
1
0
0
1
-57dB
0
1
1
1
0
0
1
-10dB
0
0
0
1
0
1
0
-58dB
0
1
1
1
0
1
0
-11dB
0
0
0
1
0
1
1
-59dB
0
1
1
1
0
1
1
-12dB
0
0
0
1
1
0
0
-60dB
0
1
1
1
1
0
0
-13dB
0
0
0
1
1
0
1
-61dB
0
1
1
1
1
0
1
-14dB
0
0
0
1
1
1
0
-62dB
0
1
1
1
1
1
0
-15dB
0
0
0
1
1
1
1
-63dB
0
1
1
1
1
1
1
-16dB
0
0
1
0
0
0
0
-64dB
1
0
0
0
0
0
0
-17dB
0
0
1
0
0
0
1
-65dB
1
0
0
0
0
0
1
-18dB
0
0
1
0
0
1
0
-66dB
1
0
0
0
0
1
0
-19dB
0
0
1
0
0
1
1
-67dB
1
0
0
0
0
1
1
-20dB
0
0
1
0
1
0
0
-68dB
1
0
0
0
1
0
0
-21dB
0
0
1
0
1
0
1
-69dB
1
0
0
0
1
0
1
-22dB
0
0
1
0
1
1
0
-70dB
1
0
0
0
1
1
0
-23dB
0
0
1
0
1
1
1
-71dB
1
0
0
0
1
1
1
-24dB
0
0
1
1
0
0
0
-72dB
1
0
0
1
0
0
0
-25dB
0
0
1
1
0
0
1
-73dB
1
0
0
1
0
0
1
-26dB
0
0
1
1
0
1
0
-74dB
1
0
0
1
0
1
0
-27dB
0
0
1
1
0
1
1
-75dB
1
0
0
1
0
1
1
-28dB
0
0
1
1
1
0
0
-76dB
1
0
0
1
1
0
0
-29dB
0
0
1
1
1
0
1
-77dB
1
0
0
1
1
0
1
-30dB
0
0
1
1
1
1
0
-78dB
1
0
0
1
1
1
0
-31dB
0
0
1
1
1
1
1
-79dB
1
0
0
1
1
1
1
-32dB
0
1
0
0
0
0
0
-80dB
1
0
1
0
0
0
0
-33dB
0
1
0
0
0
0
1
-81dB
1
0
1
0
0
0
1
-34dB
0
1
0
0
0
1
0
-82dB
1
0
1
0
0
1
0
-35dB
0
1
0
0
0
1
1
-83dB
1
0
1
0
0
1
1
-36dB
0
1
0
0
1
0
0
-84dB
1
0
1
0
1
0
0
-37dB
0
1
0
0
1
0
1
-85dB
1
0
1
0
1
0
1
-38dB
0
1
0
0
1
1
0
-86dB
1
0
1
0
1
1
0
-39dB
0
1
0
0
1
1
1
-87dB
1
0
1
0
1
1
1
-40dB
0
1
0
1
0
0
0
-88dB
1
0
1
1
0
0
0
-41dB
0
1
0
1
0
0
1
-89dB
1
0
1
1
0
0
1
-42dB
0
1
0
1
0
1
0
-90dB
1
0
1
1
0
1
0
-43dB
0
1
0
1
0
1
1
-91dB
1
0
1
1
0
1
1
-44dB
0
1
0
1
1
0
0
-92dB
1
0
1
1
1
0
0
-45dB
0
1
0
1
1
0
1
-93dB
1
0
1
1
1
0
1
-46dB
0
1
0
1
1
1
0
-94dB
1
0
1
1
1
1
0
-47dB
0
1
0
1
1
1
1
-95dB
1
0
1
1
1
1
1
-∞dB
1
1
1/0
1/0
1/0
1/0
1/0
Rev.1.0, Mar.23.2004, page 7 of 11
M61538FP
Electrical Characteristics (Supply current)
(Unless otherwise noted, Ta = 25°C, VCC(18pin) = 7V, VEE(19pin) = –7V, DVDD(5pin) = 5V, RL = 10kΩ)
Limits
Parameter
Symbol
Min
Typ
Max
Units
Test Condition
Positive Supply current
ICC
—
Negative Supply current
IEE
–20
11
20
mA
when no signal is provided
–11
—
mA
when no signal is provided
Digital Supply current
IDD
—
0.5
2
mA
when no signal is provided
Electrical Characteristics (Input/Output)
(Unless otherwise noted, Ta = 25°C, VCC(18pin) = 7V, VEE(19pin) = –7V, DVDD(5pin) = 5V, f = 1kHz, RL = 10kΩ)
Limits
Parameter
Symbol
Min
Typ
Max
Units
Test Condition
Input resistance
Rin
17
25
33
kΩ
13, 15, 17, 20, 22, 24pin,
Volume = 0 to –∞dB
Maximum output voltage
VOM
4.0
4.5
—
Vrms
Pass gain
Gv
–2
0
2
dB
2, 3, 4, 9, 10, 11pin output,
RL = 10kΩ, THD = 1%
13, 15, 17, 20, 22, 24pin input,
2, 3, 4, 9, 10, 11pin output
Distortion
THD
—
0.0012
0.009
%
BW = 400Hz to 30kHz,
Vi = 0.3Vrms, RL=10kΩ
Output noise voltage
Maximum attenuation
Vno
ATTmax
—
—
0.85
–120
8
–70
µVrms
dB
Volume = 0dB , Rg = 0Ω, IHF-A
Vi = 2Vrms, Volume = –∞dB, IHF-A
Volume gain between channels
Cross talk between channels
Dvol
CT
–1
—
0
–110
1
–70
dB
dB
Volume = 0, IHF-A
Vi = 2Vrms, RL = 10kΩ, IHF-A,
Rg = 0Ω
Rev.1.0, Mar.23.2004, page 8 of 11
M61538FP
Application Example 1
(±Power supplies used)
LIN
1µ
13
12
25K Vol
L
10 µ
14
RIN
11
10k
R
10µ
1µ
15
10
25K Vol
10k
C
10µ
16
CIN
9
17
25K
8
Vol
VCC 7V
0.1µ
10k
1µ
CLOCK
100µ 18
7
MCU I/F
0.1µ
100µ
Logic
19
VEE -7V
DATA
20
SWIN
MCU
6
1µ
25K Vol
5
VDD 5V
0.1µ
SW
10µ
21
100µ
4
10k
SL
10µ
22
SLIN
1µ
25K Vol
10k
SR
10µ
23
24
SRIN
3
1µ
2
25K Vol
10k
1
Units Resistance : Ω
Capacitance:F
Rev.1.0, Mar.23.2004, page 9 of 11
M61538FP
Application Example 2
(Single power supply used)
LIN
1µ
13
12
25K Vol
10k
14
RIN
11
10µ
L
10k
R
1µ
15
10
25K Vol
10µ
16
10k
C
9
10µ
CIN
1µ
17
VREF 5V
25K
8
Vol
VCC 10V
0.1µ
CLOCK
100µ
18
7
MCU I/F
0.1µ
Logic
19
100µ
MCU
6
DATA
20
SWIN
1µ
25K Vol
21
22
SLIN
1µ
5
VDD 5V
0.1µ
100µ
10µ
SW
10k
10 µ
SL
10k
10µ
SR
4
25K Vol
23
3
2
10k
24
SRIN
1µ
25K Vol
1
Units Resistance : Ω
Capacitance:F
Rev.1.0, Mar.23.2004, page 10 of 11
HE
G
Z1
e
1
24
z
Detail G
D
y
JEDEC Code
—
MMP
b
12
13
Weight(g)
0.2
Detail F
A2
A
Lead Material
Cu Alloy
L1
EIAJ Package Code
SSOP24-P-300-0.80
E
Rev.1.0, Mar.23.2004, page 11 of 11
A1
F
c
L
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
Symbol
e1
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
—
—
2.1
0
0.1
0.2
—
1.8
—
0.3
0.35
0.45
0.18
0.2
0.25
10.0
10.1
10.2
5.2
5.3
5.4
—
0.8
—
7.5
7.8
8.1
0.4
0.6
0.8
—
1.25
—
—
0.65
—
—
0.8
—
—
—
0.1
0˚
—
8˚
—
0.5
—
—
7.62
—
—
1.27
—
Recommended Mount Pad
e
Plastic 24pin 300mil SSOP
I2
24P2Q-A
M61538FP
Package Dimensions
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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