HD74HC195 4-bit Parallel-Access Shift Register REJ03D0590–0200 (Previous ADE-205-467) Rev.2.00 Jan 31, 2006 Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Parallel loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 13 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Type HD74HC195P DILP-16 pin Package Abbreviation P Taping Abbreviation (Quantity) — Function Table Clear Shift/ Load Clock Inputs Serial J K L X X X X H L H H L X L H H L H H H H H H H H H : high level (steady state) L : low level (steady state) X : don’t care Outputs A Parallel B C D QA X X X a X b X c X d L a X H L H L X X X X X X X X X X X X X X X X X X X X QA0 QA0 L H QAn QB L b QC L c QD L d QD H d QB0 QA0 QAn QAn QC0 QBn QBn QBn QBn QD0 QCn QCn QCn QCn QD0 QCn QCn QCn QCn QAn : transition from low to high level. a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively. QA0, QB0, QC0, QD0 : the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn : the level of QA, QB, QC or QD respectively before the most recent Rev.2.00 Jan 31, 2006 page 1 of 7 transition of the clock. HD74HC195 Pin Arrangement 16 VCC Clear 1 Serial Inputs Parallel Inputs Clear QA 15 QA K QB 14 QB A 4 A QC 13 QC B 5 B QD 12 QD C 6 C QD 11 QD D 7 D CK Shift/Load J 2 J K 3 Outputs 10 Clock 9 Shift/Load GND 8 (Top view) Timing Diagram Clock Clear Serial Inputs Shift/Load Parallel Data Inputs Outputs J K H L H L A B C D QA QB QC QD Serial Shift Clear Rev.2.00 Jan 31, 2006 page 2 of 7 Serial Shift Load HD74HC195 Logic Diagram K D C B VCC J A VCC Shift/ Load D C C Q CL CL D C C Q CL CL D C C Q CL CL D C C Q CL CL Clock Clear QD QD QC QB QA Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Jan 31, 2006 page 3 of 7 Symbol VCC VIN, VOUT Ta tr, tf Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V HD74HC195 Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Iin Quiescent supply current ICC 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Rev.2.00 Jan 31, 2006 page 4 of 7 Ta = 25°C Min Typ Max 1.5 — — 3.15 — — 4.2 — — — — 0.5 — — 1.35 — — 1.8 1.9 2.0 — 4.4 4.5 — 5.9 6.0 — 4.18 — — 5.68 — — — 0.0 0.1 — 0.0 0.1 — 0.0 0.1 — — 0.26 — — 0.26 — — ±0.1 — — 4.0 Ta = –40 to+85°C Unit Test Conditions Min Max 1.5 — V 3.15 — 4.2 — — 0.5 V — 1.35 — 1.8 1.9 — V Vin = VIH or VIL IOH = –20 µA 4.4 — 5.9 — 4.13 — IOH = –4 mA 5.63 — IOH = –5.2 mA — 0.1 V Vin = VIH or VIL IOL = 20 µA — 0.1 — 0.1 — 0.33 IOL = 4 mA — 0.33 IOL = 5.2 mA — ±1.0 µA Vin = VCC or GND — 40 µA Vin = VCC or GND, Iout = 0 µA HD74HC195 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Removal time trem Output rise/fall time tTLH tTHL 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 Input capacitance Cin 6.0 — Maximum clock frequency fmax Propagation delay time tPHL tPLH tPHL Pulse width tw Setup time tsu Hold time th Rev.2.00 Jan 31, 2006 page 5 of 7 Min — — — — — — — — — — — — 80 16 14 100 20 17 100 20 17 0 0 0 75 15 13 25 5 4 — — — — Ta = 25°C Ta = –40 to +85°C Unit Test Conditions Typ Max Min Max — 6 — 5 MHZ — 30 — 24 — 35 — 28 — 140 — 175 ns Clock to Q 13 28 — 35 — 24 — 30 — 140 — 175 ns 13 28 — 35 — 24 — 30 — 150 — 190 ns Clear to Q 15 30 — 38 — 26 — 33 — — 100 — ns Clock to Clear 7 — 20 — — — 17 — ns A, B, C, D, J, K to Clock — — 125 — 6 — 25 — — — 21 — ns Shift/Load to Clock — — 125 — 13 — 25 — — — 21 — — — 0 — ns Any input except Shift/Load –3 — 0 — — — 0 — ns Shift/Load to Clock — — 95 — 8 — 19 — — — 16 — ns Clear inactive to Clock — — 31 — 0 — 6 — — — 5 — — 75 — 95 ns 5 15 — 19 — 5 13 10 — — 16 10 pF HD74HC195 Test Circuit VCC VCC Output Clear See Function Table Input Pulse Generator Zout = 50 Ω Clock QA to QD S0 CL = 50 pF S1 Output R QD L A to D CL = 50 pF Note : 1. CL includes probe and jig capacitance. Waveforms • Waveform tr tf tw 90% 50% Clear VCC 90% 50% 10% trem tr tf 90% Clock 50% 10% tn 90% 50% 10% tw tn tn+1 0V tn+1 VCC 50% 50% 0V tsu th tsu th VCC Data 50% 50% 50% 50% 0V tsu tsu trem trem VCC 50% Shift / Load 50% 50% 50% 0V tPHL Q tPLH 90% 50% tPHL 90% 50% 10% tTHL VOH 90% 50% 10% tTLH tTHL Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. A clear pulse is applied prior to each test. 3. Propagation delay times (tPLH and tPHL ) are measured at tn+1. Proper shifting of data is verified at tn+4 with a functional test. 4. J and K inputs are tested the same as data A, B, C and D inputs except that Shift / Load input remains high. 5. tn : bit time before clocking transition. 6. tn+1 : bit time after one clocking transition. 7. tn+4 : bit time after four clocking transition. Rev.2.00 Jan 31, 2006 page 6 of 7 VOL HD74HC195 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e e bp Dimension in Millimeters Min D 19.2 E 6.3 A θ c e1 A1 0.51 b p 0.40 b 3 20.32 7.4 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 L Max 5.06 Z ( Ni/Pd/Au plating ) Rev.2.00 Jan 31, 2006 page 7 of 7 Nom 7.62 1 0.25 0.31 2.54 2.79 15° 1.12 2.54 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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