ETC 4250

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 4250 Group is a 4-bit single-chip microcomputer designed
with CMOS technology. Its CPU is that of the 720 series using a
simple instruction set. The computer is equipped with one 8-bit
timer which has a reload register and the interrupt function.
The various microcomputers in the 4250 Group include variations
of the built-in memory type as shown in the table below.
• Timer
Timer 1 ................................ 8-bit timer with a reload register
• Interrupt ................................................................... 2 sources
• CR oscillation circuit (Capacitor and Resistor connected
externally)
• Logic operation instruction
• RAM back-up function
• Key-on wakeup function (ports G and S, INT pin)
FEATURES
• Minimum instruction execution time ............................. 1.0 µs
(at 4.0 MHz system clock frequency, VDD=4.5 V to 5.5 V)
• Supply voltage
4.5 V to 5.5 V (at 4.0 MHz system clock frequency)
2.5 V to 5.5 V (at 1.0 MHz system clock frequency)
2.2 V to 5.5 V (at 1.0 MHz system clock frequency:
only for Mask ROM version)
Product
M34250M2-XXXFP
M34250E2-XXXFP *
ROM (PROM) size
(✕ 9 bits)
2048 words
2048 words
APPLICATION
Electric household appliances, consumer electronics products
(mouse, etc.)
RAM size
(✕ 4 bits)
Package
64 words
20P2N-A
Mask ROM
64 words
20P2N-A
One Time PROM
*: Shipped after writing (shipped in blank: M34250E2FP)
PIN CONFIGURATION (TOP VIEW)
M34250M2-XXXFP
1
20
D0
VSS
2
19
D1
XIN
3
18
D2/C
XOUT
4
17
D3/K
CNVSS
5
16
S0
RESET
6
15
S1
F0
7
14
S2
F1
8
13
S3
G0/INT
9
12
G3
G1/TOUT
10
11
G2
M34250M2-XXXFP
VD D
Outline 20P2N-A
ROM type
I/O port
2
(Note)
(64 words ✕ 4 bits)
RAM
(2048 words ✕ 9 bits)
ROM
Note: PROM 2048 words ✕ 9 bits
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register (SK) (4 levels)
Interrupt stack register (SDP) (1 level)
ALU (4 bits)
720 series
CPU core
Memory
XIN -XOUT
Port D
4
Timer 1 (8 bits)
Port S
4
System clock generating circuit
Port G
4
Timer
Internal peripheral functions
Port F
2
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Function
70
Minimum instruction execution time 1.0 µs (at 4.0 MHz system clock frequency) (Refer to the electrical characteristics because
the minimum instruction execution time depends on the supply voltage.)
Memory sizes ROM
M34250M2/ 2048 words ✕ 9 bits
RAM
Input/Output
ports
D0–D3
S0–S3
C
K
F0, F1
G0–G3
INT
TOUT
Timer
E2
I/O
64 words ✕ 4 bits
Four independent I/O ports; ports D2 and D3 are also used as ports C and K, respectively.
I/O
4-bit I/O port
I/O
I/O
1-bit I/O port; port C is also used as port D2.
1-bit I/O port; port K is also used as port D3.
I/O
2-bit I/O port
I/O
Input
4-bit I/O port; ports G0 and G1 are also used as pins INT and TOUT.
Interrupt input; INT pin is also used as port G0.
Output
Timer output; TOUT pin is also used as port G1.
Timer 1
Interrupt
Sources
Nesting
Oscillation circuit
8-bit timer with a reload register
2 (one for external and one for timer)
1 level
CR oscillation circuit (a capacitor and a resistor connected externally)
Frequency error: ±17 %
(VDD = 5 V ± 10 %, VDD = 3 V ± 10 %, the error of the external capacitor and resistor excluded)
Subroutine nesting
Device structure
Package
4 levels
CMOS silicon gate
Operating temperature range
20-pin plastic molded SOP (20P2N-A)
–20 °C to 85 °C
Supply voltage
2.2 V to 5.5 V (Refer to the electrical characteristics because the supply voltage depends on
Power
the system clock frequency.)
1.5 mA
Active mode
(at 4.0 MHz system clock frequency, VDD = 5 V, output transistors in the cut-off state)
dissipation
(typical value) RAM back-up mode 0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)
3
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Input/Output
Function
VDD
VSS
Power supply
Ground
—
—
Connected to a plus power supply.
Connected to a 0 V power supply.
CNVSS
CNVSS
—
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
RESET
XIN
Reset input
System clock input
XOUT
System clock output
Output
Then, pull up XIN pin through a resistor and pull down XOUT pin through a capacitor.
F 0 , F1
I/O port F
I/O
2-bit I/O port; for input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain.
G0–G3
I/O port G
I/O
4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
Input
Input
Reset pulse input pin
I/O pins of the system clock generating circuit. Connect pins XIN and XOUT directly.
structure is N-channel open-drain. Every pin of the ports has a key-on wakeup
function and a pull-up function. Both functions can be switched by software.
Ports G0 and G1 are also used as pins INT and TOUT, respectively.
S0–S3
I/O port S
I/O
4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain. Every pin of the ports has a key-on wakeup
function which can be switched by software. Also, it is used to perform the logic
D0–D3
I/O port D
I/O
operation using register A.
Each pin of port D has an independent 1-bit wide I/O function. For input use, set
the latch of the specified bit to “1.” The output structure is N-channel open-drain.
C
I/O port C
I/O
Ports D2 and D3 are also used as ports C and K, respectively.
1-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain. Port C has a pull-up function which can be
K
I/O port K
I/O
switched by software. It is also used as port D2.
1-bit I/O port. For input use, set the latch of the specified bit to “1.” The output
structure is N-channel open-drain. Port K has a pull-up function which can be
TOUT
Timer output
Output
INT
Interrupt input
Input
switched by software. It is also used as port D3.
TOUT pin has the function to output the timer 1 underflow signal divided by 2. It is
also used as port G1.
4
INT pin accepts an external interrupt. It also accepts the input signal to return the
system from the RAM back-up state. It is also used as port G0.
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MULTIFUNCTION
Pin
Multifunction
Pin
G0
G1
INT
TOUT
INT (Note 2)
TOUT (Note 2)
D2
C
C (Note 2)
Multifunction
G0
G1
D2
D3
K
K (Note 2)
D3
Notes 1: Pins except above have just single function.
2: The I/O of ports D2, D3 and G0, and the input of port G1 can be used even when ports C and K and pins INT and TOUT are
selected.
CONNECTIONS OF UNUSED PINS
Pin
F 0 , F1
G0/INT, G1/TOUT
G 2 , G3
S0–S3
Connection
Connect to VSS pin.
Open or connect to VSS pin. (Note 1)
Connection
Pin
D 0, D 1
Connect to VSS pin.
D2/C, D3/K
Open or connect to VSS pin. (Note 3)
Connect to VSS pin. (Note 2)
Notes 1: When pins G0/INT, G1/TOUT, G2 and G3 are connected to VSS pin, turn off their pull-up transistors (Pull-up control register
PU0=“✕02”) and also invalidate the key-on wakeup functions of pins G1/TOUT, G2 and G3 (Key-on wakeup contorl register
K0=“✕✕0✕2”) by software. When the POF instruction is executed while these pins are connected to VSS and the key-on
wakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediately
after going into the RAM back-up state. When these pins are open, turn on their pull-up transistors (Pull-up control register
PU0=“✕12”) by software.
2: When ports S0–S3 are connected to VSS pin, invalidate the key-on wakeup functions (Key-on wakeup contorl register
K0=“✕✕✕02”) by software. When the POF instruction is executed while these pins are connected to VSS and the key-on
wakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediately
after going into the RAM back-up state.
3: When ports D2 /C and D3/K are connected to VSS pin, turn off their pull-up transistors (register PU0=“0✕2”) by software.
When these pins are open, turn on their pull-up transistors (register PU0=“1✕2”) by software.
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
5
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT FUNCTION
Port
Port D
Pin
D 0, D 1
D2/C
Input/
Output
I/O
Output structure
N-channel open-drain
Control
Control
Control
bits
1
instructions
SD
registers
RD
(4)
PU0
Pull-up function
(programmable)
IAK
OSA
K0
Logic operation function
IAS
LO
(programmable)
Key-on wakeup functions
SZD
CLD
D3/K
Remark
SCP
RCP
SNZCP
OKA
Port S
S0–S3
I/O
N-channel open-drain
4
(4)
LGOP
(programmable)
Port G
G0/INT
I/O
(4)
N-channel open-drain
4
OGA
PU0, K0
IAG
Pull-up functions
Key-on wakeup functions
(only pull-up function is
Port F
G1/TOUT
PU0, K0
V1
G 2, G 3
PU0, K0
F 0, F 1
I/O
(2)
N-channel open-drain
DEFINITION OF CLOCK AND CYCLE
• System clock
This is the source clock input to the XIN pin. Connect pins XIN
and XOUT directly. Then, pull up XIN pin through a resistor and
pull down XOUT pin through a capacitor.
• Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling this product.
• Machine cycle
One machine cycle is the time required to execute the minimum
instruction (one-cycle instruction). The machine cycle is
equivalent to the instruction clock cycle.
6
2
OFA
IAF
programmable)
Pull-up functions
(programmable)
Key-on wakeup functions
(programmable)
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
I/O PORT
(1) Port D (D0–D3)
Each pin of port D has an independent 1-bit wide I/O function.
Each pin has an output latch. For input/output of ports D0–D3,
select one of port D with the register Y of data pointer first. For
input use, set the latch of the specified bit to “1.” All port D
output latches can be set to “1” with the CLD instruction. The
output structure is the N-channel open-drain. Ports D2 and D3
are also used as ports C and K, respectively. Accordingly,
when port D2/C is used as port D2, set the port C output latch
to “1.” When port D3/K is used as port D3, set the port K output
latch to “1.”
(2) Port C
1-bit I/O port.
Port C output latch can be set to “1” with the SCP instruction.
Port C output latch can be cleared to “0” with the RCP
instruction. Port C input level can be examined by executing
the skip (SNZCP) instruction. For input use, set the latch of
the specified bit to “1.” The output structure is the N-channel
open-drain. The pull-up transistor of port C is turned on when
the bit 1 of register PU0 is set to “1” by software. Port C is also
used as port D2. Accordingly, when port D2/C is used as port
C, set the port D2 output latch to “1.”
(3) Port K
1-bit I/O port.
For input use, set the latch of the specified bit to “1.” The
output structure is the N-channel open-drain. The pull-up
transistor of port K is turned on when the bit 1 of register PU0
is set to “1” by software. Port K is also used as port D3.
Accordingly, when port D3/K is used as port K, set the port D3
output latch to “1.”
(4) Port G (G0–G3)
4-bit I/O port.
For input use, set the latch of the specified bit to “1.” The
output structure is the N-channel open-drain. The pull-up
transistor of port G is turned on when the bit 0 of register PU0
is set to “1” by software. Ports G0 and G1 are also used as INT
pin and TOUT pin, respectively.
Pull-up control register
Pull-up control register PU0
PU01
PU00
Ports C and K
pull-up transistor control bit
Ports G0–G3
pull-up transistor control bit
Note: “W” represents write enabled.
at reset : 002
at RAM back-up : state retained
0
1
Pull-up transistor OFF
Pull-up transistor ON
0
Pull-up transistor OFF
1
Pull-up transistor ON
W
7
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(5) Port F (F0, F1)
2-bit I/O port.
For input use, set the latch of the specified bit to “1.” The output
structure is the N-channel open-drain.
(6) Port S (S0–S3)
4-bit I/O port.
Port S has the logic operation (LGOP) function. For input (logic
operation included) use, set the latch of the specified bit to
“1.” The output structure is the N-channel open-drain. When
performing the logic operation, select the logic operation
function with the logic operation selection register LO. Set the
contents of register LO through register A with the TLOA
instruction.
When the LGOP instruction is executed, the logic operation
selected with the register LO is performed between the
contents of register A and the contents of port S, and its result
is stored in register A.
Logic operation selection register
Logic operation selection register LO
LO1
Logic operation function selection bits
LO0
Note: “W” represents write enabled.
8
at reset : 002
LO1 LO0
0 XOR operation
0
1 OR operation
0
1
1
0 AND operation
1 Not available
at RAM back-up : 002
Functions
W
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS
Skip decision
(SZD instruction)
Decoder
Register Y
CLD
instruction
D0, D1
S
SD instruction
R Q
RD instruction
(Note 1)
IAF instruction
F0, F1
Register A
Aj
Pull-up transistor
(Note 3)
D Q
OFA
instruction T
(Note 1)
Register Y
PU01
Decoder
CLD
instruction
S
SD instruction
R Q
RD instruction
SCP instruction
S
RCP instruction
R Q
(Note 1)
Skip decision
(SNZCP instruction)
Skip decision
(SZD instruction)
D2/C
Key-on wakeup
input
K00
LO Register
LGOP instruction
Logic
operator
(Note 2)
Ai
IAS instruction
Pull-up transistor
S0–S3
Register A
D Q
Ai
Register Y
PU01
Decoder
(Note 1)
(Note 2)
T
(Note 1)
IAK instruction
CLD
instruction
OSA instruction
Register A
S
SD instruction
R Q
RD instruction
A0
OKA instruction
Skip decision
(SZD instruction)
D3/K
D
T Q
Notes 1:
This symbol represents
a parasitic diode.
Applied potential to ports D0, D1, F0, F1, S0–S3
must be 7V or less.
Applied potential to ports D2, D3 must be VDD or
less.
2: i represents 0, 1, 2 or 3.
3: j represents 0 or 1.
9
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (CONTINUED)
K02
Pull-up transistor
Rising
0
External interrupt
One-sided edge
detection circuit
EXF0
(Note 1)
1
Key-on wakeup
input
PU00
Falling
IAG instruction
G0/INT
Register A
A0
D Q
OGA instruction
T
Pull-up transistor
K01
Key-on wakeup
input
(Note 1)
PU00
IAG instruction
G1/TOUT
Register A
Timer 1 underflow
signal output
A1
OGA instruction
1/2
D Q
1
0
V13
T
Pull-up transistor
K01
Key-on wakeup
input
(Note 1)
PU00
IAG instruction
G2, G3
Register A
(Note 2) Ak
OGA instruction
D Q
T
This symbol represents
a parasitic diode.
Applied potential to ports G0–G3
must be VDD or less.
2: k represents 2 or 3.
Notes 1:
10
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, and bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(M(DP))
Addition
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
ALU
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
TAB instruction
Register B
B3 B2 B1 B0
Register A
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
A3 A2 A1 A0
TBA instruction Register A
Register B
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
Specifying address
PCH
PCL
p3 p2 p1 p0
DR2 DR1 DR0 A3 A2 A1 A0
8
4
0
Low-order 4 bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field The contents of The contents of
value p
register D
register A
Fig. 4 TABP p instruction execution example
11
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(5) Stack registers (SKs) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents
of program counter (PC) just before branching until returning
to the original routine when;
• branching to an interrupt service routine (referred to as an
interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used respectively when using an interrupt
service routine and when executing a table reference
instruction. Accordingly, be careful not to over the stack when
performing these operations together. The contents of registers
SKs are destroyed when 4 levels are exceeded.
The register SK nesting level is pointed automatically by 2-bit
stack pointer (SP).
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an
interrupt occurs, this register (SDP) is used to temporarily store
the contents of data pointer, carry flag and skip flag just before
an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table
reference instruction.
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions. When
an interrupt occurs, the contents of skip flag is stored
automatically in the interrupt stack register (SDP) and the skip
condition is retained.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
Stack pointer (SP) points “3” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after four
stack registers are used ((SP) = 3), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP)
(SK0)
(PC)
0
000116
SUB1
Subroutine
Main program
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC)
(SP)
(SK0)
3
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
12
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not exceed after the last page of
the built-in ROM.
Program counter (PC)
p3 p2 p1 p0
PCH
Specifying
page
a6 a5 a4 a3 a2 a1 a0
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and
consists of registers X and Y. Register X specifies a file and
register Y specifies a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure
9).
Specifying
RAM digit
Register Y (4)
Register X (2)
Specifying RAM file
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D3
0
0
1
D2
0
Register Y (4)
D1
D0
1
Port D output latch
Fig. 9 SD instruction execution example
13
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is
composed of 9 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127). Table 1 shows the ROM size
and pages. Figure 10 shows the ROM map of M34250M2.
Table 1 ROM size and pages
Product
ROM size (✕ 9 bits)
Pages
2048 words
16 (0 to 15)
M34250M2
M34250E2
A part of page 1 (addresses 008016 to 00FF16) is reserved for
interrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is
set in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
Page 2 (addresses 0100 16 to 017F16 ) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data
areas with the TABP p instruction.
DATA MEMORY (RAM)
M34250M2
6
5
4
3
2
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
Page 15
07FF16
Fig. 10 ROM map of M34250M2
008016
8 7 6 5 4 3 2 1 0
External interrupt address
008216
Timer 1 interrupt address
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
RAM 64 words ✕ 4 bits (256 bits)
Register X 0 1 2 3
RAM size
64 words ✕ 4 bits (256 bits)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
64 words
Fig. 12 RAM map
14
1 0
Page 0
Register Y
M34250E2
7
00FF16
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers X and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size
Product
8
000016
007F16
008016
00FF16
010016
017F16
018016
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an
individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3
conditions are satisfied.
• An interrupt activated condition is satisfied
(request flag = “1”)
• Interrupt enable bit = “1”
(interrupt request occurrence enabled)
• Interrupt enable flag (INTE) = “1” (interrupt enabled)
Table 3 shows interrupt sources. (Refer to each interrupt
request flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the
every interrupt enable/disable. Interrupts are enabled
when INTE flag is set to “1” with the EI instruction and
disabled when INTE flag is cleared to “0” with the DI
instruction. When any interrupt occurs, the INTE flag is
automatically cleared to “0,” so that other interrupts
are disabled until the EI instruction is executed.
Table 3 Interrupt sources
Priority
Activated condition
Interrupt name
level
1
2
Interrupt
address
External interrupt Level change of INT Address 0
in page 1
pin
Address 2
Timer 1 interrupt Timer 1 underflow
in page 1
Table 4 Interrupt request flag, interrupt enable bit and
skip instruction
Interrupt name Request flag Enable bit Skip instruction
EXF0
V10
SNZ0
External interrupt
Timer 1 interrupt
T1F
V11
Table 5 Interrupt enable bit function
Occurrence of
Interrupt enable bit
interrupt request
Enabled
1
0
Disabled
SNZ1
Skip instruction
Invalid
Valid
(2) Interrupt enable bit (V1 0 , V1 1 )
Use an interrupt enable bit of interrupt control register
V1 to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction.
Table 5 shows the interrupt enable bit function.
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to
“1.” Each interrupt request flag is cleared to “0” when
either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated
condition is satisfied even if the interrupt is disabled
by the INTE flag or its interrupt enable bit. Once set,
the interrupt request flag retains set until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag
is set.
If more than one interrupt request flag is set when the
interrupt disable state is released, the interrupt priority
level is as follows shown in Table 3.
15
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The
address to be executed when returning to the main
routine is automatically stored in the stack register
(SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source
is cleared to “0.”
• Data pointer, carry flag and skip flag
The contents of these pointer and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt
address is executed after branching a data store sequence to stack register. Write the branch instruction
to an interrupt service routine at an interrupt address.
Use the RTI instruction to return to main routine.
Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next
instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction,
interrupts are enabled after returning the main routine.
(Refer to Figure 13)
Main routine
Interrupt
service routine
Interrupt
occurs
Interrupt
is enabled
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
16
• Program counter (PC) ........... Each interrupt address
• Stack register (SK)
The address of main routine to
be executed when returning
• Interrupt enable flag (INTE) ...... 0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source) ...................................................................... 0
• Data pointer, carry flag, skip flag
......... Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
(L→H or
H→L input)
Timer 1
underflow
Activated
condition
EXF0
Address 0
in page 1
V10
T1F
V11
Request flag
(state retained)
Enable
bit
Fig. 15 Interrupt system diagram
Address 2
in page 1
Enable
flag
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Control register related to interrupt
• Timer control register V1
Interrupt enable bits of external and timer 1 are assigned
to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction
can be used to transfer the contents of register V1 to register
A.
Table 6 Control register related to interrupt
Timer control register V1
at reset : 00002
V13
G1/TOUT pin function selection bit
V12
Prescaler/timer 1 operation start bit
V11
Timer 1 interrupt enable bit
V10
External interrupt enable bit
at RAM back-up : 00002
0
Port G1 (I/O)
1
TOUT pin (output)/port G1(input)
0
1
Prescaler stop (initial state) / timer 1 stop (state retained)
Prescaler / timer 1 operation
0
Interrupt disabled (SNZ1 instruction is valid)
1
0
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
R/W
Note: “R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10, V11), and interrupt request flags (EXF0, T1F)
are “1.” The interrupt actually occurs 2 to 3 machine cycles
after the cycle in which all three conditions are satisfied. The
interrupt occurs after 3 machine cycles only when the three
interrupt conditions are satisfied on execution of other than
one-cycle instructions (Refer to Figure 16).
● When an interrupt request flag is set after its interrupt is enabled
1 machine cycle
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
T1 T2 T3 T4
f (XIN)
Interrupt enable
flag (INTE)
EI instruction
execution cycle
Interrupt disabled state.
Interrupt enabled state.
Retaining level for 5 cycles or more
of f(XIN) is necessary.
G0/INT pin
External
interrupt
EXF0 flag
Interrupt activated
condition is satisfied.
Timer 1
interrupt
T1F flag
Flag cleared
Software starts from
the interrupt address.
2 to 3 machine cycles
(Notes 1, 2)
Notes 1: The address is stacked to the last cycle.
2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
17
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
EXTERNAL INTERRUPTS
The 4250 Group has an external interrupt. An external interrupt
request occurs when a valid waveform is input to an interrupt
input pin (edge detection).
The external interrupt can be controlled with the key-on wakeup
control register K0.
Table 7 External interrupt activated condition
Name
Valid waveform
Input pin
G0/INT
External interrupt
Falling waveform (“H”→“L”)
1
Rising waveform (“L”→“H”)
0
K02
0
External interrupt
Valid waveform selection bit(K02)
Pull-up transistor
Rising
One-sided
edge detection
circuit
EXF0
(Note)
1
Key-on wakeup
input
PU00
Falling
IAG instruction
G0/INT pin
Register A
A0
OGA instruction
D Q
T
Note:
Fig. 17 External interrupt circuit structure
18
This symbol represents a
parasitic diode.
Applied potential to port G0 must be VDD
or less.
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) External interrupt request flag (EXF0)
External interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to G0/INT pin.
The valid waveforms causing the interrupt must be retained
at their level for 5 cycles or more of f(XIN) (Refer to Figure
16).
The state of EXF0 flag can be examined with the skip
instruction (SNZ0). Use the timer control register V1 to select
the interrupt or the skip instruction. The EXF0 flag is cleared
to “0” when an interrupt occurs or when the next instruction is
skipped with the skip instruction.
(2) Control register related to external interrupt
• Key-on wakeup control register K0
Register K0 controls the valid waveform for the external
interrupt and key-on wakeup function. Set the contents of
this register through register A with the TK0A instruction.
The TAK0 instruction can be used to transfer the contents
of register K0 to register A.
• External interrupt activated condition
External interrupt activated condition is satisfied when a
valid waveform is input to G0/INT pin.
The valid waveform can be selected from rising waveform
or falling waveform. An example of how to use the external
interrupt is as follows.
➀ Select the valid waveform with the bit 2 of register K0.
➁ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➂ Set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction.
➃ Set both the external interrupt enable bit (V10) and the INTE
flag to “1.”
The external interrupt is now enabled. Now when a valid
waveform is input to the G0/INT pin, the EXF0 flag is set to “1”
and the external interrupt occurs.
Table 8 Control register related to external interrupt
Key-on wakeup control register K0
K03
Prescaler dividing ratio selection bit
K02
Interrupt valid waveform for INT pin/
key-on wakeup valid waveform selection
bit (Note 2)
K01
Ports G1–G3 key-on wakeup control bit
K00
Ports S0–S3 key-on wakeup control bit
at reset : 00002
0
1
0
at RAM back-up : state retained
Instruction clock divided by 4
Instruction clock divided by 512
Rising waveform (“L” → “H”)
1
Falling waveform (“H” → “L”)
0
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
1
0
1
R/W
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least
one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when
the interrupt valid waveform is changed.
19
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TIMERS
The 4250 Group has the programmable timer.
• Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer
interrupt request flag is set to “1,” new data is loaded from the
reload register, and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 interrupt
request flag
An interrupt occurs or
a skip instruction is executed.
Fig. 18 Auto-reload function
20
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
The 4250 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer with the interrupt function
These timers can be controlled with the timer control register V1
and key-on wakeup control register K0.
Each function is described below.
Table 9 Function related timers
Circuit
Instruction clock
Frequency
Use of output signal
dividing ratio
4, 512
• Timer 1 count source
Prescaler output (ORCLK)
1 to 256
Count source
Structure
Prescaler
Frequency divider
Control
register
V1
K0
Timer 1
8-bit programmable
binary down counter
V1
• TOUT pin
• Timer 1 interrupt
Prescaler
V12
K03
1/4
0
1
1/512
0
V12(Note)
0
ORCLK
1
Bit 7
Timer 1 (8)
Timer 1 underflow
signal
Bit 0
1
Timer 1 reload register R 1(8)
1/2
T1AB
instruction
Instruction clock
Register B(4)
TAB1 instruction
Internal clock
generating circuit
(divided by 4)
Timer 1
interrupt
T1F
V13
1
Register A(4)
TAB1
instruction
G1 output
G1/ TOUT
0
G1 input
Note: Count source is stopped by clearing to “0.”
XIN
: Data is automatically set from a reload register
when timer 1 underflows (auto-reload function).
Fig. 19 Timers structure
21
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 10 Control registers related to timer
Timer control register V1
V13
G1/TOUT pin function selection bit
V12
Prescaler/timer 1 operation start bit
V11
Timer 1 interrupt enable bit
V10
External interrupt enable bit
0
Port G1 (I/O)
1
TOUT pin (output)/port G1(input)
0
1
Prescaler stop (initial state) / timer 1 stop (state retained)
Prescaler / timer 1 operation
0
Interrupt disabled (SNZ1 instruction is valid)
1
0
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Key-on wakeup control register K0
K03
Prescaler dividing ratio selection bit
Interrupt valid waveform for INT pin/
K02
key-on wakeup valid waveform selection
bit (Note 2)
K01
Ports G1–G3 key-on wakeup control bit
K00
Ports S0–S3 key-on wakeup control bit
at RAM back-up : 00002
at reset : 00002
at reset : 00002
at RAM back-up : state retained
0
1
Instruction clock divided by 4
Instruction clock divided by 512
0
Rising waveform (“L” → “H”)
1
Falling waveform (“H” → “L”)
0
1
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
0
Key-on wakeup not used
1
Key-on wakeup used (“L” level recognized)
R/W
R/W
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least
one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when
the interrupt valid waveform is changed.
22
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Control registers related to timer
• Timer control register V1
G1 /TOUT pin function selection bit and prescaler/timer 1
operation start bit are assigned to register V1. Set the
contents of this register through register A with the TV1A
instruction. The TAV1 instruction can be used to transfer
the contents of register V1 to register A.
• Key-on wakeup control register K0
Prescaler dividing ratio selection bit is assigned to register
K0. Set the contents of this register through register A with
the TK0A instruction. The TAK0 instruction can be used to
transfer the contents of register K0 to register A.
(5) Timer output pin (G1/TOUT)
Timer output pin (G1/TOUT) has the function to output the timer
1 underflow signal divided by 2. The selection of G1/TOUT pin
function can be controlled with the bit 3 of register V1.
(6) Timer interrupt request flag (T1F)
Timer interrupt request flag is set to “1” when the timer
underflows. The state of this flag can be examined with the
skip instruction (SNZ1).
Use the register V1 to select an interrupt or a skip instruction.
T1F flag is cleared to “0” when an interrupt occurs or when the
next instruction is skipped with a skip instruction.
(2) Precautions
Note the following for the use of timers.
• Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
• Reading the count value
Stop timer 1 counting and then execute the TAB1 instruction
to read its data.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio
can be selected. The count source of prescaler is the
instruction clock.
Use the bit 3 of register K0 to select the prescaler dividing
ratio and the bit 2 of register V1 to start and stop its operation.
Prescaler is initialized, and the output signal (ORCLK) stops
when the bit 2 of register V1 is cleared to “0.”
(4) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1). Data can be set simultaneously in timer 1 and
the reload register (R1) with the T1AB instruction.
Timer 1 starts counting after the following process;
➀ set data in timer 1, and
➁ set the bit 2 of register V1 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (autoreload function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B with the
TAB1 instruction. When reading the data, stop the counter
and then execute the TAB1 instruction. Timer 1 underflow
signal divided by 2 can be output from G1/TOUT pin.
23
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RESET FUNCTION
System reset is performed by applying “L” level to RESET pin
for 1 machine cycle or more when the following condition is
satisfied;
• the value of supply voltage is the minimum value or more of
the recommended operating conditions.
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
f(XIN)
RESET
Software starts
(address 0 in page 0)
3584 to 3585 machine cycles
The number of clock cycles depends on the
internal state of the microcomputer when
reset is performed.
Fig. 20 Reset release timing
=
Reset input
1 machine cycle or more
3584 to 3585 machine cycles
0.85VDD
Software starts
(address 0 in page 0)
RESET
0.1VDD
(Note)
Note : Keep the value of supply voltage the minimum value or more
of the recommended operating conditions.
Fig. 21 RESET pin input waveform and reset operation
24
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Power-on reset
Reset can be automatically performed at power on (power-on
reset) by connecting a resistor, a diode, and a capacitor to
RESET pin. Connect RESET pin and the external circuit at the
shortest distance.
VDD
VDD
RESET pin voltage
Internal reset
signal
RESET
pin
Reset state
Internal reset signal
This symbol represents a parasitic diode.
Note: Applied potential to RESET pin
must be 7 V or less.
Reset released
Power-on
Fig. 22 Power-on reset circuit example
(2) Internal state at reset
Table 11 shows port state at reset, and Figure 23 shows
internal state at reset (they are retained after system is released
from reset).
Table 11 Port state at reset
Function
Name
D0, D1, D2/C, D3/K
D0, D1, D2/C, D3/K
S0–S3
G0/INT, G1/TOUT
S0–S3
G0/INT, G1
G 2 , G3
G 2, G 3
F 0 , F1
F 0 , F1
The contents of timers, registers, flags and RAM except shown
in Figure 23 are undefined, so set the initial value to them.
State
High impedance
(Note)
Note: Output latch is set to “1.”
25
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
• Program counter (PC) .............................................................. 0
Address 0 in page 0 is set to program counter.
0
0
0
0
0
0
• Interrupt enable flag (INTE) ..................................................... 0
(Interrupt disabled)
0
0
0
0
• Power down flag (P) ................................................................. 0
• External interrupt request flag (EXF0) ..................................... 0
• Timer 1 interrupt request flag (T1F) ........................................ 0
• Timer control register V1 ......................................................... 0
0
0
0
(Interrupt disabled, prescaler/timer 1 stopped)
• Key-on wakeup control register K0 ......................................... 0 0 0 0
• Pull-up control register PU0 ..................................................... 0
• Logic operation selection register LO ...................................... 0
• Carry flag (CY) ......................................................................... 0
0
• Register A ................................................................................. 1
• Register B ................................................................................. 1
• Stack pointer (SP) .................................................................... 1
1
1
1
1
1
1
1
Fig. 23 Internal state at reset
26
0
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
The 4250 Group has the RAM back-up mode.
When the POF instruction is executed continuously, system
enters the RAM back-up state.
As oscillation stops retaining RAM, the function of reset circuit
and states at RAM back-up mode, current dissipation can be
reduced without losing the contents of RAM. Table 12 shows
the function and states retained at RAM back-up. Figure 24 shows
the state transition.
Table 12 Functions and states retained at RAM back-up
RAM back-up
Function
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port
Timer control register V1
Timer 1 function
Pull-up control register PU0
(1) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
(2) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF instruction
continuously, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
(3) Cold start condition
The CPU starts executing the software from address 0 in page
0 when reset pulse is input to RESET pin.
In this case, the P flag is “0.”
Key-on wakeup control register K0
Logic operation selection register LO
External interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Interrupt enable flag (INTE)
✕
O
✕
✕
✕
O
O
✕
✕
✕
✕
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “3” at RAM back-up.
(4) Return signal
An external wakeup signal is used to return from the RAM
back-up mode. Table 13 shows the return condition for each
return source.
Table 13 Return source and return condition
Return source
G0/INT pin
Return condition
Remarks
Return by an external rising edge Select the return edge (rising edge or falling edge) with the bit 2 of register
input (“L”→“H”) or falling edge K0 according to the external state before going into the RAM back-up
input (“H”→“L”).
The EXF0 flag is not set.
state.
Ports G1–G3
Return by an external “L” level Set the port using the key-on wakeup function selected with register K0
S0–S3
input.
to “H” level before going into the RAM back-up state.
Note: G0/INT pin and ports G1–G3, S0–S3 share the circuit which is used to detect the edge and to recognize “L” level.
The G0/INT pin cannot be set to “no key-on wakeup.”
27
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
of this register through register A with the TK0A instruction.
The TAK0 instruction can be used to transfer the contents
of register K0 to register A.
(5) Key-on wakeup control register K0
• Key-on wakeup control register K0
The interrupt valid waveform for INT pin/key-on wakeup
valid waveform selection bit, the ports G 1 –G 3 key-on
wakeup control bit and the ports S 0 –S 3 key-on wakeup
control bit are assigned to the register K0. Set the contents
Table 14 Key-on wakeup control register
Key-on wakeup control register K0
K03
at reset : 00002
Prescaler dividing ratio selection bit
Interrupt valid waveform for INT pin/
K02
key-on wakeup valid waveform selection
bit (Note 2)
K01
Ports G1–G3 key-on wakeup control bit
K00
Ports S0–S3 key-on wakeup control bit
at RAM back-up : state retained
0
1
Instruction clock divided by 4
Instruction clock divided by 512
0
Rising waveform (“L” → “H”)
1
Falling waveform (“H” → “L”)
0
1
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
0
Key-on wakeup not used
R/W
Key-on wakeup used (“L” level recognized)
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one
instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set when the
interrupt valid waveform is changed.
POF instruction
is executed
A
B
f(XIN) stop
(Stabilizing time a )
Reset
f(XIN) oscillation
Return input
(Stabilizing time a )
(RAM back-up
mode)
Stabilizing time a : Microcomputer starts its operation after 3584 to 3585 machine cycles for the time
required to stabilize the f(XIN) oscillation.
Fig. 24 State transition
Power down flag P
POF instruction
S
Reset input
R
Q
Software start
P = “1”
?
Yes
No
● Set source
● Clear source
POF instruction is executed
Reset input
Fig. 25 Set source and clear source of the P flag
28
Cold start
Warm start
Fig. 26 Start condition identified example using the SNZP
instruction
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to return from the RAM back-up state
XIN
Oscillation
circuit
XOUT
Internal clock
generating circuit
(divided by 4)
Instruction clock
Counter
Wait time control
circuit (Note)
Software
start signal
RESET
POF instruction
R
S
Key-on wakeup control register
K00, K0 1
Q
Multiplexer
Ports G 1–G3
Ports S 0–S3
K02 Rising
G0/INT pin
0
Rising detected
1
Falling
Note: The wait time control circuit is used to start the microcomputer operation after 3584 to 3585 machine cycles
for the time required to stabilize the f(XIN) oscillation.
Fig. 27 Clock control circuit structure
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) M34250M2-XXXFP Mask ROM Order Confirmation Form
..............................................................................................1
(2) Data to be written into mask ROM ......................... EPROM
(three sets containing the identical data)
(3) Mark Specification Form ..................................................... 1
XIN
XOUT
M34250M2-XXXFP
Clock signal f(XIN) is obtained by connecting XIN pin and XOUT
pin directly, and externally connecting a resistor to XIN and a
capacitor to XOUT. Connect this external circuit to pins XIN and
XOUT at the shortest distance.
When an external clock signal is input, note the input waveform
(refer to the list of precaution).
The system clock frequency
is affected by a capacitor, a
resistor and an LSI, So, set
the constants within the
range of the frequency limits.
Fig. 28 Resistor and capacitor external circuit
29
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.01 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the One Time PROM version, CNVSS pin is also used as
VPP pin. Connect this pin to VSS through the resistor about
5 kΩ which is assigned to CNV SS /V PP pin as close as
possible at the shortest distance.
➁ Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
➂ Timer count source
Stop timer 1 counting to change its count source.
➃ Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
➄ G0/INT pin
When the interrupt valid waveform of the G0/INT pin is changed
with the bit 2 of register K0 in software, be careful about the
following notes.
• After clear the bit 0 of register V1 to “0” (Figure 29➀),
change the interrupt valid waveform of G0/INT pin with the
bit 2 of register K0 .
• Set a value to bit 2 of register K0 and execute the SNZ0
instruction to clear the external interrupt request flag (EXF0)
after executing at least one instruction (refer to Figure 29➁).
Depending on the input state of the G0/INT pin, the EXF0
flag may be set when the interrupt valid waveform is
changed.
...
LA 4
; (✕✕✕02)
TV1A
LA 4
; The SNZ0 instruction is valid ............. ➀
TK0A
; Change of the interrupt valid waveform
NOP
SNZ0
.............................................................. ➁
; The SNZ0 instruction is executed
NOP
...
✕ : this bit is not related to the setting of G0/INT pin.
Fig. 29 External interrupt program example
30
➅ Notes on unused pins
• When pins G0/INT, G1/TOUT, G2 and G3 are connected to
VSS pin, turn off their pull-up transistors (register PU0=“✕02”)
and also invalidate the key-on wakeup functions of pins
G1/TOUT, G 2 and G3 (register K0=“✕✕0✕2”) by software.
When the POF instruction is executed while these pins are
connected to VSS and the key-on wakeup functions are left
valid, the system returns from RAM back-up state by
recognizing the return condition immediately after going into
the RAM back-up state. When these pins are open, turn on
their pull-up transistors (register PU0=“✕12”) by software.
• When ports S0–S3 are connected to VSS pin, invalidate the
key-on wakeup functions (register K0=“✕✕✕0 2 ”) by
software. When the POF instruction is executed while these
pins are connected to VSS and the key-on wakeup functions
are left valid, the system returns from RAM back-up state
by recognizing the return condition immediately after going
into the RAM back-up state.
• When ports D2/C and D3/K are connected to VSS pin, turn
off their pull-up transistors (register PU0=“0✕2”) by software.
When these pins are open, turn on their pull-up transistors
(register PU0=“1✕2”) by software.
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS or VDD at the shortest distance
(within 20 mm) and use the thick wire against noise.
➆ Multifunction
• G0/INT pin can be also used as an I/O port G0 even when it
is used as INT pin.
• G1/TOUT pin can be also used as input port G1 even when it
is used as TOUT pin.
• D2 /C pin can be also used as I/O port D2 even when it is
used as port C.
• D3 /K pin can be also used as I/O port D3 even when it is
used as port K.
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
➇ Key-on wakeup
When system returns from RAM back-up state by using the
G0/INT pin, select the return edge (rising edge or falling edge)
with the bit 2 of register K0 according to the external state
before going into the RAM back-up state.
When system returns from RAM back-up state by using the
ports G1–G3 and S0–S3, set the port using the key-on wakeup
function selected with register K0 to “H” level before going into
the RAM back-up state.
G0/INT pin and ports G1–G3, S0–S3 share the circuit which is
used to detect the edge and to recognize “L” level.
The G0/INT pin cannot be set to “no key-on wakeup.”
➈ External clock input waveform
When the external clock is used, open XOUT pin, and input the
clock waveform into XIN pin shown below. (Refer to Figure 30)
•Duty ratio = 50 %.
•“H” level input voltage=VDD (V), “L” level input voltage=VSS (V).
VDD(V)
VSS(V)
t/2 (S)
t/2 (S)
t (S)
Fig. 30 External clock input waveform
➉ CR oscillation constant
Use the external 30 pF capacitor and enable to change the
frequency by the external resistor.
Test the system sufficiently because the oscillation constant
depends on the ROM type (mask ROM or PROM).
31
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Contents
Symbol
Contents
Symbol
A
Register A (4 bits)
D
Port D (4 bits)
B
Register B (4 bits)
Register D (3 bits)
F
Port F (2 bits)
Port G (4 bits)
DR
E
V1
K0
PU0
Register E (8 bits)
Timer control register V1 (4 bits)
Key-on wakeup control register K0 (4 bits)
G
S
K
C
Port S (4 bits)
Port K (1 bit)
Port C (1 bit)
Pull-up control register PU0 (2 bits)
Logic operation selection register LO (2 bits)
x
X
Register X (2 bits)
y
p
Y
Register Y (4 bits)
Data pointer (6 bits)
n
Hexadecimal constant which represents the
immediate value
(It consists of registers X and Y)
j
Hexadecimal constant which represents the
A3A2A1A0
immediate value
Binary notation of hexadecimal variable A
LO
DP
PC
PCH
PCL
SK
SP
CY
R1
T1
T1F
INTE
EXF0
P
Program counter (11 bits)
High-order 4 bits of program counter
Low-order 7 bits of program counter
Stack register (11 bits ✕ 4)
Stack pointer (2 bits)
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
(same for others)
←
↔
Direction of data movement
Carry flag
Timer 1 reload register
Timer 1
?
( )
Decision of state shown before “?”
Contents of registers and memories
Timer 1 interrupt request flag
—
Negate, Flag unchanged after executing
Interrupt enable flag
External interrupt request flag
M(DP)
instruction
RAM address pointed by the data pointer
Power down flag
a
Label indicating address a6 a5 a4 a3 a2 a1 a0
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p3 p2 p1 p0
C
Hex. C + Hex. number x (also same for others)
Data exchange between a register and memory
+
x
Note : The 4250 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
32
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION
TBA
(B) ← (A)
Grouping Mnemonic
Function
LA n
(A) ← n
n = 0 to 15
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
Grouping Mnemonic
operation
(A) ← (B)
Comparison
Function
TAB
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
(PCH) ← p
Ba
TYA
(Y) ← (A)
(PC L ) ← (DR 2 –DR 0 ,
A3–A0)
BL p, a
TEAB
(E7–E4) ← (B)
(B) ← (ROM(PC))7 to 4
(E3–E0) ← (A)
(A) ← (ROM(PC))3 to 0
(PC) ← (SK(SP))
(B) ← (E7–E4)
(SP) ← (SP) – 1
(A) ← (E3–E0)
(DR2–DR0) ← (A2–A0)
LXY x, y
(X) ← x, x = 0 to 3
(Y) ← y, y = 0 to 15
INY
(Y) ← (Y) + 1
DEY
(Y) ← (Y) – 1
TAM j
(A) ← (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
XAM j
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
(A) ← (A) + (M(DP))
AMC
(A) ← (A) + (M(DP))
+ (CY)
(PCL) ← a6–a0
(PCH) ← p
(PCL) ← a6–a0
BA a
(PCL) ← (a6–a4, A3–A0)
BLA p, a
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
BM a
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(CY) ← Carry
(PCL) ← a6–a0
An
(A) ← (A) + n
n = 0 to 15
SC
(CY) ← 1
RC
(CY) ← 0
SZC
(CY) = 0 ?
CMA
(A) ← (A)
RAR
→ CY → A3A2A1A0
LGOP
Logic operation
Subroutine operation
TDA
AM
Branch operation
(A) ← (Y)
TABE
Function
SEAM
TAY
Arithmetic operation
RAM addresses
Register to register transfer
Grouping Mnemonic
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p, (SP) ← (SP) + 1
(SK(SP)) ← (PC)
a
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
(X) ← (X) EXOR(j)
instruction
XOR, OR, AND
j = 0 to 3
(Y) ← (Y) – 1
XAMI j
RTI
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(A) ←→ (M(DP))
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
SB j
(Mj(DP)) ← 1
j = 0 to 3
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
Return operation
XAMD j
Bit operation
RAM to register transfer
j = 0 to 3
33
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Function
Grouping Mnemonic
Function
INTE← 0
CLD
(D) ← 1
NOP
(PC) ← (PC) + 1
EI
INTE ← 1
RD
(D(Y)) ← 0
POF
RAM back-up
SNZP
(P) = 1 ?
TLOA
(LO) ← (A1, A0)
TV1A
(V1) ← (A)
TAV1
(A) ← (V1)
TK0A
(K0) ← (A)
TAK0
(A) ← (K0)
TPU0A
(PU0) ← (A)
(Y) = 0 to 3
SNZ0
(EXF0) = 1 ?
SD
After skipping the next
instruction
(EXF0) ← 0
(B) ← (T17–T14)
(A) ← (T13–T10)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
SNZ1
(T1F) = 1 ?
After skipping the next
instruction
(D(Y)) = 0 ?
(Y) = 0 to 3
Input/Output operation
T1AB
(D(Y)) ← 1
(Y) = 0 to 3
SZD
Timer operation
Grouping Mnemonic
DI
TAB1
SCP
(C) ← 1
RCP
(C) ← 0
SNZCP
(C) = 1?
OFA
(F) ← (A1, A0)
IAF
(A1, A0) ← (F)
(T1F) ← 0
34
Function
(A3, A2) ← (0)
OGA
(G) ← (A)
IAG
(A) ← (G)
OSA
(S) ← (A)
IAS
(A) ← (S)
OKA
(K) ← (A0)
IAK
(A0) ← (K),
(A3, A2, A1) ← (0)
Other operation
Interrupt operation
Grouping Mnemonic
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE
00
01
02
03
0000
0
NOP
BLA
SZB
0
BL
1
BA
CLD
SZB
1
BL
SZB
2
0001
05
06
07
BMLA
XAM
0
BML
XAM
1
BML
BL
XAM
2
04
LGOP
08
09
–
D3–
D0
Hex.
notation
10000 11000
–
D8–D4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
10111 11111
0A
0B
0C
0D
0E
0F
OGA TABP
0
A
0
LA
0
LXY
0,0
LXY
1,0
LXY
2,0
LXY
3,0
BM
B
OKA
TABP
1
A
1
LA
1
LXY
0,1
LXY
1,1
LXY
2,1
LXY
3,1
BM
B
BML
SCP
TABP
2
A
2
LA
2
LXY
0,2
LXY
1,2
LXY
2,2
LXY
3,2
BM
B
XAM
3
BML
RCP
TABP
3
A
3
LA
3
LXY
0,3
LXY
1,3
LXY
2,3
LXY
3,3
BM
B
TAM
0
BML
OFA
TABP
4
A
4
LA
4
LXY
0,4
LXY
1,4
LXY
2,4
LXY
3,4
BM
B
LA
5
LXY
0,5
LXY
1,5
LXY
2,5
LXY
3,5
BM
B
LXY
0,6
LXY
1,6
LXY
2,6
LXY
3,6
BM
B
10 to 1718 to 1F
0010
2
0011
3
SNZP
INY
SZB
3
BL
0100
4
DI
RD
SZD
BL
RT
5
EI
SD
SEAn
BL
RTS
IAS
TAM
1
BML
T1AB
TABP
5
A
5
0110
6
RC
SEAM
BL
RTI
IAF
TAM
2
BML
TV1A
TABP
6
A
6
0111
7
SC
BL
IAK
TAM
3
BML
TK0A
TABP
7
A
7
LA
7
LXY
0,7
LXY
1,7
LXY
2,7
LXY
3,7
BM
B
TLOA
XAMI
0
BML
TAV1
TABP
8
A
8
LA
8
LXY
0,8
LXY
1,8
LXY
2,8
LXY
3,8
BM
B
LXY
3,9
BM
B
0101
1000
1001
DEY
LA
6
8
IAG
BL
9
TDA
BL
XAMI
1
BML
TAK0
TABP
9
A
9
LA
9
LXY
0,9
LXY
1,9
LXY
2,9
TEAB TABE
BL
XAMI
2
BML
TAB1
TABP
10
A
10
LA
10
LXY
0,10
LXY
1,10
LXY LXY
2,10 3,10
BM
B
XAMI
3
BML TPU0A
TABP
11
A
11
LA
11
LXY
0,11
LXY
1,11
LXY LXY
2,11 3,11
BM
B
1010
A
AM
1011
B
AMC
OSA
BL
1100
C
TYA
CMA
BL
RB
0
SB
0
TABP
XAMD
BML SNZ1
12
0
A
12
LA
12
LXY
0,12
LXY
1,12
LXY LXY
2,12 3,12
BM
B
1101
D
POF
RAR
BL
RB
1
SB
1
XAMD
TABP
BML SNZCP
1
13
A
13
LA
13
LXY
0,13
LXY
1,13
LXY LXY
2,13 3,13
BM
B
1110
E
TBA
TAB
BL
RB
2
SB
2
XAMD
BML
2
TABP
14
A
14
LA
14
LXY
0,14
LXY
1,14
LXY LXY
2,14 3,14
BM
B
1111
F
BL
RB
3
SB
3
XAMD
TABP
BML SNZ0
3
15
A
15
LA
15
LXY
0,15
LXY
1,15
LXY LXY
2,15 3,15
BM
B
TAY
SZC
The above table shows the relationship between machine language codes and machine language instructions. D3–D0
show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language
code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word
instructions, but only the first word of each instruction is shown.
The codes for the second word of a two-word instruction are described below.
BL
BML
BA
BLA
BMLA
SEA
SZD
1
1
1
1
1
0
0
The second word
1aaa aaaa
0aaa aaaa
1aaa
1aaa
0aaa
1011
0010
Do not use the code marked “–.”
aaaa
pppp
pppp
nnnn
1011
35
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS
TAB
0
0
0
0
1
1
1
1
0
0 1
E
1
1
(A) ← (B)
TBA
0
0
0
0
0
1
1
1
0
0 0
E
1
1
(B) ← (A)
TAY
0
0
0
0
1
1
1
1
1
0 1
F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
1
1
0
0
0 0
C
1
1
(Y) ← (A)
TEAB
0
0
0
0
1
1
0
1
0
0 1
A
1
1
(E7–E4) ← (B) (E3–E0) ← (A)
TABE
0
0
0
1
0
1
0
1
0
0 2
A
1
1
(B) ← (E7–E4) (A) ← (E3–E0)
TDA
0
0
0
1
0
1
0
0
1
0 2
9
1
1
(DR2–DR0) ← (A2–A0)
LXY x, y
0
1
1
x1 x0 y3 y2 y1 y0
0 C y
+x
1
1
(X) ← x, x = 0 to 3
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
RAM addresses
Register to register transfer
Type of
instructions
36
Hexadecimal
notation
Function
(Y) ← y, y = 0 to 15
INY
0
0
0
0
1
0
0
1
1
0 1
3
1
1
(Y) ← (Y) + 1
DEY
0
0
0
0
1
0
1
1
1
0 1
7
1
1
(Y) ← (Y) – 1
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
Transfers the contents of register A to register D.
Continuous
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
description
Detailed description
Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
37
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
TAM j
0
0
1
1
0
0
1
j1
j0
Hexadecimal
notation
0 6
4
1
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
Function
(A) ← (M(DP))
(X) ← (X) EXOR(j)
+j
RAM to register transfer
j = 0 to 3
XAM j
0
0
1
1
0
0
0
j1
j0
0 6
j
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
XAMD j
0
0
1
1
0
1
1
j1
j0
0 6 C
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
+j
j = 0 to 3
(Y) ← (Y) – 1
XAMI j
0
0
1
1
0
1
0
j1
j0
0 6
8
+j
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
38
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Detailed description
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
39
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
LA n
0
1
0
1
1
n3 n2 n1 n0
Hexadecimal
notation
0 B n
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(A) ← n
n = 0 to 15
TABP p
0
1
0
0
1
p3 p2 p1 p0
0 9
p
1
3
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(SP) ← (SP) – 1
(PC) ← (SK(SP))
Arithmetic operation
(Note)
AM
0
0
0
0
0
1
0
1
0
0 0
A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
1
0
1
1
0 0
B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
An
0
1
0
1
0
n3 n2 n1 n0
0 A n
1
(A) ← (A) + n
n = 0 to 15
SC
0
0
0
0
0
0
1
1
1
0 0
7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
1
1
0
0 0
6
1
1
(CY) ← 0
SZC
0
0
0
1
0
1
1
1
1
0 2
F
1
1
(CY) = 0 ?
CMA
0
0
0
0
1
1
1
0
0
0 1
C
1
1
(A) ← (A)
RAR
0
0
0
0
1
1
1
0
1
0 1
D
1
1
→ CY → A3A2A1A0
LGOP
0
1
0
0
0
0
0
0
1
0 4
1
1
1
Logic operation instruction XOR, OR, AND
Note : p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.
40
1
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Continuous
–
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
description
–
Detailed description
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p.
When this instruction is executed, 1 stage of stack register is used.
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
–
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
Overflow = 0
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one‘s complement for register A‘s contents in register A.
–
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
Execute the logic operation selected by logic operation selection register LO between the contents of
register A and port S, and stores the result in register A.
41
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
SB j
0
0
1
0
1
1
1
j1
j0
Hexadecimal
notation
0 5
C
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Bit operation
+j
RB j
0
0
1
0
0
1
1
j1
j0
0 4
C
0
0
0
1
0
0
0
j1
j0
0 2
j
(Mj(DP)) ← 1
j = 0 to 3
1
1
+j
SZB j
Function
(Mj(DP)) ← 0
j = 0 to 3
1
1
(Mj(DP)) = 0 ?
Comparison
operation
j = 0 to 3
SEAM
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
n = 0 to 15
Ba
0
1
0
1
1
n3 n2 n1 n0
1
1
a6 a5 a4 a3 a2 a1 a0
0 B n
1
8
a
1
1
(PCL) ← a6–a0
2
2
(PCH) ← p
(PCL) ← a6–a0
+a
BL p, a
0
0
0
1
1
p3 p2 p1 p0
0 3
p
1
1
a6 a5 a4 a3 a2 a1 a0
1 8
a
Branch operation
(Note)
+a
BA a
BLA p, a
0
0
0
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
0
0
0
0 1
0
1
1
a6 a5 a4 p3 p2 p1 p0
1 8
p
0
0
1
0
0
0
0
0
0
1
0
0 0
+a
Note : p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.
42
1
2
2
(PCL) ← (a6–a4, A3–A0)
2
2
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
(Note)
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
j = 0 to 3
Detailed description
of M(DP) is “0.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
n = 0 to 15
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a with register A in the identical page.
–
–
Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a with register A in page p.
43
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Mnemonic
Type of
instructions
BM a
D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
1
1
0
a 6 a5 a4 a3 a2 a1 a0
a
a
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
1
p3 p2 p1 p0
0 7
p
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
BMLA p, a 0
0
1
0 5
0
1
0
a6 a5 a4 p3 p2 p1 p0
1 a
p
0
1
0
0
0
0
(PCL) ← a6–a0
(Note)
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
Return operation
(PCL) ← (a6–a4, A3–A0)
(Note)
RTI
0
0
1
0
0
0
1
1
0
0 4
6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RT
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(PC) ← (SK(SP))
Interrupt operation
(SP) ← (SP) – 1
DI
0
0
0
0
0
0
1
0
0
0 0
4
1
1
(INTE) ← 0
EI
0
0
0
0
0
0
1
0
1
0 0
5
1
1
(INTE) ← 1
SNZ0
0
1
0
0
0
1
1
1
1
0 8 F
1
1
(EXF0) = 1 ?
Note : p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.
44
After skipping the next instruction
(EXF0) ← 0
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the
low-order 4 bits of address a with register A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y), carry flag, skip status, NOP mode status by the continuous
Detailed description
description of the LA/LXY instruction to the states just before interrupt.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
–
–
Clears (0) to the interrupt enable flag INTE, and disables the interrupt.
–
–
Sets (1) to the interrupt enable flag INTE, and enables the interrupt.
(EXF0) = 1
–
Skips the next instruction when the contents of EXF0 flag is “1.”
After skipping, clears the EXF0 flag.
45
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
TAB1
0
1
0
0
0
1
0
1
0
Hexadecimal
notation
0 8 A
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(B) ← (T17–T14)
Timer operation
(A) ← (T13–T10)
T1AB
0
1
0
0
0
0
1
0
1
0 8 5
1
1
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
SNZ1
0
1
0
0
0
1
1
0
0
0 8 C
1
1
(T1F) = 1 ?
After skipping the next instruction
Input/Output operation
(T1F) ← 0
46
CLD
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
RD
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 3
SD
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 3
SZD
0
0
0
1
0
0
1
0
0
0 2 4
2
2
(D(Y)) = 0 ?
(Y) = 0 to 3
0
0
0
1
0
1
0
1
1
0 2 B
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
–
–
Transfers the contents of timer 1 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 1 and timer 1 reload register.
(T1F) = 1
–
Skips the next instruction when the contents of T1F flag is “1.”
Detailed description
After skipping, clears (0) to T1F flag.
–
–
Sets (1) to port D (high-impedance state).
–
–
Clears (0) to a bit of port D specified by register Y.
–
–
Sets (1) to a bit of port D specified by register Y (high-impedance state).
(D(Y)) = 0
(Y) = 0 to 3
–
Skips the next instruction when a bit of port D specified by register Y is “0.”
47
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
OFA
0
1
0
0
0
0
1
0
0
0 8 4
1
1
(F) ← (A1, A0)
IAF
0
0
1
0
1
0
1
1
0
0 5 6
1
1
(A1, A0) ← (F), (A3, A2) ← 0
OGA
0
1
0
0
0
0
0
0
0
0 8 0
1
1
(G) ← (A)
IAG
0
0
0
1
0
1
0
0
0
0 2 8
1
1
(A) ← (G)
OSA
0
0
0
0
1
1
0
1
1
0 1 B
1
1
(S) ← (A)
IAS
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (S)
OKA
0
1
0
0
0
0
0
0
1
0 8 1
1
1
(K) ← (A0)
IAK
0
0
1
0
1
0
1
1
1
0 5 7
1
1
(A0) ← (K), (A3–A1) ← 0
SCP
0
1
0
0
0
0
0
1
0
0 8 2
1
1
(C) ← 1
RCP
0
1
0
0
0
0
0
1
1
0 8 3
1
1
(C) ← 0
SNZCP
0
1
0
0
0
1
1
0
1
0 8 D
1
1
(C) = 1 ?
NOP
0
0
0
0
0
0
0
0
0
0 0
0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
1
1
0
1
0 0
D
1
1
RAM back-up
SNZP
0
0
0
0
0
0
0
1
1
0 0
3
1
1
(P) = 1 ?
TLOA
0
0
1
0
1
1
0
0
0
0 5
8
1
1
(LO) ← (A1, A0)
TV1A
0
1
0
0
0
0
1
1
0
0 8
6
1
1
(V1) ← (A)
TAV1
0
1
0
0
0
1
0
0
0
0 8
8
1
1
(A) ← (V1)
TK0A
0
1
0
0
0
0
1
1
1
0 8
7
1
1
(K0) ← (A)
TAK0
0
1
0
0
0
1
0
0
1
0 8
9
1
1
(A) ← (K0)
TPU0A
0
1
0
0
0
1
0
1
1
0 8
B
1
1
(PU0) ← (A)
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Other operation
Input/Output operation
Type of
instructions
48
Hexadecimal
notation
Function
MITSUBISHI MICROCOMPUTERS
4250 Group
Skip condition
Carry flag CY
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
–
–
Outputs the contents of register A to port F.
–
–
Transfers the contents of port F to register A.
–
–
Outputs the contents of register A to port G.
–
–
Transfers the contents of port G to register A.
–
–
Outputs the contents of register A to port S.
–
–
Transfers the contents of port S to register A.
–
–
Outputs the contents of register A to port K.
–
–
Transfers the contents of port K to register A.
–
–
Sets (1) to port C.
–
–
Clears (0) to port C.
(C) = 1
–
Skips the next instruction when the contents of port C is “1.”
–
–
No operation
–
–
Puts the system in RAM back-up state.
(P) = 1
–
Skips the next instruction when P flag is “1.”
After skipping, P flag remains unchanged.
–
–
Transfers the contents of register A to the logic operation selection register LO.
–
–
Transfers the contents of register A to register V1.
–
–
Transfers the contents of register V1 to register A.
–
–
Transfers the contents of register A to register K0.
–
–
Transfers the contents of register K0 to register A.
–
–
Transfers the contents of register A to register PU0.
Detailed description
49
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONTROL REGISTERS
V13
G1/TOUT pin function selection bit
V12
Prescaler/timer 1 operation start bit
V11
Timer 1 interrupt enable bit
V10
External interrupt enable bit
0
Port G1 (I/O)
1
0
TOUT pin (output) / port G1(input)
Prescaler stop (initial state) / timer 1 stop (state retained)
1
Prescaler/timer 1 operation
0
1
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Key-on wakeup control register K0
K03
Prescaler dividing ratio selection bit
Interrupt valid waveform for INT pin/
K02
key-on wakeup valid waveform selection
bit (Note 2)
K01
Ports G1–G3 key-on wakeup control bit
K00
Ports S0–S3 key-on wakeup control bit
at reset : 00002
PU00
at RAM back-up : state retained
0
Instruction clock divided by 4
1
0
Instruction clock divided by 512
Rising waveform (“L” → “H”)
1
Falling waveform (“H” → “L”)
0
Key-on wakeup not used
1
Key-on wakeup used (“L” level recognized)
Key-on wakeup not used
0
1
Pull-up control register PU0
PU01
at RAM back-up : 00002
at reset : 00002
Timer control register V1
at reset : 002
at RAM back-up : state retained
0
Pull-up transistor OFF
1
Pull-up transistor ON
Ports G0–G3
0
1
Pull-up transistor OFF
Pull-up transistor ON
Logic operation selection register LO
LO1
Logic operation function selection bits
R/W
Key-on wakeup used (“L” level recognized)
Ports C and K
pull-up transistor control bit
pull-up transistor control bit
R/W
at reset : 002
LO1 LO0
0 XOR operation
0
1 OR operation
0
at RAM back-up : 002
W
W
Functions
0 AND operation
1
1 Not available
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least
one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when
the interrupt valid waveform is changed.
LO0
50
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD
Supply voltage
VI
Input voltage XIN, G0–G3, D2/C, D3/K
VI
Input voltage F0, F1, S0–S3, D0, D1, RESET
VO
Output voltage XOUT
VO
VO
Pd
Conditions
Unit
V
Ratings
–0.3 to 7.0
–0.3 to VDD+0.3
V
–0.3 to 8.0
–0.3 to VDD+0.3
V
V
Output voltage F0, F1, S0–S3, D0, D1
Output transistors
–0.3 to 8.0
V
Output voltage G0–G3, D2/C, D3/K
in cut-off state
Ta = 25 °C
–0.3 to VDD+0.3
300
V
Topr
Power dissipation
Operating temperature range
Tstg
Storage temperature range
–20 to 85
mW
°C
–40 to 125
°C
RECOMMENDED OPERATING CONDITIONS
(Ta = –20 °C to 85 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)
Symbol
VDD
Supply voltage
VRAM
RAM back-up voltage (at RAM back-up mode)
VSS
Supply voltage
“H” level input voltage F0, F1, D0, D1
VIH
VIH
VIH
VIH
VIH
0.4 MHz ≤ f(XIN) ≤ 4.4 MHz
0.4 MHz ≤ f(XIN) ≤ 1.1 MHz
2.2
“H” level input voltage S0–S3
0.7VDD
0.4VDD
VDD = 2.2 V to 5.5 V
0.6VDD
VDD
VDD
7
7
7
0.16VDD
0
0.2VDD
0.3VDD
0
0
VIL
“L” level input voltage INT
VIL
“L” level input voltage RESET
IOL(peak) “L” level peak output current
10
12
(Note 1)
VDD = 3 V ±10 %
0.4
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.1VDD V
24
mA
(Note 1)
VDD = 4.5 V to 5.5 V
VDD = 2.2 V to 5.5 V
Unit
0.15VDD
0
Frequency error (errors of external capacitor and resistor VDD = 5 V ±10 %
Ta = 25 °C [reference]
not included)
Note: Use the 30 pF capacitor externally and enable the (–20 °C to 85 °C)
change of frequency by external resistor.
VDD
0.85VDD
0
“L” level input voltage F0, F1, G0–G3, D0–D3
F0, F1, S0–S3, D0, D1, D2/C, D3/K
IOL(avg) “L” level average output current G0, G1/TOUT, G2, G3
f(XIN)
System clock frequency (Note 2)
7
VDD
0.7VDD
0.85VDD
VDD = 2.2 V to 5.5 V
VDD = 4.5 V to 5.5 V
F0, F1, S0–S3, D0, D1, D2/C, D3/K
IOL(peak) “L” level peak output current G0, G1/TOUT, G2, G3
IOL(avg) “L” level average output current
5.5
5.5
5.5
0.7VDD
0.5VDD
“L” level input voltage C, K
“L” level input voltage S0–S3
Max.
0
VDD = 4.5 V to 5.5 V
VIL
Typ.
5.0
2.0
“H” level input voltage INT
“H” level input voltage C, K
“H” level input voltage RESET
∆f(XIN)
Limits
Min.
4.5
“H” level input voltage G0–G3, D2, D3
VIH
VIL
VIL
Conditions
Parameter
4.0
1.0
5
4.4
mA
mA
mA
MHz
1.1
±17
%
±17
Ta = 25 °C [reference]
(–20 °C to 85 °C)
Notes 1: Keep the total currents of IOL(avg) for ports S0–S3, D0, D1, D2/C, D3/K to 50 mA or less.
Keep the total currents of IOL(avg) for ports F0, F1, G0, G2, G3 and G1/TOUT pin to 30 mA or less.
2: The system clock frequency is affected by the external capacitor, resistor and LSI. Accordingly, set the constants so as not
to exceed the frequency limits.
Be careful about the input waveform when using the external clock. Refer to the notes on use.
51
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
(Ta = –20 °C to 85 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Test conditions
VOL
“L” level output voltage
VDD = 5 V
VDD = 3 V
VOL
F0, F1, S0–S3, D0, D1, D2/C, D3/K
“L” level output voltage
G0, G1/TOUT, G2, G3
VDD = 5 V
VDD = 3 V
Limits
Min.
Typ.
Max.
Unit
2
V
V
IOL = 5 mA
0.9
2
IOL = 2 mA
0.9
V
V
IOL = 12 mA
IOL = 6 mA
IIH
“H” level input current
F0, F1, S0–S3, D0, D1, RESET
VI = 7 V
1
µA
IIH
“H” level input current
VI = VDD
1
µA
IIL
G0/INT, G1, G2, G3, D2/C, D3/K
“L” level input current
VI = 0 V (Note)
–1
µA
IOZH
G0/INT, G1, G2, G3, RESET
Output current at off-state
VO = 7 V
1
µA
VO = VDD
1
µA
1.5
5
mA
0.3
0.1
1
1
mA
F0, F1, S0–S3, D0, D1, D2/C, D3/K,
F0, F1, S0–S3, D0, D1
IOZH
IDD
Output current at off-state
G0, G1/TOUT, G2, G3, D2/C, D3/K
Supply current at active mode
VDD = 5 V
VDD = 3 V
at RAM back-up mode
f(XIN) = 4.0 MHz
f(XIN) = 1.0 MHz
Ta = 25 °C
VDD = 5 V
10
VDD = 3 V
RPU
Pull-up transistor
VDD = 5 V, VI = 0 V
5
G0/INT, G1, G2, G3, D2/C, D3/K
VT+ – VT– Hysteresis INT
VT+ – VT– Hysteresis S0–S3
VT+ – VT– Hysteresis RESET
11
0.3
VDD = 5 V
VDD = 5 V
0.1
1.8
VDD = 3 V
0.7
Note: In this case, the pull-up transistors for G0/INT pin and ports G1, G2, G3, D2/C and D3/K are not selected.
52
6
25
µA
µA
µA
kΩ
V
V
V
V
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BASIC TIMING DIAGRAM
Machine cycle
Parameter
Pin name
State
Clock
XIN
Ports D, C, K output
D0,D1
D2/C,D3/K
Ports D, C, K input
D0,D1
D2/C,D3/K
Ports F, G, S output
F0,F1
G0/INT,G1/TOUT
G2, G3
S0–S3
Ports F, G, S input
F0,F1
G0/INT,G1/TOUT
G2, G3
S0–S3
Interrupt input
G0/INT
Mi
Mi+1
T4
T1
T2
T3
T4
53
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4250 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing
to built-in PROM.
Table 15 Product of built-in PROM version
PROM size
Product
(✕ 9 bits)
M34250E2-XXXFP *
RAM size
(✕ 4 bits)
Table 15 shows the product of built-in PROM version. Figure 31
and 32 show the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
Package
ROM type
One Time PROM [shipped after writing]
2048 words
64 words
20P2N-A
M34250E2FP *
*: Under development
(shipped after writing and test in factory)
One Time PROM [shipped in blank]
PIN CONFIGURATION (TOP VIEW)
1
20
D0
VSS
2
19
D1
XIN
3
18
D2/C
XOUT
4
17
D3/K
CNVSS
5
16
S0
RESET
6
15
S1
F0
7
14
S2
F1
8
13
S3
G0/INT
9
12
G3
G1/TOUT
10
11
G2
M34250E2-XXXFP
VDD
Outline 20P2N-A
Fig. 31 Pin configuration of built-in PROM version
54
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
VDD
1
20
D0
VSS
VSS(0V)
2
19
D1
X IN
3
18
D2/C
X OUT
4
17
D3/K
CNVSS
5
16
S0
RESET
6
15
S1
F0
7
14
S2
F1
8
13
S3
G0/INT
9
12
G3
G1/TOUT 10
11
G2
✽
VPP
SCLK
SDA
PGM
VDD
M34250E 2-XXXFP
VDD
Outline 20P 2N-A
✽ : A resistor is connected to XIN pin.
A capacitor is connected to XOUT pin.
Note: The state of each disconnected pin is the same as that at reset.
Fig. 32 Pin configuration of built-in PROM version (continued)
55
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) PROM mode
The 4250 Group has a function to serially input/output the
command codes, addresses, and data required for operation
(e.g. read and program) on the built-in PROM using only a
few pins. This mode can be selected by setting pins SDA (serial
data input/output), SCLK (serial clock input), and PGM to “H”
after connecting wires as shown in Figure 32 and powering
on the VDD pin, and then applying 12 V to the VPP pin.
In the PROM mode, three types of software commands (read,
program, and program verify) can be used.
Clock-synchronous serial I/O is used, beginning from the LSB
(LSB first). Use the special-purpose serial programmer when
performing serial read/program.
Refer to the Mitsubishi Data Book “DEVELOPMENT
SUPPORT TOOLS FOR MICROCOMPUTERS” about the
serial programmer (serial programmer and control software,
etc.) for the Mitsubishi single-chip microcomputers.
(2) Notes on handling
➀ A high-voltage is used for writing. Take care that overvoltage
is not applied. Take care especially at turning on the power.
➁ For the One Time PROM version shipped in blank,
Mitsubishi Electric corp. does not perform PROM writing
test and screening in the assembly process and following
processes. In order to improve reliability after writing,
performing writing and test according to the flow shown in
Figure 33 before using is recommended (Products shipped
in blank: PROM contents is not written in factory when
shipped)
56
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150°C exceeding 100
hours.
Fig. 33 Flow of writing and test of the product shipped in
blank
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1997 MITSUBISHI ELECTRIC CORP.
KI-9711 Printed in Japan (ROD) II
New publication, effective Nov. 1997.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
4250 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
971130
(1/1)