AT73C240 vs AT73C213 - Software Integration 1. Scope The goal of this document is to help a software team that already uses the AT73C213 product to easily integrate the new AT73C240 product in their application. This document describes the registers that are changed or removed between the AT73C213 product and the AT73C240 product. In the tables that follow, the registers that have changed are highlight in blue and the registers that have been removed are highlight in red. 2. Product Description The AT73C240 is a fully integrated, low-cost, combined stereo audio DAC and audio power amplifier circuit. The stereo DAC section is a complete high performance, stereo, audio digital-to-analog converter. It comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. Power Management and Analog Companions (PMAAC) Application Note Master clock is 256 or 384 times the input data rate, allowing choice of input data rate up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC section is followed by a volume and mute control and can be simultaneously played back directly through a stereo 32 Ohm headset pair of drivers. The stereo 32 Ohm headset pair of drivers also includes a mixer of a LINEL and LINER pair of stereo inputs. The Audio Power Amplifier is a differential amplifier designed in CMOS technology. It is capable of driving an 8 Ohm Loudspeaker at maximum power of 440mW. The volume, mute, power down, de-emphasis controls and audio formats are digitally programmable via a serial bus and the digital audio data are provided through a multiformat I2S interface. 6484A–PMAAC–04-Jun-09 3. Operating Conditions Table 3-1. Operating Condition Table For AT73C240 Product Parameter/Function Pads Storage Temperature Conditions Min Max Unit -- -55 150 °C Operating Temperature -- -40 85 °C Audio Power Input Voltage VBAT 3.0 5.5 V Digital Input Voltage VDIG 2.4 3.3 V Analog Input Voltage AVDD, AVDDHS 2.7 3.3 V 4. Glossary DAC -- Digital to Analog Converter SPI -- Serial Peripheral Interface TWI -- Two Wire Interface PA -- Audio Power Amplifier I²S -- Integrated Interchip Sound Interface 2 Application Note 6484A–PMAAC–04-Jun-09 Application Note 5. AT73C240 Block Diagram -36 to +12dB / 3dB step AT73C240 GNDB VREF PAINN VBAT CBP HPP Audio PA HPN AT73C240 Block Diagram PAINP Figure 5-1. VDIG AVDD Voltage Reference AVDDHS SPI_DOUT LINER PGA SPI_DIN / TWD Status Registers INGND -36 to +12dB / 3dB step SPI SPI_CLK / TWCK LINEL SPI_CSB / TW_ADD PGA -46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step MCLK -6 to +6dB / 3dB step 32 driver + DAC Volume Control + Volume Control RSTB Digital Filter VCM -6 to +6dB / 3dB step HSR 32 driver + DAC Volume Control + Volume Control Digital Filter Serial Audio I/F HSL SMODE SDIN LRFS BCLK GNDA -46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step MONOP MONO + GNDD MONON 3 6484A–PMAAC–04-Jun-09 6. User Interface : Register Table 6.1 AT73C213 Register Table Address Register Name Access Reset State 0x00 DAC_CTRL DAC Control Read/Write 0x00 0x01 DAC_LLIG DAC Left Line In Gain Read/Write 0x05 0x02 DAC_RLIG DAC Right Line In Gain Read/Write 0x05 0x03 DAC_LMPG DAC Left Master Playback Gain Read/Write 0x08 0x04 DAC_RMPG DAC Right Master Playback Gain Read/Write 0x08 0x05 DAC_LLOG DAC Left Line Out Gain Read/Write 0x00 0x06 DAC_RLOG DAC Right Line Out Gain Read/Write 0x00 0x07 DAC_OLC DAC Output Level Control Read/Write 0x22 0x08 DAC_MC DAC Mixer Control Read/Write 0x09 0x09 DAC_CSFC DAC Clock and Sampling Frequency Control Read/Write 0x00 0x0A DAC_MISC DAC Miscellaneous Read/Write 0x00 0x0C DAC_PRECH DAC Precharge Control Read/Write 0x00 0x0D DAC_AUXG Dac Auxilary input gain Control Read/Write 0x05 0x10 DAC_RST DAC Reset Read/Write 0x00 0x11 PA_CRTL Power Amplifier Control Read/Write 0x00 Access Reset State 6.2 AT73C240 Register Table Address Register Name 0x00 DAC_CTRL DAC Control Read/Write 0x00 0x01 DAC_LLIG DAC Left Line In Gain Read/Write 0x05 0x02 DAC_RLIG DAC Right Line In Gain Read/Write 0x05 0x03 DAC_LMPG DAC Left Master Playback Gain Read/Write 0x08 0x04 DAC_RMPG DAC Right Master Playback Gain Read/Write 0x08 0x05 DAC_LLOG DAC Left Line Out Gain Read/Write 0x00 0x06 DAC_RLOG DAC Right Line Out Gain Read/Write 0x00 0x07 DAC_OLC DAC Output Level Control Read/Write 0x22 0x08 DAC_MC DAC Mixer Control Read/Write 0x09 0x09 DAC_CSFC DAC Clock and Sampling Frequency Control Read/Write 0x00 0x0A DAC_MISC DAC Miscellaneous Read/Write 0x00 0x0B IS_CTRL I²S synchronous Read/Write 0x00 0x0C DAC_PRECH DAC Precharge Control Read/Write 0x00 0x10 DAC_RST DAC Reset Read/Write 0x00 0x11 PA_CRTL Power Amplifier Control Read/Write 0x0F 4 Application Note 6484A–PMAAC–04-Jun-09 Application Note 7. DAC Control Register : DAC_CTRL 7.1 AT73C213 Register Register Name: DAC_CTRL (Address = 0x00) Reset State: 0x00 Access: Read/Write 7 ONPADRV Bit 0 1 2 3 4 5 6 7 7.2 6 ONAUXIN Name ONLNIL ONLNIR ONLNOL ONLNOR ONDACL ONDACR ONAUXIN ONPADRV 5 ONDACR 4 ONDACL 3 ONLNOR 2 ONLNOL 1 ONLNIR Description Left channel line in amplifier (L to power down, H to power up) Right channel line in amplifier (L to power down, H to power up) Left channel line out driver (L to power down, H to power up) Right channel line out driver (L to power down, H to power up) Left channel DAC (L to power down, H to power up) Right channel DAC (L to power down, H to power up) Differential mono auxiliary input amplifier (L to power down, H to power up) Differential mono PA driver (L to power down, H to power up) 0 ONLNIL Reset Value Low Low Low Low Low Low Low Low AT73C240 Register Register Name: DAC_CTRL (Address = 0x00) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 0 1 2 3 4 5 7 6 ONPADRV Name ONLNIL ONLNIR ONLNOL ONLNOR ONDACL ONDACR ONPADRV Not Used 5 ONDACR 4 ONDACL 3 ONLNOR 2 ONLNOL Description Left channel line in amplifier (L to power down, H to power up) Right channel line in amplifier (L to power down, H to power up) Left channel line out driver (L to power down, H to power up) Right channel line out driver (L to power down, H to power up) Left channel DAC (L to power down, H to power up) Right channel DAC (L to power down, H to power up) Differential mono PA driver (L to power down, H to power up) -- 1 ONLNIR 0 ONLNIL Reset Value Low Low Low Low Low Low Low Low 5 6484A–PMAAC–04-Jun-09 8. DAC Output Level Control Register : DAC_OLC 8.1 AT73C213 Register Register Name: DAC_OLC (Address = 0x07) Reset State: 0x22 (Access: Read/Write) 7 RSHORT Bit 2:0 3 6:4 7 6 Name LOLC LSHORT ROLC RSHORT 5 ROLC 4 3 LSHORT 2 1 LOLC Description Left channel output level selector Left channel short circuit indicator Right channel output level selector Right channel short circuit indicator 0 Reset Value Low, High, Low Low Low, High, Low Low l Table 8-1. Output Level Contro LOLC / ROLC Gain Unit LOLC / ROLC Gain Unit 000 6 dB 011 -3 dB 010 3 dB ≥100 -6 dB 010 0 dB 8.2 AT73C240 Register Register Name: DAC_OLC (Address = 0x07) Reset State: 0x22 (Access: Read/Write) 7 RSHORT Bit 2:0 3 6:4 7 6 Name LOLC LSHORT ROLC RSHORT 5 ROLC 4 3 LSHORT 2 1 LOLC Description Left channel output level selector Left channel short circuit indicator Right channel output level selector Right channel short circuit indicator 0 Reset Value Low, High, Low Low Low, High, Low Low l Table 8-2. 6 Output Level Contro LOLC / ROLC Gain Unit LOLC / ROLC Gain Unit 000 -5 dB 011 2.5 dB 010 -2.5 dB ≥100 5 dB 010 0 dB Application Note 6484A–PMAAC–04-Jun-09 Application Note 9. DAC Miscellaneous Register : DAC_MISC 9.1 AT73C213 Register Register Name: DAC_MISC (Address = 0x0A) Reset State: 0x00 Access: Read/Write 7 VCMCAPSEL Bit 1:0 2 3 5:4 6 7 9.2 6 Not Used Name NBITS DEEMPEN DITHEN DINTSEL Not Used VCMCAPSEL 5 4 3 DITHEN DINTSEL 2 DEEMPEN 1 0 NBITS Description Data Interface Word Lenght De-emphasis enable Dither enable I2S data format selector -VCM decoupling capacitor selector Reset Value High, Low Low Low Low, Low Low Low AT73C240 Register Register Name: DAC_MISC (Address = 0x0A) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 1:0 2 3 5:4 6 7 6 VCMCAPSEL Name NBITS DEEMPEN DITHEN DINTSEL VCMCAPSEL Not Used 5 4 3 DITHEN DINTSEL Description Data Interface Word Lenght De-emphasis enable Dither enable I2S data format selector VCM decoupling capacitor selector -- 2 DEEMPEN 1 0 NBITS Reset Value High, Low Low Low Low, Low Low Low 7 6484A–PMAAC–04-Jun-09 10. I²S Synchronous Register : IS_CTRL 10.1 AT73C213 Register This register does not exist for AT73C213 product 10.2 AT73C240 Register Register Name: IS_CTRL (Address = 0x0B) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 0 1 2 3 4 5 6 7 8 6 Not Used Name Not Used Not Used IS_CTRL Not Used Not Used Not Used Not Used Not Used 5 Not Used 4 Not Used 3 Not Used Description --Active synchronous I2S master clock ------ 2 IS_CTRL 1 Not Used 0 Not Used Reset Value Low Low Low Low Low Low Low Low Application Note 6484A–PMAAC–04-Jun-09 Application Note 11. DAC Precharge Register : DAC_PRECH 11.1 AT73C213 Register Register Name: DAC_PRECH (Address = 0x0C) Reset State: 0x00 Access: Read/Write 7 PRCHGPDRV Bit 0 1 2 3 4 5 6 7 11.2 6 PRCHGAUX Name ONMSTR PRCHG PRCHGLNIL PRCHGLNIR PRCHGLNOL PRCHGLNOR PRCHGAUX PRCHGPDRV 5 PRCHGLNOR 4 PRCHGLNOL 3 PRCHGLNIR 2 PRCHGLNIL 1 PRCHG Description Master power on control Master pre-charge Left channel Line In pre-charge Right channel Line In pre-charge Left channel Line Out pre-charge Right channel Line Out pre-charge Differential mono auxiliary input pre-charge Differential mono PA driver pre-charge 0 ONMSTR Reset Value Low Low Low Low Low Low Low Low AT73C240 Register Register Name: DAC_PRECH (Address = 0x0C) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 0 1 2 3 4 5 6 7 6 Not Used Name ONMSTR PRCHG PRCHGLNIL PRCHGLNIR PRCHGPDRV Not Used Not Used Not Used 5 Not Used 4 PRCHGPDRV 3 PRCHGLNIR Description Master power on control Master pre-charge Left channel Line In pre-charge Right channel Line In pre-charge Differential mono PA driver pre-charge ---- 2 PRCHGLNIL 1 PRCHG 0 ONMSTR Reset Value Low Low Low Low Low Low Low Low 9 6484A–PMAAC–04-Jun-09 12. DAC Auxiliary Input Gain Register : DAC_AUXG 12.1 AT73C213 Register Register Name: DAC_AUXG (Address = 0x0D) Reset State: 0x05 Access: Read/Write 7 Not Used Bit 4:0 5 6 7 6 Not Used Name AUXG Not Used Not Used Not Used Table 12-1. 5 Not Used 4 3 2 AUXG Description Differential mono auxiliary input analog gain selector ---- 0 Reset Value Low, Low, High, Low, High Low Low Low AUXG Selection Table AUXG Gain Unit AUXG Gain Unit 00000 20 dB 01001 -12 dB 00001 12 dB 01010 -15 dB 00010 9 dB 01011 -18 dB 00011 6 dB 01100 -21 dB 00100 3 dB 01101 -24 dB 00101 0 dB 01110 -27 dB 00110 -3 dB 01111 -30 dB 00111 -6 dB 10000 -33 dB 01000 -9 dB ≥10001 < -60 dB 12.2 1 AT73C240 Register This register does not exist for AT73C240 product 10 Application Note 6484A–PMAAC–04-Jun-09 Application Note 13. DAC Reset Register : DAC_RST 13.1 AT73C213 Register Register Name: DAC_RST (Address = 0x10) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 0 1 2 3 4 5 6 7 13.2 6 Not Used Name RSTZ RESFILZ RESMASK Not Used Not Used Not Used Not Used Not Used 5 Not Used 4 Not Used 3 Not Used 2 RESMASK 1 RESFILZ Description Active low reset of the audio codec Active low reset of the audio codec filter Active high reset mask of the audio codec ------ 0 RSTZ Reset Value Low Low Low Low Low Low Low Low AT73C240 Register Register Name: DAC_RST (Address = 0x10) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 0 1 2 3 4 5 6 7 6 Not Used Name RSTZ RESFILZ Not Used Not Used Not Used Not Used Not Used Not Used 5 Not Used 4 Not Used 3 Not Used Description Active low reset of the audio codec Active low reset of the audio codec filter ------- 2 Not Used 1 RESFILZ 0 RSTZ Reset Value Low Low Low Low Low Low Low Low 11 6484A–PMAAC–04-Jun-09 14. Power Amplifier Control Register : PA_CTRL 14.1 AT73C213 Register Register Name: PA_CTRL (Address = 0x11) Reset State: 0x00 Access: Read/Write 7 Not Used Bit 3:0 4 5 6 7 14.2 6 APAON Name APAGAIN APALP APAPRECH APAON Not Used 5 APAPRECH 4 APALP 3 2 1 0 APAGAIN Description Audio power amplifier gain selector Audio power amplifier low power Audio power amplifier precharge Audio power amplifier enable -- Reset Value Low, Low, Low, Low Low Low Low Low AT73C240 Register Register Name: PA_CTRL (Address = 0x11) Reset State: 0x0F Access: Read/Write 7 Not Used Bit 0 4 5 6 7 12 6 Not Used Name APAGAIN APAPRECH APAON Not Used Not Used 5 APAON 4 APAPRECH Description Audio power amplifier gain selector Audio power amplifier precharge Audio power amplifier enable --- 3 2 1 0 APAGAIN Reset Value High, High, High, High Low Low Low Low Application Note 6484A–PMAAC–04-Jun-09 Application Note 15. Revision History Doc. Rev Date Comments 6484A 04-Jun-09 Creation Change Request Ref. 13 6484A–PMAAC–04-Jun-09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM www.atmel.com/Iproducts/ASIC Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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