TCS3472 Datasheet - Apr. 2013 - V1.0 Color Light-to-digital Converter with IR Filter General Description The TCS3472 device provides a digital return of red, green, blue (RGB), and clear light sensing values. An IR blocking filter, integrated on-chip and localized to the color sensing photodiodes, minimizes the IR spectral component of the incoming light and allows color measurements to be made accurately. The high sensitivity, wide dynamic range, and IR blocking filter make the TCS3472 an ideal color sensor solution for use under varying lighting conditions and through attenuating materials. The TCS3472 color sensor has a wide range of applications including RGB LED backlight control, solid-state lighting, health/fitness products, industrial process controls and medical diagnostic equipment. In addition, the IR blocking filter enables the TCS3472 to perform ambient light sensing (ALS). Ambient light sensing is widely used in display-based products such as cell phones, notebooks, and TVs to sense the lighting environment and enable automatic display brightness for optimal viewing and power savings. The TCS3472, itself, can enter a lower-power wait state between light sensing measurements to further reduce the average power consumption. Figure TCS3472 – 1: Key Benefits and Features Benefits Features Enables accurate color and light sensing measurements under varying lighting conditions by minimizing IR and UV spectral component effects. Red, Green, Blue (RGB), and Clear Light Sensing with IR Blocking Filter • Programmable Analog Gain and Integration Time • 3,800,000:1 Dynamic Range • Very High Sensitivity — Ideally Suited for Operation Behind Dark Glass Programmable interrupt pin enables level-style interrupts when pre-set values are exceeded, thus reducing companion micro-processor overhead. Maskable Interrupt • Programmable Upper and Lower Thresholds with Persistence Filter Enabling a low-power wait-state between RGBC measurements to reduce average power consumption. Power Management • Low Power — 2.5-μA Sleep State • 65-μA Wait State with Programmable Wait State Time from 2.4 ms to > 7 Seconds Datasheet - Apr. 2013 - V1.0 TCS3472 – 1 Benefits Features Digital interfaces are less susceptible to noise. I²C Fast Mode Compatible Interface • Data Rates up to 400 kbit/s • Input Voltage Levels Compatible with VDD or 1.8 VBUS Backward compatibility enables interchangeability and re-usability in systems. Register Set and Pin Compatible with the TCS3x71 Series Reduces PCB space requirements while simplifying designs. Small 2 mm 2.4 mm Dual Flat No-Lead (FN) Package Applications The applications of TCS3472 include: • • • • • RGB LED Backlight Control Light Color Temperature Measurement Ambient Light Sensing for Display Backlight Control Fluid and Gas Analysis Product Color Verification and Sorting End Products and Market Segments • • • • • TVs, Mobile Handsets, Tablets, Computers, and Monitors Consumer and Commercial Printing Medical and Health Fitness Solid State Lighting (SSL) and Digital Signage Industrial Automation Figure TCS3472 – 2: Functional Block Diagram TCS3472 – 2 Datasheet - Apr. 2013 - V1.0 Detailed Description The TCS3472 light-to-digital converter contains a 3 × 4 photodiode array, four analog-to-digital converters (ADC) that integrate the photodiode current, data registers, a state machine, and an I²C interface. The 3 × 4 photodiode array is composed of red-filtered, green-filtered, blue-filtered, and clear (unfiltered) photodiodes. In addition, the photodiodes are coated with an IR-blocking filter. The four integrating ADCs simultaneously convert the amplified photodiode currents to a 16-bit digital value. Upon completion of a conversion cycle, the results are transferred to the data registers, which are double-buffered to ensure the integrity of the data. All of the internal timing, as well as the low-power wait state, is controlled by the state machine. Communication of the TCS3472 data is accomplished over a fast, up to 400 kHz, two-wire I²C serial bus. The industry standard I²C bus facilitates easy, direct connection to microcontrollers and embedded processors. In addition to the I²C bus, the TCS3472 provides a separate interrupt signal output. When interrupts are enabled, and user-defined thresholds are exceeded, the active-low interrupt is asserted and remains asserted until it is cleared by the controller. This interrupt feature simplifies and improves the efficiency of the system software by eliminating the need to poll the TCS3472. The user can define the upper and lower interrupt thresholds and apply an interrupt persistence filter. The interrupt persistence filter allows the user to define the number of consecutive out-of-threshold events necessary before generating an interrupt. The interrupt output is open-drain, so it can be wire-ORed with other devices. Datasheet - Apr. 2013 - V1.0 TCS3472 – 3 The TCS3472 pin assignments are described below. Pin Assignment Figure TCS3472 – 3: Pin Diagram Package FN Dual Flat No-Lead (Top View): Package drawing is not to scale. VDD 1 6 SDA SCL 2 5 INT GND 3 4 NC Figure TCS3472 – 4: Pin Description Pin Number Pin Name 1 VDD 2 SCL 3 GND 4 NC Output No connect — do not connect. 5 INT Output Interrupt — open drain (active low). 6 SDA Input/Output TCS3472 – 4 Pin Type Description Supply voltage. Input I²C serial clock input terminal – clock signal for I²C serial data. Power supply ground. All voltages are referenced to GND. I²C serial data I/O terminal — serial data I/O for I²C. Datasheet - Apr. 2013 - V1.0 Ordering Information Figure TCS3472 – 5: Ordering Information Device Address Package-Leads Interface Description Ordering Number TCS34721† 0x39 FN−6 I²C VBUS = VDD Interface TCS34721FN TCS34723† 0x39 FN−6 I²C VBUS = 1.8 V Interface TCS34723FN TCS34725 0x29 FN−6 I²C VBUS = VDD Interface TCS34725FN TCS34727 0x29 FN−6 I²C VBUS = 1.8 V Interface TCS34727FN †Contact ams for availability. Notes: 1. All products are RoHS compliant and ams green. 2. Buy our products or get free samples online at www.ams.com/ICdirect 3. Technical Support is available at www.ams.com/Technical-Support 4. For further information and requests, email us at [email protected] 5. (or) find your local distributor at www.ams.com/distributor Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Figure TCS3472 – 6: Absolute Maximum Ratings over Operating Free-air Temperature Range (unless otherwise noted) Parameter Min Supply voltage, VDD Max Units Comments 3.8 V All voltages are with respect to GND Input terminal voltage −0.5 3.8 V Output terminal voltage −0.5 3.8 V Output terminal current −1 20 mA Storage temperature range, Tstg −40 85 ºC 2000 V ESD tolerance, human body model Datasheet - Apr. 2013 - V1.0 TCS3472 – 5 All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Electrical Characteristics Figure TCS3472 – 7: Recommended Operating Conditions Symbol VDD TA Parameter Conditions Min Typ Max TCS34721 & TCS34725 (I²C VBUS = VDD) 2.7 3 3.6 TCS34723 & TCS34727 (I²C VBUS = 1.8 V) 2.7 3 3.3 Supply voltage Units V Operating free - air temperature -30 70 ºC Figure TCS3472 – 8: Operating Characteristics, VDD = 3 V, TA = 25ºC (unless otherwise noted) Symbol IDD VOL ILEAK VIH VIL TCS3472 – 6 Parameter Supply current Conditions Min Typ Max Active 235 330 Wait state 65 Sleep state - no I²C activity 2.5 Units μA 10 3 mA sink current 0 0.4 6 mA sink current 0 0.6 Leakage current, SDA, SCL, INT pins -5 5 Leakage current, LDR pin -5 INT SDA output low voltage V μA TCS34721 & TCS34725 0.7 VDD TCS34723 & TCS34727 1.25 5 SCL SDA input high voltage V TCS34721 & TCS34725 0.3 VDD TCS34723 & TCS34727 0.54 SCL SDA input low voltage V Datasheet - Apr. 2013 - V1.0 Figure TCS3472 – 9: Optical Characteristics, VDD=3 V, TA = 25ºC, AGAIN = 16, ATIME = 0xF6(unless otherwise noted) (Note 1) Parameter Red Channel Test Conditions Blue Channel Clear Channel Unit Min Max Min Max Min Max Min Typ Max 0% 15% 10% 42% 65% 88% 11.0 13.8 16.6 λD = 465 nm Note 2 Re Irradiance responsivity Green Channel λD = 525 nm Note 3 4% 25% 60% 85% 10% 45% 13.2 16.6 20.0 λD = 615 nm Note 4 80% 110% 0% 14% 5% 24% 15.6 19.5 23.4 counts /μW /cm2 Notes: 1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel value. 2. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength λ D = 465 nm, spectral halfwidth Δλ½ = 22 nm. 3. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength λ D = 525 nm, spectral halfwidth Δλ½ = 35 nm. 4. The 615 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics: dominant wavelength λ D = 615 nm, spectral halfwidth Δλ½ = 15 nm. Figure TCS3472 – 10: RGBC Characteristics, VDD = 3 V, TA = 25ºC, AGAIN = 16, AEN = 1 (unless otherwise noted) Parameter Conditions Min Typ Max Units Dark ADC count value Ee = 0, AGAIN = 60×, ATIME = 0xD6 (100 ms) 0 1 5 counts ADC integration time step size ATIME = 0xFF 2.27 2.4 2.56 ms ADC number of integration steps (see Note below) 1 256 steps ADC counts per step (see Note below) 0 1024 counts 0 65535 counts ADC count value (see Note below) Gain scaling, relative to 1X gain setting ATIME = 0xC0 (153.6 ms) 4X 3.8 4 4.2 16X 15 16 16.8 60X 58 60 63 X Note: Parameter ensured by design and is not tested. Datasheet - Apr. 2013 - V1.0 TCS3472 – 7 Figure TCS3472 – 11: Wait Characteristics, VDD = 3 V, TA = 25ºC, WEN = 1 (unless otherwise noted) Parameter Wait step size Conditions WTIME = 0xFF Wait number of integration steps (see Note below) Channel Min Typ Max Units 2.27 2.4 2.56 ms 256 steps 1 Note: Parameter ensured by design and is not tested. TCS3472 – 8 Datasheet - Apr. 2013 - V1.0 The timing characteristics of TCS3472 are given below. Timing Characteristics Figure TCS3472 – 12: AC Electrical Characteristics, VDD = 3 V, TA = 25ºC (unless otherwise noted) Parameter† Description Min Typ Max Units 400 kHz f(SCL) Clock frequency (I²C only) t(BUF) Bus free time between start and stop condition 1.3 μs t(HDSTA) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 μs t(SUSTA) Repeated start condition setup time 0.6 μs t(SUSTO) Stop condition setup time 0.6 μs t(HDDAT) Data hold time 0 t(SUDAT) Data setup time 100 ns t(LOW) SCL clock low period 1.3 μs t(HIGH) SCL clock high period 0.6 μs 0 0.9 μs tF Clock/data fall time 300 ns tR Clock/data rise time 300 ns Ci Input pin capacitance 10 pF † Specified by design and characterization; not production tested. Timing Diagrams Figure TCS3472 – 13: Parameter Measurement Information Datasheet - Apr. 2013 - V1.0 TCS3472 – 9 Typical Operating Characteristics Relative Responsivity Figure TCS3472 – 14: Photodiode Spectral Responsivity RGBC λ - Wavelength - nm Normalized Responsivity Figure TCS3472 – 15: Normalized Responsivity vs. Angular Displacement θ - Angular Displacement - º TCS3472 – 10 Datasheet - Apr. 2013 - V1.0 IDD Normalized @ 3V, 25ºC Figure TCS3472 – 16: Normalized IDD vs. VDD and Temperature VDD – V Temperature Coefficient - ppm/ºC Figure TCS3472 – 17: Responsivity Temperature Coefficient λ - Wavelength - nm Datasheet - Apr. 2013 - V1.0 TCS3472 – 11 Principles of Operation System States An internal state machine provides system control of the RGBC and power management features of the device. At power up, an internal power-on-reset initializes the device and puts it in a low-power Sleep state. When a start condition is detected on the I²C bus, the device transitions to the Idle state where it checks the Enable Register (0x00) PON bit. If PON is disabled, the device will return to the Sleep state to save power. Otherwise, the device will remain in the Idle state until the RGBC function is enabled (AEN). Once enabled, the device will execute the Wait and RGBC states in sequence as indicated in Figure TCS3472 - 17. Upon completion and return to Idle, the device will automatically begin a new Wait-RGBC cycle as long as PON and AEN remain enabled. Figure TCS3472 – 18: Simplified State Diagram TCS3472 – 12 Datasheet - Apr. 2013 - V1.0 RGBC Operation The RGBC engine contains RGBC gain control (AGAIN) and four integrating analog-to-digital converters (ADC) for the RGBC photodiodes. The RGBC integration time (ATIME) impacts both the resolution and the sensitivity of the RGBC reading. Integration of all four channels occurs simultaneously and upon completion of the conversion cycle, the results are transferred to the color data registers. This data is also referred to as channel count. The transfers are double-buffered to ensure that invalid data is not read during the transfer. After the transfer, the device automatically moves to the next state in accordance with the configured state machine. Figure TCS3472 – 19: RGBC Operation Note: In this document, the nomenclature uses the bit field name in italics followed by the register address and bit number to allow the user to easily identify the register and bit that controls the function. For example, the power on (PON) is in register 0x00, bit 0. This is represented as PON (r0x00:b0). The registers for programming the integration and wait times are a 2’s compliment values. The actual time can be calculated as follows: ATIME = 256 − Integration Time / 2.4 ms Inversely, the time can be calculated from the register value as follows: Integration Time = 2.4 ms × (256 − ATIME) For example, if a 100-ms integration time is needed, the device needs to be programmed to: 256 − (100 / 2.4) = 256 − 42 = 214 = 0xD6 Conversely, the programmed value of 0xC0 would correspond to: (256 − 0xC0) × 2.4 = 64 × 2.4 = 154 ms. Datasheet - Apr. 2013 - V1.0 TCS3472 – 13 Interrupts The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defined range. While the interrupt function is always enabled and its status is available in the status register (0x13), the output of the interrupt state can be enabled using the RGBC interrupt enable (AIEN) field in the enable register (0x00). Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level. An interrupt can be generated when the Clear data (CDATA) is less than the Clear interrupt low threshold (AILTx) or is greater than the Clear interrupt high threshold (AIHTx). It is important to note that the thresholds are evaluated in sequence, first the low threshold, then the high threshold. As a result, if the low threshold is set above the high threshold, the high threshold is ignored and only the low threshold is evaluated. To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows the user to specify the number of consecutive out-of-range Clear occurrences before an interrupt is generated. The persistence filter register (0x0C) allows the user to set the Clear persistence filter (APERS) value. See the persistence filter register for details on the persistence filter value. Once the persistence filter generates an interrupt, it will continue until a special function interrupt clear command is received (see command register). Figure TCS3472 – 20: Programmable Interrupt TCS3472 – 14 Datasheet - Apr. 2013 - V1.0 System Timing The system state machine shown in Figure TCS3472 - 18 provides an overview of the states and state transitions that provide system control of the device. This section highlights the programmable features, which affect the state machine cycle time, and provides details to determine system level timing. When the power management feature is enabled (WEN), the state machine will transition to the Wait state. The wait time is determined by WLONG, which extends normal operation by 12× when asserted, and WTIME. The formula to determine the wait time is given in the box associated with the Wait state in Figure TCS3472 - 21. When the RGBC feature is enabled (AEN), the state machine will transition through the RGBC Init and RGBC ADC states. The RGBC Init state takes 2.4 ms, while the RGBC ADC time is dependent on the integration time (ATIME). The formula to determine RGBC ADC time is given in the associated box in Figure TCS3472 - 21. If an interrupt is generated as a result of the RGBC cycle, it will be asserted at the end of the RGBC ADC. Figure TCS3472 – 21: Detailed State Diagram Notes: 1. There is a 2.4 ms warm-up delay if PON is enabled. If PON is not enabled, the device will return to the Sleep state as shown. 2. PON, WEN, and AEN are fields in the Enable register (0x00). Datasheet - Apr. 2013 - V1.0 TCS3472 – 15 Power Management Power consumption can be managed with the Wait state, because the Wait state typically consumes only 65 μA of IDD current. An example of the power management feature is given below. With the assumptions provided in the example, average IDD is estimated to be 152 μA. Figure TCS3472 – 22: Power Management System State Machine State Programmable Parameter Programmed Value WTIME 0xEE WLONG 0 Wait RGBC Init RGBC ADC ATIME 0xEE Duration Typical Current 43.2 ms 0.065 mA 2.40 ms 0.235 mA 43.2 ms 0.235 mA Average I DD Current = ((43.2 × 0.065) + (43.2 × 0.235) + (2.40 × 0.235)) / 89 ≈ 152 μA Keeping with the same programmed values as the example, Figure TCS3472 - 23 shows how the average IDD current is affected by the Wait state time, which is determined by WEN, WTIME, and WLONG. Note that the worst-case current occurs when the Wait state is not enabled. Figure TCS3472 – 23: Average IDD Current WEN WTIME WLONG WAIT State Average IDD Current 0 n/a n/a 0 ms 291 μA 1 0xFF 0 2.40 ms 280 μA 1 0XEE 0 43.2 ms 152 μA 1 0x00 0 614 ms 82 μA 1 0x00 1 7.37 s 67 μA TCS3472 – 16 Datasheet - Apr. 2013 - V1.0 Interface and control are accomplished through an I²C serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. The devices support the 7-bit I²C addressing protocol. I²C Protocol The I²C standard provides for three types of bus transaction: read, write, and a combined protocol (Figure TCS3472 - 24). During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the register address from the previous command will be used for data access. Likewise, if the MSB of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. The command byte contains either control information or a 5-bit register address. The control commands can also be used to clear interrupts. The I²C bus protocol was developed by Philips (now NXP). For a complete description of the I²C protocol, please review the NXP I²C design specification at http://www.I2C−bus.org/references/. Figure TCS3472 – 24: I²C Protocols A N P R S Acknowledge (0) Not Acknowledged (1) Stop Condition Read (1) Start Condition Datasheet - Apr. 2013 - V1.0 Sr W Repeated Start Condition Write (0) Continuation of Protocol Master - to - Slave Slave - to - Master TCS3472 – 17 The TCS3472 is controlled and monitored by data registers and a command register accessed through the serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Figure TCS3472 - 25. Register Description Figure TCS3472 – 25: Register Set Address −− Register Name COMMAND R/W W Register Function Reset Value Specifies register address 0x00 0x00 ENABLE R/W Enables states and interrupts 0x00 0x01 ATIME R/W RGBC time 0xFF 0x03 WTIME R/W Wait time 0xFF 0x04 AILTL R/W Clear interrupt low threshold low byte 0x00 0x05 AILTH R/W Clear interrupt low threshold high byte 0x00 0x06 AIHTL R/W Clear interrupt high threshold low byte 0x00 0x07 AIHTH R/W Clear interrupt high threshold high byte 0x00 0x0C PERS R/W Interrupt persistence filter 0x00 0x0D CONFIG R/W Configuration 0x00 0x0F CONTROL R/W Control 0x00 0x12 ID R Device ID 0x13 STATUS R Device status 0x00 0x14 CDATAL R Clear data low byte 0x00 0x15 CDATAH R Clear data high byte 0x00 0x16 RDATAL R Red data low byte 0x00 0x17 RDATAH R Red data high byte 0x00 0x18 GDATAL R Green data low byte 0x00 0x19 GDATAH R Green data high byte 0x00 0x1A BDATAL R Blue data low byte 0x00 0x1B BDATAH R Blue data high byte 0x00 ID The mechanics of accessing a specific register depends on the specific protocol used. See the section on I²C protocols on the previous pages. In general, the COMMAND register is written first to specify the specific control-status-data register for subsequent read/write operations. TCS3472 – 18 Datasheet - Apr. 2013 - V1.0 The COMMAND registers specifies the address of the target register for future write and read operations. Command Register 7 6 CMD 5 4 3 2 TYPE Fields Bits CMD 7 1 0 ADDR/SF Description Select Command Register. Must write as 1 when addressing COMMAND register. Selects type of transaction to follow in subsequent data transfers: FIELD VALUE TYPE 6:5 INTEGRATION TIME 00 Repeated byte protocol transaction 01 Auto-increment protocol transaction 10 Reserved — Do not use 11 Special function — See description below Byte protocol will repeatedly read the same register with each data access. Block protocol will provide auto-increment function to read successive bytes. Address field/special function field. Depending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-data register for subsequent read and write transactions. The field values listed below only apply to special function commands: FIELD VALUE ADDR/SF READ VALUE 4:0 00110 Clear channel interrupt clear Other Reserved — Do not write The Clear channel interrupt clear special function clears any pending interrupt and is self-clearing. Datasheet - Apr. 2013 - V1.0 TCS3472 – 19 The ENABLE register is used primarily to power the TCS3472 device ON and OFF, and enable functions and interrupts as shown below. Enable Register (0x00) 7 6 5 Reserved 4 3 2 1 0 AIEN WEN Reserved AEN PON Fields Bits Description Reserved 7:5 AIEN 4 RGBC interrupt enable. When asserted, permits RGBC interrupts to be generated. WEN 3 Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the wait timer. Reserved 2 Reserved. Write as 0. AEN 1 RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates the RGBC. Writing a 0 disables the RGBC. PON (Notes 1, 2) 0 Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator. Reserved. Write as 0. Notes: 1. See Power Management section for more information. 2. A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated. TCS3472 – 20 Datasheet - Apr. 2013 - V1.0 The RGBC timing register controls the internal integration time of the RGBC clear and IR channel ADCs in 2.4-ms increments. Max RGBC Count = (256 − ATIME) × 1024 up to a maximum of 65535. RGBC Timing Register (0x01) Fields ATIME Bits Description VALUE INTEG_CYCLES TIME MAX COUNT 0xFF 1 2.4 ms 1024 0xF6 10 24 ms 10240 0xD5 42 101 ms 43008 0xC0 64 154 ms 65535 0x00 256 700 ms 65535 7:0 Wait time is set 2.4 ms increments unless the WLONG bit is asserted, in which case the wait times are 12× longer. WTIME is programmed as a 2’s complement number. Wait Time Register (0x03) Fields WTIME Bits Description REGISTER VALUE WAIT TIME TIME (WLONG= 0) TIME (WLONG= 1) 0xFF 1 2.4 ms 0.029 sec 0xAB 85 204 ms 2.45 sec 0x00 256 614 ms 7.4 sec 7:0 The RGBC interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation. If the value generated by the clear channel crosses below the lower threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin. RGBC Interrupt Threshold Registers (0x04 − 0x07) Register Address Bits AILTL 0x04 7:0 RGBC clear channel low threshold lower byte AILTH 0x05 7:0 RGBC clear channel low threshold upper byte AIHTL 0x06 7:0 RGBC clear channel high threshold lower byte AIHTH 0x07 7:0 RGBC clear channel high threshold upper byte Datasheet - Apr. 2013 - V1.0 Description TCS3472 – 21 The persistence register controls the filtering interrupt capabilities of the device. Configurable filtering is provided to allow interrupts to be generated after each integration cycle or if the integration has produced a result that is outside of the values specified by the threshold register for some specified amount of time. Persistence Register (0x0C) 7 6 5 4 3 2 Reserved Field Bits PPERS 7:4 1 0 APERS Description Reserved Interrupt persistence. Controls rate of interrupt to the host processor. APERS TCS3472 – 22 FIELD VALUE MEANING INTERRUPT PERSISTENCE FUNCTION 0000 Every 0001 1 1 clear channel value outside of threshold range 0010 2 2 clear channel consecutive values out of range 0011 3 3 clear channel consecutive values out of range 0100 5 5 clear channel consecutive values out of range 0101 10 10 clear channel consecutive values out of range 0110 15 15 clear channel consecutive values out of range 0111 20 20 clear channel consecutive values out of range 1000 25 25 clear channel consecutive values out of range 1001 30 30 clear channel consecutive values out of range 1010 35 35 clear channel consecutive values out of range 1011 40 40 clear channel consecutive values out of range 1100 45 45 clear channel consecutive values out of range 1101 50 50 clear channel consecutive values out of range 1110 55 55 clear channel consecutive values out of range 1111 60 60 clear channel consecutive values out of range Every RGBC cycle generates an interrupt 3:0 Datasheet - Apr. 2013 - V1.0 Configuration Register (0x0D) 7 6 The configuration register sets the wait long time 5 4 3 2 Reserved 1 0 WLONG Reserved Fields Bits Description Reserved 7:2 WLONG 1 Wait Long. When asserted, the wait cycles are increased by a factor 12× from that programmed in the WTIME register. Reserved 0 Reserved. Write as 0. Reserved. Write as 0. The Control register provides eight bits of miscellaneous control to the analog block. These bits typically control functions such as gain settings and/or diode selection. Control Register (0x0F) 7 6 5 4 3 2 1 Reserved Fields Bits Reserved 7:2 0 AGAIN Description Reserved. Write as 0. RGBC Gain Control. AGAIN FIELD VALUE RGBC GAIN VALUE 00 1X gain 01 4X gain 10 16X gain 11 60X gain 1:0 Datasheet - Apr. 2013 - V1.0 TCS3472 – 23 The ID Register provides the value for the part number. The ID register is a read-only register. ID Register (0x12) 7 6 5 4 3 2 1 0 ID Field Bits ID 7:0 Description 0x44 = TCS34721 and TCS34725 Part number identification 0x19 0x4D = TCS34723 and TCS34727 The Status Register provides the internal status of the device. This register is read only. Status Register (0x13) 7 6 5 Reserved Field Bits Reserved 7:5 AINT 4 Reserved 3:1 AVALID 0 TCS3472 – 24 4 AINT 3 2 Reserved 1 0 AVALID Description Reserved. RGBC clear channel Interrupt. Reserved. RGBC Valid. Indicates that the RGBC channels have completed an integration cycle. Datasheet - Apr. 2013 - V1.0 RGBC Channel Data Registers (0x14 – 0x1B) Clear, red, green, and blue data is stored as 16-bit values. To ensure the data is read correctly, a two-byte read I²C transaction should be used with a read word protocol bit set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. Register Address Bits CDATA 0x14 7:0 Clear data low byte CDATAH 0x15 7:0 Clear data high byte RDATA 0x16 7:0 Red data low byte RDATAH 0x17 7:0 Red data high byte GDATA 0x18 7:0 Green data low byte GDATAH 0x19 7:0 Green data high byte BDATA 0x1A 7:0 Blue data low byte BDATAH 0x1B 7:0 Blue data high byte Datasheet - Apr. 2013 - V1.0 Description TCS3472 – 25 Application Information: Hardware PCB Pad Layout Suggested PCB pad layout guidelines for the Dual Flat No-Lead (FN) surface mount package are shown in Figure TCS3472 - 26. Figure TCS3472 – 26: Suggested FN Package PCB Layout Pads can be extended further if hand soldering is needed. Notes: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. TCS3472 – 26 Datasheet - Apr. 2013 - V1.0 Package Drawings and Markings Figure TCS3472 – 27: Package FN – Dual Flat No-Lead Packaging Configuration Notes: 1. All linear dimensions are in micrometers. Dimension tolerance is ±20 μm unless otherwise noted. 2. The die is centered within the package within a tolerance of ± 3 mils. 3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55. 4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish. 5. This package contains no lead (Pb). 6. This drawing is subject to change without notice. Datasheet - Apr. 2013 - V1.0 TCS3472 – 27 Mechanical Data Figure TCS3472 – 28: Carrier Tape and Reel Information Notes: 1. All linear dimensions are in millimeters. Dimension tolerance is ± 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing A0, B 0, and K 0 are defined in ANSI EIA Standard 481-B 2001. 4. Each reel is 178 millimeters in diameter and contains 3500 parts. 5. ams packaging tape and reel conform to the requirements of EIA Standard 481-B. 6. In accordance with EIA standard, device pin 1 is located next to sprocket holes in the tape. 7. This drawing is subject to change without notice. TCS3472 – 28 Datasheet - Apr. 2013 - V1.0 Soldering and Storage Information Soldering Information The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The process, equipment, and materials used in these test are detailed below. The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure TCS3472 – 29: Solder Reflow Profile Parameter Reference Average temperature gradient in preheating Device 2.5 ºC/sec tsoak 2 to 3 minutes Time above 217 ºC (T1) t1 Max 60 sec Time above 230 ºC (T2) t2 Max 50 sec Time above Tpeak - 10 ºC (T3) t3 Max 10 sec Peak temperature in reflow Tpeak 260 ºC Soak time Temperature gradient in cooling Max -5 ºC/sec Figure TCS3472 – 30: Solder Reflow Profile Graph Note: Not to scale – for reference only. Datasheet - Apr. 2013 - V1.0 TCS3472 – 29 Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. The Moisture Barrier Bags should be stored under the following conditions: • Temperature Range < 40°C • Relative Humidity < 90% • Total Time - No longer than 12 months from the date code on the aluminized envelope if unopened. Rebaking of the reel will be required if the devices have been stored unopened for more than 12 months and the Humidity Indicator Card shows the parts to be out of the allowable moisture region. Opened reels should be used within 168 hours if exposed to the following conditions: • Temperature Range < 30°C • Relative Humidity < 60% If rebaking is required, it should be done at 50°C for 12 hours. The FN package has been assigned a moisture sensitivity level of MSL 3. TCS3472 – 30 Datasheet - Apr. 2013 - V1.0 RoHS Compliant and ams Green Statement The term RoHS complaint means that ams products fully comply with current RoHS directive. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green means RoHS compliant and no Sb/Br). ams defines Green that additionally to RoHS compliance our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information and Disclaimer The information provided in this statement represents ams knowledge and belief as of the date that it is provided. ams bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams and ams suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Datasheet - Apr. 2013 - V1.0 TCS3472 – 31 Copyrights Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Disclaimer Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. TCS3472 – 32 Datasheet - Apr. 2013 - V1.0