AMD TFE 2011 Infineon - Extremely high perforemance silicon and package technology for high power density voltage regulations Copyright © Infineon Technologies 2011. All rights reserved. Product requirement •Higher power density •Higher efficiency •Better price performance Silicon Technology Packaging Technology 2011/10/3 Copyright © Infineon Technologies 2011. All rights reserved. RDS,on distribution 60% 50% 30% 20% 10% 0% packaging 40% OptiMOS™3 30V in TO-220 silicon 600V OptiMOS™3 30V in SSO8 Substrate Epi Channel Bond-wires/Clip Metallisation Drain-pin packaging 70% silicon 80% silicon 90% 30V Vds depending resistance ‘silicon limit’ 30V 100% packaging Relative Contribution to total resistance Resistance distribution for OptiMOS™ and CoolMOS™ in TO-220 and SSO8 packages Source-pin CoolMOS™ 600V in TO-220 • Packaging is crucial for LV MOSFETs • Epi resistance ~ Vds2.5 (silicon limit) dominating at higher Vds Copyright © Infineon Technologies 2011. All rights reserved. 2011/10/3 MOSFET Technology as a Key for High PowerDensity converters MOSFET packaging package contribution to Rds(on) for BiC devices 90% 30V 80% 60V 70% 80V 100V 60% 150V high package contribution, Si technology is hindered by package 50% 40% * 30% 20% 10% * 0% 0 1 2 3 4 5 6 7 8 * without layout contribution 2011/10/3 Copyright © Infineon Technologies 2011. All rights reserved. Increase efficiency in all load conditions How is performance improvement achieved ? Consequent reduction of efficiency relevant Figure of Merits … 120.0 -45% New OptiMOS™ 25V OptiMOS™3 -70% Figure of Merit [mOhmxnC] 100.0 80.0 -50% 60.0 40.0 -50% -45% 20.0 0.0 FOMg(Vgs=4.5),typ FOMg(Vgs=4.5V),typ FOMg(Vgs=10),typ FOMg(Vgs=10V),typ FOMgd(Vgs=4.5V),typ FOMgd(Vgs=4.5V),typ FOMgd(Vgs=10V),typ FOMgd(Vgs=10V),typ FOMQoss FOMgQoss (Vgs=4.5V,typ (Vgs=10V),typ Comparison for BSC050NE2LS New OptiMOS™ 25V and BSC090N03LS OptiMOS™3 Copyright © Infineon Technologies 2011. All rights reserved. 03.10.2011 Leadless Power packages The CanPak uses the DirectFET* technology *DirectFET(R) is a trademark of international rectifier corporation; DirectFET(R) technology is licensed from international rectifier corporation Copyright © Infineon Technologies 2011. All rights reserved. 2011/10/3 Reduce footprint enabling new solutions Best in Class OptiMOS™3 S3O8 3.5 mOhm Best in Class for new OptiMOS™ 1.9 mOhm -46% 3.3x3.3x1.0 mm New solution with new OptiMOS™ 30V Today‘s standard … S3O8 SuperSO8 60% footprint reduction 6 mOhm + 2.0 mOhm 6 mOhm + 1.9 mOhm footprint: 60 mm² Copyright © Infineon Technologies 2011. All rights reserved. footprint: 22 mm² 03.10.2011 Infineon high-performance power stages S3O8 DrMOS CanPAK S3O8/SSO8 SS08 22.2mm x 8.0mm* 20.6mm x 9.0mm 21.5mm x 8.7mm* 25.2 mm x 8.7 mm 27.6mm x 11.5mm 177 mm² 185 mm² 187 mm² 220 mm² 318.4 mm² 10/3/2011 Copyright © Infineon Technologies 2011. All rights reserved. Note: * FET driver mounted on backside of board. SS08 dimensions with driver on backside 27.6mm x 9.0mm Page 8 Area consumption [mm²] Area consumption of Infineon PowerStages * 10/3/2011 * Copyright © Infineon Technologies 2011. All rights reserved. * * Page 9 Area consumption in layout [mm²] Area consumption of Infineon PowerStages * 10/3/2011 * Copyright © Infineon Technologies 2011. All rights reserved. Page 10 OptiMOS™ in various discrete packages … Top side cooling Ultra-low inductance Low profile 96% (Peak) Efficiency [%] SuperSO8 5.2x6.2 mm² CanPAK-S/M 4.9x3.6/4.9x6.3mm² 93% ! S3O8 TDC ~ 35A TDC ~ 35A 3.3x3.3 mm² TDC ~ 20A 90% D-PAK 87% 6.5x9.6 mm² TDC ~ 25A 0.2 0.5 0.7 0.9 ? Power density [W/mm²] Copyright © Infineon Technologies 2011. All rights reserved. Page 11 Maximum Current Capabilities at Tcase=110°C Vin=12V, Vout=1.2V, LL=0.0 mOhm, fswitch=434 kHz, 100 lfm no heatsink, Tamb=25°C, 1 phase operation 2 oz each layer. In thermal equilibrium ~20 mins at Iout specified. SuperSO8 110°C 29.0°C 90°C High_Side High_Side 110°C 40 88.7°C 41.2°C 60 80 100 110.0°C 40 3.0 mOhm+1.3 mOhm 5.0 mOhm+1.0 mOhm 38.1°C 60 80 111.6°C 100 3.6 mOhm+1.8 mOhm CanPAK 60 DrMOS 80 S3O8 Low_Side Low_Side Low_Side High_Side 110°C 40A Tcase=110°C 45A Tcase=110°C 49A Tcase=110°C Copyright © Infineon Technologies 2011. All rights reserved. 49A Tcase=90°C Page 12 System efficiency for OptiMOS™ products 4 phases, 313 kHz, 210 nH, VR12 compatible solution (SB 130W) System Efficiency 95 94 93.3% peak at 60A CanPAK 93 90.5% at 140A 92 Efficiency (%) (35A/phase) S308 + SS08 91 90 89 Conditions for measurements Vin=12V, Vout=1.2V, Vdrive=5V, Lout=210 nH fswitch=313kHz, Tamb=25°C, 300 lfm 88 87 CanPAK (BSF030NE2LQ, BSB013NE2LXI) S3O8/SSO8 (BSZ036NE2LS, BSC010NE2LS) 86 85 Output Load Current (A) Copyright © Infineon Technologies 2011. All rights reserved. Page 13 CanPAK thermal performance for 2 phase memory Both phases thermo coupled before heatsink attachment Phases thermo coupled after heatsink assembly Thermocouples were used for accurate thermal measurements When applying a heatsink the thermocouples were attached through a small hole in the heatsink 10/3/2011 Copyright © Infineon Technologies 2009. All rights reserved. Page 14 Thermal rise of 2nd phase LS CanPAK at 25C and 55C ambient, with 1min soak time at 2A load step (total 28min) Temperature rise of the hotest phase 2 90 with heatsink mounted, 300 lfm airflow 85 80 75 70 24C temp rise at 80A Temperature rise (C) 65 15C temp rise 60 Ambient 55C level 55 50 45 40 37C at 60A 35 13C temp rise 30 Ambient 25C level 25 20 15 60A reached after 28min of 2A load step 10 5 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 0 Output Load Current (A) For Tamb=25C CanPAK temperature only increases by 15C for Iout=60A (blue graph) At Tamb=55C CanPAK temperature rise is just 24C at Iout=80A (red graph) 10/3/2011 Copyright © Infineon Technologies 2009. All rights reserved. Page 15 BLADE™3x3 solder terminations vias to substrate isolation layer vias to die isolation layer 1.2 mOhm in 3.0x3.4 mm2 footprint substrate die Double sided cooling via metal backplate Source down concept reduces source inductance to ~0 nH for maximized efficiency Footprint allows layout optimization for smallest loop inductance Re-distribution layer allows incorporation of various die sizes Copyright © Infineon Technologies 2011. All rights reserved. Page 16 Balde 3x3 length x width in mm² 3.0 x 3.4 footprint in mm² 10.2 height in mm 0.6 power in W (Tc=25°C) 78 max ID in A (Tc=25°C) 50 Rthja in K/W (6cm² cooling) 50 Tjmax in °C 150 RDS(on) in mOhm 1.2 – 5.0 package inductance in nH D G S 0.01 package resistance in mOhm 0.2 top side cooling yes bottom side cooling yes paralleling/routing applications standard • • • • Server NB, VGA, telekom (POL,) Small footprint and low profile Compact design Low package resistance Minimized conduction losses Low package inductance (source down) Reduced switching losses Low thermal resistance top side Top side / Double side cooling Copyright © Infineon Technologies 2009. All rights reserved. Efficiency for BLADE™3x3 94 93% peak 550 kHz 93 450 kHz 350 kHz 92 91 90% peak 90 Efficiency (%) 89 88 87 86 12.0 ‐ 1.20 ‐ for 320nH ‐ 350kHz ‐ BSN047NE2LS+BSN012NE2LS, r‐22 Conditions measurements 85 12.0 ‐ 1.20 ‐ 320nH ‐ 450kHz ‐ BSN047NE2LS+BSN012NE2LS, r‐23 12.0 ‐ 1.20 ‐ 320nH ‐ 550kHz ‐ BSN047NE2LS+BSN012NE2LS, r‐25 Vin=12V, Vout=1.2V, no LL Vdrive=5V, Lout=320 nH Tamb=25°C, no airflow, no heatsink Included Losses: PowerStage, Driver, Inductor 84 83 82 81 35.0 34.0 33.0 32.0 31.0 30.0 29.0 28.0 27.0 26.0 25.0 24.0 23.0 22.0 21.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 9.0 10.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 80 Iout (A) BLADE™3x3 achieves 93% peak efficiency and 90% at Iout=35A Copyright © Infineon Technologies 2011. All rights reserved. 10.02.2010