AMD 890FX Databook Technical Reference Manual Rev 3.00 P/N: 43403_890FX_ds_pub © 2012 Advanced Micro Devices, Inc. Trademarks AMD, the AMD Arrow logo, AMD Phenom, AMD Cool'n'Quiet, and combinations thereof, ATI, the ATI logo, Radeon, and CrossFire are trademarks of Advanced Micro Devices, Inc. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Microsoft, Windows, and Windows Vista are registered trademarks of Microsoft Corporation. PCI Express and PCIe are registered trademarks of PCI-SIG. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Disclaimer The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to this document including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD shall not be liable for any damage, loss, expense, or claim of loss of any kind or character (including without limitation direct, indirect, consequential, exemplary, punitive, special, incidental or reliance damages) arising from use of or reliance on this document. No license, whether express, implied, arising by estoppel, or otherwise, to any intellectual property rights are granted by this publication. Except for AMD product purchased pursuant to AMD's Standard Terms and Conditions of Sale, and then only as expressly set forth therein, AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. © 2012 Advanced Micro Devices, Inc. All rights reserved. Table of Contents Chapter 1: Overview 1.1 Introducing AMD 890FX/990X/970 ..................................................................................................................................1-1 1.2 RD890 Features...................................................................................................................................................................1-1 1.2.1 CPU Interface .......................................................................................................................................................1-1 1.2.2 PCI Express® Interface ........................................................................................................................................1-1 1.2.3 A-Link Express III Interface ................................................................................................................................1-1 1.2.4 Power Management Features ...............................................................................................................................1-2 1.2.5 PC Design Guide Compliance..............................................................................................................................1-2 1.2.6 Test Capability Features .......................................................................................................................................1-2 1.2.7 Packaging .............................................................................................................................................................1-2 1.3 Software Features................................................................................................................................................................1-2 1.4 Device ID ............................................................................................................................................................................1-2 1.5 Branding Diagrams .............................................................................................................................................................1-3 1.6 Conventions and Notations .................................................................................................................................................1-3 1.6.1 Pin Names.............................................................................................................................................................1-3 1.6.2 Pin Types ..............................................................................................................................................................1-3 1.6.3 Numeric Representation .......................................................................................................................................1-4 1.6.4 Hyperlinks ............................................................................................................................................................1-4 1.6.5 Acronyms and Abbreviations ...............................................................................................................................1-4 Chapter 2: Functional Descriptions 2.1 HyperTransport™ Interface ................................................................................................................................................2-1 2.1.1 Overview ..............................................................................................................................................................2-1 2.1.2 HyperTransport™ Flow Control Buffers .............................................................................................................2-3 2.2 IOMMU ..............................................................................................................................................................................2-4 2.3 PCI Express®.....................................................................................................................................................................2-5 2.3.1 PCIe® Ports..........................................................................................................................................................2-5 2.3.2 PCIe® Reset Signals ............................................................................................................................................2-5 2.4 External Clock Chip............................................................................................................................................................2-6 Chapter 3: Pin Descriptions and Strap Options 3.1 Pin Assignment Top View ..................................................................................................................................................3-2 3.2 RD890 Interface Block Diagram ........................................................................................................................................3-4 3.3 CPU HyperTransport™ Interface .......................................................................................................................................3-4 3.4 PCI Express® Interfaces .....................................................................................................................................................3-5 3.4.1 Interface for External Graphics Controllers .........................................................................................................3-5 3.4.2 Interface for General Purpose External Devices ..................................................................................................3-5 3.4.3 A-Link Express III Interface to Southbridge........................................................................................................3-6 3.4.4 Miscellaneous PCI Express® Signals ..................................................................................................................3-6 3.5 Clock Interface ....................................................................................................................................................................3-6 3.6 Power Management Pins.....................................................................................................................................................3-7 3.7 Miscellaneous Pins..............................................................................................................................................................3-7 3.8 Power Pins...........................................................................................................................................................................3-7 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 RD890 Databook 3.00 Table of Contents-1 3.9 Ground Pins........................................................................................................................................................................ 3-9 3.10 Strapping Options........................................................................................................................................................... 3-10 Chapter 4: Timing Specifications 4.1 HyperTransport™ Bus Timing .......................................................................................................................................... 4-1 4.2 PCI Express® Differential Clock AC Specifications......................................................................................................... 4-1 4.3 HyperTransport™ Reference Clock Timing Parameters ................................................................................................... 4-1 4.4 OSCIN Reference Clock Timing Parameters..................................................................................................................... 4-2 4.5 Power Rail Sequence.......................................................................................................................................................... 4-2 4.5.1 Power Up ............................................................................................................................................................. 4-3 4.5.2 Power Down ........................................................................................................................................................ 4-4 Chapter 5: Electrical Characteristics and Physical Data 5.1 Electrical Characteristics.................................................................................................................................................... 5-1 5.1.1 Maximum and Minimum Ratings........................................................................................................................ 5-1 5.1.2 DC Characteristics ............................................................................................................................................... 5-1 5.2 RD890 Thermal Characteristics ......................................................................................................................................... 5-2 5.2.1 RD890 Thermal Limits........................................................................................................................................ 5-2 5.2.2 Thermal Diode Characteristics ............................................................................................................................ 5-2 5.3 Package Information .......................................................................................................................................................... 5-4 5.3.1 Pressure Specification.......................................................................................................................................... 5-5 5.3.2 Board Solder Reflow Process Recommendations ............................................................................................... 5-6 Chapter 6: Power Management and ACPI 6.1 ACPI Power Management Implementation ....................................................................................................................... 6-1 Chapter 7: Testability 7.1 Test Capability Features..................................................................................................................................................... 7-1 7.2 Test Interface...................................................................................................................................................................... 7-1 7.3 XOR Tree ........................................................................................................................................................................... 7-1 7.3.1 Brief Description of an XOR Tree....................................................................................................................... 7-1 7.3.2 Description of the XOR Tree for the RD890....................................................................................................... 7-2 7.3.3 XOR Tree Activation........................................................................................................................................... 7-2 7.3.4 XOR Tree for the RD890 .................................................................................................................................... 7-3 7.4 VOH/VOL Test .................................................................................................................................................................. 7-4 7.4.1 Brief Description of a VOH/VOL Tree ............................................................................................................... 7-4 7.4.2 VOH/VOL Tree Activation ................................................................................................................................. 7-5 7.4.3 VOH/VOL pin list ............................................................................................................................................... 7-6 Appendix A: Pin Listings 7.5 RD890 Pin Listing Sorted by Ball Reference .................................................................................................................... A-2 A.1 RD890 Pin Listing Sorted by Pin Name ........................................................................................................................... A-9 Appendix B: Revision History 43403 AMD 890FX Databook 3.00 Table of Contents-2 © 2012 Advanced Micro Devices, Inc. Proprietary List of Figures Figure 1-1: Figure 1-2: Figure 2-1: Figure 2-2: Figure 2-3: Figure 3-1: Figure 4-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 7-1: Figure 7-2: RD890 Branding Diagram for A21 Engineering Sample ........................................................................................... 1-3 RD890 Branding Diagram for A21 Production Sample ............................................................................................. 1-3 RD890 Internal Blocks and Interfaces ........................................................................................................................ 2-1 HyperTransport™ Interface Block Diagram ............................................................................................................... 2-2 RD890 HyperTransport™ Interface Signals ............................................................................................................... 2-3 RD890 Interface Block Diagram ................................................................................................................................. 3-4 RD890 Power Rail Power Up Sequence ..................................................................................................................... 4-3 RD890 692-Pin FCBGA Package Outline .................................................................................................................. 5-4 RD890 Ball Arrangement (Bottom View) .................................................................................................................. 5-5 RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile .............................................................. 5-7 XOR Tree .................................................................................................................................................................... 7-2 Sample of a Generic VOH/VOL Tree ......................................................................................................................... 7-5 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 List of Figures-1 This page is left blank intentionally. 43403 AMD 890FX Databook 3.00 List of Figures-2 © 2012 Advanced Micro Devices, Inc. Proprietary List of Tables Table 1-1: Pin Type Codes ..............................................................................................................................................................1-4 Table 1-2: Acronyms and Abbreviations ........................................................................................................................................1-4 Table 2-1: RD890 HyperTransport™ Flow Control Buffers ..........................................................................................................2-3 Table 2-2: Possible Configurations for the PCI Express® General Purpose Links ........................................................................2-5 Table 3-1: HyperTransport™ Interface ...........................................................................................................................................3-4 Table 3-2: 2 x 16 or 4 x 8 PCI Express® Interface for External Graphics .....................................................................................3-5 Table 3-3: PCI Express® Interface for General Purpose External Devices ....................................................................................3-5 Table 3-4: 1 x 4 Lane A-Link Express III Interface for Southbridge .............................................................................................3-6 Table 3-5: Miscellaneous PCI Express® Signals ............................................................................................................................3-6 Table 3-6: Clock Interface ...............................................................................................................................................................3-6 Table 3-7: Power Management Pins ...............................................................................................................................................3-7 Table 3-8: Miscellaneous Pins ........................................................................................................................................................3-7 Table 3-9: Power Pins .....................................................................................................................................................................3-7 Table 3-10: Ground Pins .................................................................................................................................................................3-9 Table 3-11: Strap Definitions for the RD890 ................................................................................................................................3-10 Table 3-12: Strap Definition for STRAP_PCIE_GPP_CFG .........................................................................................................3-10 Table 4-1: Timing Requirements for PCIe® Differential Clocks (GFX_REFCLK, GFX2_REFCLK, and GPP_REFCLK at 100MHz) .........................................................................................................................................................................................4-1 Table 4-2: Timing Requirements for HyperTransport™ Reference Clock (100MHz) ...................................................................4-1 Table 4-3: Timing Requirements for OSCIN Reference Clock (14.3181818MHz) .......................................................................4-2 Table 4-4: Power Rail Groupings for the RD890 ...........................................................................................................................4-2 Table 4-5: RD890 Power Rail Power-up Sequence ........................................................................................................................4-3 Table 5-1: Power Rail Maximum and Minimum Voltage Ratings .................................................................................................5-1 Table 5-1: DC Characteristics for PCIe® Differential Clocks (GFX_REFCLK, GFX2_REFCLK, and GPP_REFCLK at 100MHz) ..........................................................................................................................................................................................................5-1 Table 5-2: DC Characteristics for 1.8V GPIO Pads ........................................................................................................................5-1 Table 5-3: DC Characteristics for the HyperTransport™ 100MHz Differential Clock (HT_REFCLK) .......................................5-2 Table 5-4: RD890 Thermal Limits ..................................................................................................................................................5-2 Table 5-5: RD890 692-Pin FCBGA Package Physical Dimensions ...............................................................................................5-4 Table 5-6: Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder ......................................................................5-6 Table 6-1: ACPI States Supported by the RD890 ...........................................................................................................................6-1 Table 7-1: Pins on the Test Interface ..............................................................................................................................................7-1 Table 7-2: Example of an XOR Tree ..............................................................................................................................................7-2 Table 7-3: RD890 XOR Tree ..........................................................................................................................................................7-3 Table 7-4: Truth Table for the VOH/VOL Tree Outputs ................................................................................................................7-5 Table 7-5: RD890 VOH/VOL Tree ................................................................................................................................................7-6 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 List of Tables-1 This page intentionally left blank. 43403 AMD 890FX Databook 3.00 List of Tables-2 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 1 Overview 1.1 Introducing AMD 890FX AMD 890FX (referred to by its code name “RD890” in this document) is the system logic of the latest platform from AMD that enables its next generation CPUs with the leading ATI CrossFire™ solutions. The RD890 has a total of 42 PCI Express® lanes: 10 lanes are dedicated for external PCIe devices, and the rest support 2 x16 PCIe links or 4 x8 PCIe links for the ultimate graphics setup. With support for a four-lane A-Link Express III interface to AMD’s Southbridges such as the SB800, the RD890 guarantees separate bandwidth for peripherals, graphics, and General Purpose Graphics Processor Unit (GPGPU). The RD890 also comes equipped with the new HyperTransport™ 3 and PCIe Gen 2 technologies, with the ability for high system overclocking to deliver leadership performance. All of these are achieved by a highly integrated, thermally efficient design in a 29mm x 29mm package. The RD890 also supports a revision 1.26 compliant IOMMU (Input/Output Memory Management Unit) implementation for address translation and protection services. This feature allows virtual addresses from PCI Express endpoint devices to be translated to physical memory addresses. On-chip caching of address translations is provided to improve I/O performance. The device is also compliant with revision 1.0 of the PCI Express Address Translation Services (ATS) specification to enable ATS-compliant endpoint devices to cache address translation. These features enhance memory protection and support hardware-based I/O virtualization when combined with appropriate operating system or hypervisor software. Combined with AMD Virtualization™ (AMD-V™) technology, these features are designed to provide comprehensive platform level virtualization support. 1.2 RD890 Features 1.2.1 CPU Interface 1.2.2 • • • • Supports 16-bit up/down HyperTransport™ (HT) 3.0 interface up to 5.2 GT/s. • • • Supports AMD Phenom™ and later desktop processors. Supports 1200, 1400, 1600, 1800, 2000, 2200, 2400, and 2600 MHz HT3 frequencies. Supports “Shanghai” and subsequent series of AMD server/workstation and desktop processors through sockets F, AM3, G34, and C32. Supports LDTSTOP interface and CPU throttling. Supports broadcast memory write to the graphics ports. PCI Express® Interface • • • 1.2.3 Supports 200, 400, 600, 800, and 1000 MHz HT1 frequencies. Supports PCIe Gen 2 (version 2.0). Optimized peer-to-peer and general purpose link performance. Supports 2 x16 graphics links for simultaneous operation of 2 graphics cards. They are also configurable to operate as 4 x8 graphics links. • Supports 10 PCI E Gen 2 general purpose lanes, supporting up to 7 devices on specific ports (possible configurations are described in Section 2.3, “PCI Express®”). • Supports a revision 1.26 compliant IOMMU (Input/Output Memory Management Unit) implementation for address translation and protection services. Please refer to the AMD I/O Virtualization Technology (IOMMU) Specification for more details. A-Link Express III Interface • One x4 A-Link Express III interface for connection to an AMD Southbridge. The A-Link Express III is a proprietary interface developed by AMD based on the PCI Express technology, with additional Northbridge-Southbridge © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 1-1 Software Features messaging functionalities. It supports the PCIe Gen 2 transfer rate of 5 GT/s, and is backward compatible with the A-Link Express II interface. 1.2.4 1.2.5 Power Management Features • • Fully supports ACPI states S1, S3, S4, and S5. • • Supports AMD Cool’n’Quiet™ technology via FID/VID change. • Supports dynamic lane reduction for the PCIe interfaces, adjusting to the task the number of lanes employed. The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture— On, Standby, Suspend, and Off. Each power state can be achieved by software control bits. Clocks are controlled dynamically using a mechanism that is transparent to the software. The ASIC hardware detects idle blocks and turns off the clocks to those blocks in order to reduce power consumption. PC Design Guide Compliance The RD890 complies with all relevant Windows Logo Program (WLP) requirements from Microsoft® for WHQL certification. 1.2.6 Test Capability Features The RD890 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per Million) ratio: • Full scan implementation on the digital core logic which provides about 97% fault coverage through ATPG (Automatic Test Pattern Generation Vectors). • • • • Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules. • • IDDQ mode support to allow chip evaluation through current leakage measurements. A JTAG test mode in order to allow board level testing of neighboring devices. An XOR tree test mode on all the digital I/O's to allow for proper soldering verification at the board level. Access to the analog modules and PLLs in the RD890 in order to allow full evaluation and characterization of these modules. Highly advanced signal observability through the debug port. These test modes can be accessed through the settings of the instruction register of the JTAG circuitry. 1.2.7 Packaging • • 1.3 Flip chip design in a 29mm x 29mm 692-FCBGA package. Software Features • • • • • • 1.4 Single chip solution in 65nm, 1.1V CMOS technology. Supports Microsoft Windows® XP, Windows Vista®, and Windows® 7. Supports corporate manageability requirements such as DMI. ACPI support. Full write combining support for maximum performance. Comprehensive OS and API support. Extensive Power Management support. Device ID The RD890 is a member of the AMD chipset family, which consists of different devices designed to support different platforms. Each device is identified by the device ID, which is stored in the NB_DEVICE_ID register. The device ID for the RD890 is 5A11h. 43403 AMD 890FX Databook 3.00 1-2 © 2012 Advanced Micro Devices, Inc. Proprietary Branding Diagrams 1.5 Branding Diagrams AMD Logo RD890 A21 YYWW ENG MADE IN TAIWAN WXXXXX.WW 215-0716020 AMD Product Type Date Code* Country of Origin Wafer Lot Number Part Number * YY - Assembly Start Year WW - Assembly Start Week Note: Branding can be in laser, ink, or mixed laser-and-ink marking. Figure 1-1 RD890 Branding Diagram for A21 Engineering Sample AMD Logo NORTHBRIDGE YYWW MADE IN TAIWAN WXXXXX.WW 215-0716020 AMD Product Type Date Code* Country of Origin Wafer Lot Number Part Number * YY - Assembly Start Year WW - Assembly Start Week Note: Branding can be in laser, ink, or mixed laser-and-ink marking. Figure 1-2 RD890 Branding Diagram for A21 Production Sample 1.6 Conventions and Notations The following sections explain the conventions used throughout this manual. 1.6.1 Pin Names Pins are identified by their pin names or ball references. All active-low signals are identified by the suffix ‘#’ in their names (e.g., SYSRESET#). 1.6.2 Pin Types The pins are assigned different codes according to their operational characteristics. These codes are listed in Table 1-1. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 1-3 Conventions and Notations Table 1-1 Pin Type Codes Code 1.6.3 Pin Type I Digital Input O Digital Output I/O Bi-Directional Digital Input or Output M Multifunctional Pwr Power Gnd Ground A-O Analog Output A-I Analog Input A-I/O Analog Bi-Directional Input/Output A-Pwr Analog Power A-Gnd Analog Ground Other Pin types not included in any of the categories above Numeric Representation Hexadecimal numbers are appended with “h” whenever there is a risk of ambiguity. Other numbers are in decimal. Pins of identical functions but different trailing digits (e.g., DFT_GPIO0, DFT_GPIO1, ...DFT_GPIO5) are referred to collectively by specifying their digits in square brackets and with colons (i.e., “DFT_GPIO[5:0]”). A similar short-hand notation is used to indicate bit occupation in a register. For example, NB_COMMAND[15:10] refers to the bit positions 10 through 15 of the NB_COMMAND register. 1.6.4 Hyperlinks Phrases or sentences in blue italic font are hyperlinks to other parts of the manual. Users of the PDF version of this manual can click on the links to go directly to the referenced sections, tables, or figures. 1.6.5 Acronyms and Abbreviations The following is a list of the acronyms and abbreviations used in this manual. Table 1-2 Acronyms and Abbreviations Acronym Full Expression ACPI Advanced Configuration and Power Interface ASPM Active State Power Management A-Link-E A-Link Express interface between the Northbridge and Southbridge. BGA Ball Grid Array BIOS Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a system or expansion card. BIST Built In Self Test. DBI Dynamic Bus Inversion DPM Defects per Million EPROM Erasable Programmable Read Only Memory FCBGA Flip Chip Ball Grid Array FIFO First In, First Out VSS Ground GPIO General Purpose Input/Output HT IDDQ IOMMU JTAG HyperTransport™ interface Direct Drain Quiescent Current Input/Output Memory Management Unit Joint Test Access Group. An IEEE standard. 43403 AMD 890FX Databook 3.00 1-4 © 2012 Advanced Micro Devices, Inc. Proprietary Conventions and Notations Table 1-2 Acronyms and Abbreviations (Continued) Acronym Full Expression MB Mega Byte NB Northbridge PCI PCIe ® Peripheral Component Interface PCI Express® PLL Phase Locked Loop POST Power On Self Test PD Pull-down Resistor PU Pull-up Resistor RAS Reliability, Availability and Serviceability SB Southbridge TBA To Be Added VRM Voltage Regulation Module © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 1-5 Conventions and Notations This page is left blank intentionally. 43403 AMD 890FX Databook 3.00 1-6 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 2 Functional Descriptions This chapter describes the functional operation of the major interfaces of the RD890 system logic chip. Figure 2-1 illustrates the RD890 internal blocks and interfaces. CPU Interface CPU PCIe® GFX Interface (1 x 16 or 2 x 8 Lanes) PCIe GFX2 Interface A-Link-E Interface PCIe GPP Interface (6 Lanes for 6 ports, plus 4 Lanes for 1 port) Expansion Slots (1 x 4 Lanes) Southbridge Root Complex IO Controller (1 x 16 or 2 x 8 Lanes) Graphics Controllers IOMMU Graphics Controllers HyperTransport™ 3 Unit Register Interface Figure 2-1 RD890 Internal Blocks and Interfaces 2.1 HyperTransport™ Interface 2.1.1 Overview The RD890 is optimized to interface with the AMD Phenom™ and later desktop processors. The supports HyperTransport™ 3 (HT3), as well as HyperTransport 1 (HT1) for backward compatibility and for initial boot-up. For a detailed description of the interface, please refer to the HyperTransport I/O Link Specification from the HyperTransport Consortium. Figure 2-2, “HyperTransport™ Interface Block Diagram,” illustrates the basic blocks of the host bus interface of the RD890. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 2-1 HyperTransport™ Interface 10.4 GB/s to CPU 10.4 GB/s from CPU Tx PHY Rx PHY Tx PHY Interface Rx PHY Interface Protocol Transmitter Protocol Receiver Response Interface Upstream Arbitration Host Interface Host read responses DMA requests IOMMU requests DMA read response data Host requests Host read responses IOMMU L2 PCIe® Cores I/O Controller Figure 2-2 HyperTransport™ Interface Block Diagram The RD890 HyperTransport bus interface consists of 16 unidirectional differential Command/Address/Data pins, and 2 differential Control pins and 2 differential Clock pins in both the upstream and downstream directions. On power up, the link is 8-bit wide and runs at a default speed of 400MT/s in HyperTransport 1 mode. After negotiation, carried out by the HW and SW together, the link width can be brought up to the full 16-bit width and the interface can run up to 5.2GT/s in HyperTransport 3 mode. In HyperTransport 1 mode, the interface operates by clock-forwarding while in HyperTransport 3 mode, the interface operates by dynamic phase recovery, with frequency information propagated over the clock pins. The interface is illustrated below in Figure 2-3, “RD890 HyperTransport™ Interface Signals.” The signal name and direction for each signal is shown with respect to the RD890. Detailed descriptions of the signals are given in Section 3.3, “CPU HyperTransport™ Interface‚’ on page 3-4. 43403 AMD 890FX Databook 3.00 2-2 © 2012 Advanced Micro Devices, Inc. Proprietary HyperTransport™ Interface HT_TXCALN HT_TXCALP HT_RXCALP 2 HT_TXCLKN 2 HT_TXCTLP 2 HT_TXCTLN 2 HT_TXCADP 16 HT_TXCADN 16 HT_RXCLKP 2 HT_RXCLKN 2 HT_RXCTLP 2 HT_RXCTLN 2 HT_RXCADP 16 HT_RXCADN 16 CPU RD890 HT_RXCALN HT_TXCLKP Figure 2-3 RD890 HyperTransport™ Interface Signals The RD890 HyperTransport interface has the following features: 2.1.2 • • • • • • HyperTransport 3.0 compliant • • • Link disconnection with tristate, LS0, LS1, LS2, and LS3 low-power modes 16-bit and 8-bit link widths supported. Width for each direction of the link is independently controlled. 400MT/s to 5.2GT/s link speeds in increments of 400MT/s (up to 2GT/s only for HyperTransport 1 mode) DC-coupled HyperTransport mode only UnitID clumping for x16 PCI Express® ports Isochronous flow-control mode for Southbridge audio and IOMMU 64-bit address extension support (52-bit physical addressing) Error retry in HyperTransport 3 mode Full HyperTransport-defined BIST support for both internal and external loopback modes HyperTransport™ Flow Control Buffers The RD890 HTIU implements the following flow control buffers in its receiver: Table 2-1 RD890 HyperTransport™ Flow Control Buffers Flow Control Buffer Type Posted Non-Posted Cmd 16 16 Data 16 1 Advertise 63 credits. ISOC Cmd 0 0 Advertise 63 credits. ISOC Data 0 0 Advertise 63 credits. © 2012 Advanced Micro Devices, Inc. Proprietary Response Advertise 63 credits. 43403 AMD 890FX Databook 3.00 2-3 IOMMU 2.2 IOMMU The RD890’s IOMMU (Input/Output Memory Management Unit) block provides address translation and protection services as described in version 1.26 of the AMD I/O Virtualization Technology (IOMMU) Specification. The RD890 also supports the PCI Express Address Translation Services 1.0 Specification, which allows the supporting of endpoint devices to request and cache address translations. When DMA requests containing virtual addresses are received, the IOMMU looks up the page translation tables located in the system memory in order to convert the virtual addresses into physical addresses and to verify access privileges. On-chip caching is provided in order to speed up translation and reduce or eliminate the number of system memory accesses required. Every PCIe core contains a local translation cache, and the RD890 also contains a shared global translation cache. The RD890 supports up to 216 domains, each of which can utilize a separate 64-bit virtual address space. It supports a 52-bit physical address space. 43403 AMD 890FX Databook 3.00 2-4 © 2012 Advanced Micro Devices, Inc. Proprietary PCI Express® 2.3 PCI Express® 2.3.1 PCIe® Ports In total, there are 12 PCIe® ports on the RD890, divided into 5 groups and implemented in hardware as 5 separate cores: • PCIE-GFX: 2 graphics ports, 16 lanes in total. Width of each port is x8. In the default configuration, the 2 ports are combined to provide a 1 x16 port. • PCIE-GFX2: 2 graphics ports, 16 lanes in total. Width of each port is x8. In the default configuration, the 2 ports are combined to provide a 1 x16 port. • PCIE-GPPa: 6 general purpose ports, with 6 lanes in total. They support 6 different configurations with respect to link widths: 4:2, 4:1:1, 2:2:2, 2:2:1:1, 2:1:1:1:1, and 1:1:1:1:1:1 (default configuration). See Table 2-2, “Possible Configurations for the PCI Express® General Purpose Links‚’ on page 2-5 and Table 3-12, “Strap Definition for STRAP_PCIE_GPP_CFG‚’ on page 3-10. • PCIE-GPPb: 1 general purpose port, with 4 lanes in total. Width of the port is x4. Table 2-2 Possible Configurations for the PCI Express® General Purpose Links PCIe® Core Physical Lane Config. B Config. C Config. C2 Config. E Config. K x2 x2 GPP0 GPP1 GPPa GPP2 x4 x4 x2 GPP3 GPP4 GPP5 x2 x1 x1 x2 x2 x1 x2 x1 Config. L x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x4 x4 x4 GPP6 GPPb GPP7 GPP8 x4 x4 x4 GPP9 • PCIE-SB: The Southbridge port provides a dedicated x4 link to the Southbridge (also referred to as the “A-Link Express III interface”). Each port supports the following PCIe functions: • • • • • • PCIe Gen 1 and Gen 2 link speeds ASPM L0s and L1 states ACPI power management Endpoint and root complex initiated dynamic link degradation Lane reversal Alternative Routing-ID Interpretation (ARI) The PCIE-GFX and PCIE-GFX2 ports also support the ATI CrossFire™ technology. 2.3.2 PCIe® Reset Signals Reset signals to PCIe slots, as well as embedded PCIe devices, must be controlled through one or more software-controllable GPIO pins instead of the global system reset. It is recommended that unique GPIO pins be used for each slot or device. The RD890 has four GPIO pins that may be used for the purpose of driving reset signals (PCIE_GPIO_RESET[5:4] and PCIE_GPIO_RESET[2:1]). Additional reset GPIO pins may be driven by platform-specific means such as a super I/O or an I/O expander. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 2-5 External Clock Chip 2.4 External Clock Chip On the RD890 platform, an external clock chip provides the CPU, PCI Express, and A-Link Express III reference clocks. For requirements on the clock chip, please refer to the 700 and 800 Series IGP Express AMD Platform External Clock Generator Requirements Specification for Client Platforms. 43403 AMD 890FX Databook 3.00 2-6 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 3 Pin Descriptions and Strap Options This chapter gives the pin descriptions and the strap options for the RD890. To jump to a topic of interest, use the following list of hyperlinked cross references: “Pin Assignment Top View” on page 3-2 “RD890 Interface Block Diagram” on page 3-4 “CPU HyperTransport™ Interface” on page 3-4 “PCI Express® Interfaces” on page 3-5: “Interface for External Graphics Controllers” on page 3-5 “Interface for General Purpose External Devices” on page 3-5 “A-Link Express III Interface to Southbridge” on page 3-6 “Miscellaneous PCI Express® Signals” on page 3-6 “Clock Interface” on page 3-6 “Power Management Pins” on page 3-7 “Miscellaneous Pins” on page 3-7 “Power Pins” on page 3-7 “Ground Pins” on page 3-9 “Strapping Options” on page 3-10 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 3-1 Pin Assignment Top View 3.1 Pin Assignment Top View 1 2 4 5 6 7 8 9 10 11 12 13 14 VDDA18P CIE VSS VDDPCIE GFX_TX6 P VSS GFX_TX5 P VSS GFX_TX3 P VSS GFX_TX1 P VSS VDDA18P CIE VDDPCIE VSS GFX_TX6 N GFX_RX6 P GFX_TX5 N GFX_TX4 P GFX_TX3 N GFX_TX2 P GFX_TX1 N GFX_TX0 P VDDA18P CIE VDDA18P CIE VSS VSS A B 3 C VDDPCIE VSS VDDPCIE VSS GFX_RX6 N VSS GFX_TX4 N VSS GFX_TX2 N VSS GFX_TX0 N VDDA18P CIE VDDA18P CIE D GFX_RX7 N GFX_RX7 P VSS VDDPCIE VSS GFX_RX5 P VSS GFX_RX3 P VSS GFX_RX1 P VSS VDDA18P CIE VDDA18P CIE VSS E VSS GFX_TX7 N GFX_TX7 P VSS VDDPCIE GFX_RX5 N GFX_RX4 P GFX_RX3 N GFX_RX2 P GFX_RX1 N GFX_RX0 P VDDA18P CIE VDDA18P CIE PCE_TCA LRN F GFX_TX8 N GFX_TX8 P VSS GFX_RX8 N GFX_RX8 P VDDPCIE GFX_RX4 N VSS GFX_RX2 N VSS GFX_RX0 N VDDA18P CIE VDDA18P CIE PCE_TCA LRP G VSS GFX_TX9 N GFX_TX9 P VSS GFX_RX9 N GFX_RX9 P VDDPCIE VDDPCIE VSS VDDPCIE VSS VDDA18P CIE VDDA18P CIE VDDA18P CIE H GFX_TX10 N GFX_TX10 P VSS GFX_RX1 0N GFX_RX1 0P VSS VDDPCIE GFX_REF CLKN VDDPCIE VSS VDDPCIE VDDA18P CIE VDDA18P CIE VDDA18P CIE J VSS GFX_TX11 N GFX_TX11 P VSS GFX_RX11 N GFX_RX11 P VSS GFX_REF CLKP K GFX_TX12 N GFX_TX12 P VSS GFX_RX1 2N GFX_RX1 2P VSS VDDPCIE VSS L VSS GFX_TX13 N GFX_TX13 P VSS GFX_RX1 3N GFX_RX1 3P VSS VDDPCIE VDDA18P CIE VSS VSS VDDC M GFX_TX14 N GFX_TX14 P VSS GFX_RX1 4N GFX_RX1 4P VSS VDDPCIE VSS VSS VSS VDDC VSS N VSS GFX_TX15 N GFX_TX15 P VSS GFX_RX1 5N GFX_RX1 5P VSS VDDPCIE VSS VDDC VSS VDDC P GFX2_TX0 N GFX2_TX0 P VSS GFX2_RX 0N GFX2_RX 0P VSS VDDPCIE VSS VSS VSS VDDC VSS R VSS GFX2_TX1 N GFX2_TX1 P VSS GFX2_RX 1N GFX2_RX 1P VSS VDDPCIE VSS VDDC VSS VDDC T GFX2_TX2 N GFX2_TX2 P VSS GFX2_RX 2N GFX2_RX 2P VSS VDDPCIE VSS VSS VSS VDDC VSS U VSS GFX2_TX3 N GFX2_TX3 P VSS GFX2_RX 3N GFX2_RX 3P VSS GFX2_RE FCLKN VSS VSS VSS VDDC V GFX2_TX4 N GFX2_TX4 P VSS GFX2_RX 4N GFX2_RX 4P VSS VDDPCIE GFX2_RE FCLKP VDDA18P CIE VSS VSS VSS W VSS GFX2_TX5 N GFX2_TX5 P VSS GFX2_RX 5N GFX2_RX 5P VSS VDDPCIE Y GFX2_TX6 N GFX2_TX6 P VSS GFX2_RX 6N GFX2_RX 6P VSS VDDPCIE VSS AA VSS GFX2_TX7 N GFX2_TX7 P VSS GFX2_RX 7N GFX2_RX 7P VSS VDDPCIE VSS VDDPCIE VSS GPP_REF CLKN AB GFX2_TX8 N GFX2_TX8 P VSS GFX2_RX 8N GFX2_RX 8P VSS VDDPCIE VSS AC VSS GFX2_TX9 N GFX2_TX9 P VSS VSS VDDPCIE GFX2_RX 13P AD GFX2_RX 9N GFX2_RX 9P VSS VSS VDDPCIE GFX2_RX 12P AE VSS GFX2_TX1 0N GFX2_TX1 0P VDDPCIE VSS AF GFX2_RX 10N GFX2_RX 10P VDDPCIE VSS GFX2_RX 11P VDDPCIE VSS GFX2_TX1 1P GFX2_RX 11N VSS GFX2_TX1 1N 3 4 AG AH 1 2 VSS VDDPCIE VSS VDDPCIE VSS VDDPCIE VSS VDDPCIE VSS GFX2_RX 15P VSS GPP_RX9 N VSS GPP_RX7 N VSS GFX2_RX 13N GFX2_RX 14P GFX2_RX 15N PCE_RCA LRN GPP_RX9 P GPP_RX8 N GPP_RX7 P GPP_RX6 N GFX2_RX 12N VSS GFX2_RX 14N VSS PCE_RCA LRP VSS GPP_RX8 P VSS GPP_RX6 P VSS GFX2_TX1 3P VSS GFX2_TX1 5P VSS GPP_TX8 N VSS GPP_TX6 N VSS GFX2_TX1 2P GFX2_TX1 3N GFX2_TX1 4P GFX2_TX1 5N GPP_TX9 N GPP_TX8 P GPP_TX7 N GPP_TX6 P GPP_TX5 N VSS GFX2_TX1 2N VSS GFX2_TX1 4N VSS GPP_TX9 P VSS GPP_TX7 P VSS GPP_TX5 P 5 6 7 8 9 10 11 12 13 14 CPU Interface A-Link Express III Interface Clock Interface PCIe® External Graphics 0 Interface PCIe External Graphics 2 Interface PCIe General Purpose Interface Power Management Interface Core Power PCIe Main I/O Power PCIe 1.8V I/O Power and PLL Power GPIO 1.8V I/O Power HyperTransport™ Interface Power Grounds Other 43403 AMD 890FX Databook 3.00 3-2 © 2012 Advanced Micro Devices, Inc. Proprietary Pin Assignment Top View 15 16 17 18 19 20 21 22 23 24 25 26 PWM_GPI O4 VSS POWERG OOD VDD18 TESTMOD E VSS DBG_GPI O3 VSS DFT_GPIO 5 VSS DFT_GPIO 1 VSS 27 28 PWM_GPI O2 PWM_GPI O6 OSCIN VDD18 PCIE_RES ET_GPIO1 I2C_CLK DBG_GPI O2 DBG_GPI O1 DFT_GPIO 4 DFT_GPIO 2 DFT_GPIO 3 DFT_GPIO 0 VSS VSS PWM_GPI O5 VSS VDD18 VSS I2C_DATA VSS DBG_GPI O0 VSS VDDHTTX VDDHTTX VDDHTTX VDDHTTX VDDHTTX C SYSRESE T# VSS PCIE_RES ET_GPIO2 VDD18 PCIE_RES ET_GPIO3 VSS ALLOW_L DTSTOP VDDHTTX VDDHTTX HT_RXCA LN HT_RXCA LP VSS HT_TXCA LN HT_TXCA LP D LDTSTOP # PWM_GPI O1 PCIE_RES ET_GPIO5 VDD18 PCIE_RES ET_GPIO4 VSS STRP_DA TA VDDHTTX HT_TXCA D8P HT_TXCA D8N VSS HT_TXCA D0P HT_TXCA D0N VSS E VSS PWM_GPI O3 VSS VSS VSS VSS VSS VDDHTTX VSS HT_TXCA D9P HT_TXCA D9N VSS HT_TXCA D1P HT_TXCA D1N F HT_TXCA D10N HT_TXCA D2N A B VSS VSS VSS VSS VSS VSS VDDA18H TPLL VDDHTTX HT_TXCA D10P VSS HT_TXCA D2P VSS G VSS VSS VSS VSS VSS VSS VSS VDDHTTX VSS HT_TXCA D11P HT_TXCA D11N VSS HT_TXCA D3P HT_TXCA D3N H HT_REFC LKN VSS HT_TXCL K1P HT_TXCL K1N VSS HT_TXCL K0P HT_TXCL K0N VSS J HT_REFC LKP VDDHT VSS HT_TXCA D12P HT_TXCA D12N VSS HT_TXCA D4P HT_TXCA D4N K VDDHT VSS HT_TXCA D13P HT_TXCA D13N VSS HT_TXCA D5P HT_TXCA D5N VSS L HT_TXCA D14N HT_TXCA D6N M N VSS VDDC VSS VSS VDDC VSS VSS VSS VSS VDDHT VSS HT_TXCA D14P VSS HT_TXCA D6P VSS VDDC VSS VSS VDDHT VSS HT_TXCA D15P HT_TXCA D15N VSS HT_TXCA D7P HT_TXCA D7N VSS VDDC VSS VDDC VSS VSS VDDHT VSS HT_TXCTL 1P HT_TXCTL 1N VSS HT_TXCTL 0P HT_TXCTL 0N P VSS VDDC VSS VSS VDDHT VSS HT_RXCT L1N HT_RXCT L1P VSS HT_RXCT L0N HT_RXCT L0P VSS R VDDC VSS VDDC VSS VSS VDDHT VSS HT_RXCA D15N HT_RXCA D15P VSS HT_RXCA D7N HT_RXCA D7P T VSS VDDC VSS VSS VDDHT VSS HT_RXCA D14N HT_RXCA D14P VSS HT_RXCA D6N HT_RXCA D6P VSS U VSS VSS VSS VDDA18P CIE VSS VDDHT VSS HT_RXCA D13N HT_RXCA D13P VSS HT_RXCA D5N HT_RXCA D5P V VDDHT VSS HT_RXCA D12N HT_RXCA D12P VSS HT_RXCA D4N HT_RXCA D4P VSS W THERMAL DIODE_P VDDHT VSS HT_RXCL K1N HT_RXCL K1P VSS HT_RXCL K0N HT_RXCL K0P Y HT_RXCA D11N HT_RXCA D11P VSS HT_RXCA D3N HT_RXCA D3P VSS AA GPP_REF CLKP VDDPCIE VDDPCIE VSS VDDPCIE VSS VSS THERMAL DIODE_N VDDHT VSS VSS VDDHT VSS HT_RXCA D10N HT_RXCA D10P VSS HT_RXCA D2N HT_RXCA D2P AB HT_RXCA D9P HT_RXCA D1P VSS VDDPCIE VSS VDDPCIE GPP_RX5 N VSS GPP_RX3 N VSS GPP_RX1 N VSS SB_RX3P VDDHT HT_RXCA D9N VSS HT_RXCA D1N VSS AC GPP_RX5 P GPP_RX4 N GPP_RX3 P GPP_RX2 N GPP_RX1 P PCE_BCA LRN SB_RX3N SB_RX2P VDDHT HT_RXCA D8N HT_RXCA D8P VSS HT_RXCA D0N HT_RXCA D0P AD VSS GPP_RX4 P VSS GPP_RX2 P VSS PCE_BCA LRP VSS SB_RX2N VSS VDDHT VDDHT VDDHT VDDHT VDDHT AE GPP_TX4 N VSS GPP_TX2 N VSS GPP_TX0 N VSS SB_TX2P VSS SB_TX1P VSS SB_RX1P VSS VDDHT VSS GPP_TX4 P GPP_TX3 N GPP_TX2 P GPP_TX1 N GPP_TX0 P GPP_RX0 N SB_TX2N SB_TX3P SB_TX1N SB_TX0P SB_RX1N SB_RX0P VSS VSS GPP_TX3 P VSS GPP_TX1 P VSS GPP_RX0 P VSS SB_TX3N VSS SB_TX0N VSS SB_RX0N 15 16 17 18 19 20 21 22 23 24 25 26 AF AG AH 27 28 CPU Interface A-Link Express III Interface Clock Interface PCIe External Graphics 0 Interface PCIe External Graphics 2 Interface PCIe General Purpose Interface Power Management Interface Core Power PCIe Main I/O Power PCIe 1.8V I/O Power and PLL Power GPIO 1.8V I/O Power HyperTransport Interface Power Grounds Other © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 3-3 RD890 Interface Block Diagram 3.2 RD890 Interface Block Diagram Figure 3-1 shows the different interfaces on the RD890. Interface names in blue are hyperlinks to the corresponding sections in this chapter. PCIe® Graphics Interface HT_RXCAD[15:0]P, HT_RXCAD[15:0]N HT_RXCLK[1:0]P, HT_RXCLK[1:0]N HT_RXCTL[1:0]P, HT_RXCTL[1:0]N HT_TXCAD[15:0]P, HT_TXCAD[15:0]N HT_TXCLK[1:0]P, HT_TXCLK[1:0]N HT_TXCTL[1:0]P, HT_TXCTL[1:0]N HT_RXCALP, HT_RXCALN HT_TXCALP, HT_TXCALN HyperTransport™ Interface A-Link Express III Interface SB_TX[3:0]P, SB_TX[3:0]N SB_RX[3:0]P, SB_RX[3:0]N Power Management Interface SYSRESET# POWERGOOD LDTSTOP# ALLOW_LDTSTOP PWM_GPIO[6:1] PCIe Interface for General Purpose External Devices Misc. PCIe Signals Clock Interface DBG_GPIO[3:0] I2C_CLK I2C_DATA STRP_DATA DFT_GPIO[5:0] TESTMODE THERMALDIODE_P THERMALDIODE_N GFX_TX[15:0]P, GFX_TX[15:0]N GFX_RX[15:0]P, GFX_RX[15:0]N GFX2_TX[15:0]P, GFX2_TX[15:0]N GFX2_RX[15:0]P, GFX2_RX[15:0]N GPP_TX[9:0]P, GPP_TX[9:0]N GPP_RX[9:0]P, GPP_RX[9:0]N PCE_BCALRP, PCE_BCALRN PCE_RCALRP, PCE_RCALRN PCE_TCALRP, PCE_TCALRN PCIE_RESET_GPIO[5:1] OSCIN HT_REFCLKP, HT_REFCLKN GPP_REFCLKP, GPP_REFCLKN GFX_REFCLKP, GFX_REFCLKN GFX2_REFCLKP, GFX2_REFCLKN Misc. Signals Power VDDHT Grounds VSS VDD18 VDDPCIE VDDA18PCIE VDDC VDDHTTX VDDA18HTPLL Figure 3-1 RD890 Interface Block Diagram 3.3 CPU HyperTransport™ Interface Table 3-1 HyperTransport™ Interface Pin Name Type Power Domain Ground Domain Functional Description HT_RXCAD[15:0]P, HT_RXCAD[15:0]N I VDDHT VSS Receiver Command, Address, and Data Differential Pairs HT_RXCLK[1:0]P, HT_RXCLK[1:0]N I VDDHT VSS Receiver Clock Signal Differential Pair. Forwarded clock signal. Each byte of RXCAD uses a separate clock signal. Data is transferred on each clock edge. HT_RXCTL[1:0]P, HT_RXCTL[1:0]N I VDDHT VSS Receiver Control Differential Pair. The pair is for distinguishing control packets from data packets. Each byte of RXCAD uses a separate control signal. HT_TXCAD[15:0]P, HT_TXCAD[15:0]N O VDDHT VSS Transmitter Command, Address, and Data Differential Pairs 43403 AMD 890FX Databook 3.00 3-4 © 2012 Advanced Micro Devices, Inc. Proprietary PCI Express® Interfaces Table 3-1 HyperTransport™ Interface Pin Name 3.4.1 Power Domain Ground Domain Functional Description HT_TXCLK[1:0]P, HT_TXCLK[1:0]N O VDDHT VSS Transmitter Clock Signal Differential Pair. Forwarded clock signal. Each byte of TXCAD uses a separate clock signal. Data is transferred on each clock edge. HT_TXCTL[1:0]P, HT_TXCTL[1:0]N O VDDHT VSS Transmitter Control Differential Pair. The pair is for distinguishing control packets from data packets. Each byte of TXCAD uses a separate control signal. Other VDDHT VSS Receiver Calibration Resistor to HT_RXCALP HT_RXCALN 3.4 Type (Continued) HT_RXCALP Other VDDHT VSS Receiver Calibration Resistor to HT_RXCALN HT_TXCALP Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALN HT_TXCALN Other VDDHT VSS Transmitter Calibration Resistor to HTTX_CALP PCI Express® Interfaces Interface for External Graphics Controllers Table 3-2 2 x 16 or 4 x 8 PCI Express® Interface for External Graphics Type Power Domain Ground Domain GFX_TX[15:0]P, GFX_TX[15:0]N O VDDA18PCIE VSSA_PCIE 50 between complements External Graphics 0 Transmit Data Differential Pairs. Connect to connector[s] for external graphics card[s] on the motherboard. GFX_RX[15:0]P, GFX_RX[15:0]N I VDDA18PCIE VSSA_PCIE 50 between complements External Graphics 0 Receive Data Differential Pairs. Connect to connector[s] for external graphics card[s] on the motherboard. GFX2_TX[15:0]P, GFX2_TX[15:0]N O VDDA18PCIE VSSA_PCIE 50 between complements External Graphics 2 Transmit Data Differential Pairs. Connect to connector[s] for external graphics card[s] on the motherboard. GFX2_RX[15:0]P, GFX2_RX[15:0]N I VDDA18PCIE VSSA_PCIE 50 between complements External Graphics 2 Receive Data Differential Pairs. Connect to connector[s] for external graphics card[s] on the motherboard. Pin Name 3.4.2 Integrated Termination Functional Description Interface for General Purpose External Devices Table 3-3 PCI Express® Interface for General Purpose External Devices Pin Name GPP_TX[9:0]P, GPP_TX[9:0]N GPP_RX[9:0]P, GPP_RX[9:0]N Power Domain Type O I VDDA18PCIE VDDA18PCIE © 2012 Advanced Micro Devices, Inc. Proprietary Ground Domain Integrated Termination Functional Description VSSA_PCIE General Purpose Transmit Data Differential Pair for 50 between general purpose external devices. Connect to an complements external connector on the motherboard for ExpressCard support. VSSA_PCIE General Purpose Receive Data Differential Pair for 50 between general purpose external devices. Connect to an complements external connector on the motherboard for ExpressCard support. 43403 AMD 890FX Databook 3.00 3-5 Clock Interface 3.4.3 A-Link Express III Interface to Southbridge Table 3-4 1 x 4 Lane A-Link Express III Interface for Southbridge 3.4.4 Pin Name Type Power Domain Ground Domain Integrated Termination Functional Description SB_TX[3:0]P, SB_TX[3:0]N O VDDA18PCIE VSSA_PCIE Southbridge Transmit Data Differential Pairs. Connect to the 50 between corresponding Receive Data Differential Pairs on the complements Southbridge. SB_RX[3:0]P, SB_RX[3:0]N I VDDA18PCIE VSSA_PCIE Southbridge Receive Data Differential Pairs. Connect to the 50 between corresponding Transmit Data Differential Pairs on the complements Southbridge. Miscellaneous PCI Express® Signals Table 3-5 Miscellaneous PCI Express® Signals Type Power Domain Ground Domain PCE_BCALRN I VDDA18PCIE VSSA_PCIE N Channel Driver Compensation Calibration for Rx and Tx Channels on Bottom Side. PCE_BCALRP I VDDA18PCIE VSSA_PCIE P Channel Driver Compensation Calibration for Rx and Tx Channels on Bottom Side PCE_TCALRN I VDDA18PCIE VSSA_PCIE N Channel Driver Compensation Calibration for Rx and Tx Channels on Top Side. PCE_TCALRP I VDDA18PCIE VSSA_PCIE P Channel Driver Compensation Calibration for Rx and Tx Channels on Top Side PCE_RCALRN I VDDA18PCIE VSSA_PCIE N Channel Driver Compensation Calibration for Rx and Tx Channels on Right Side. PCE_RCALRP I VDDA18PCIE VSSA_PCIE P Channel Driver Compensation Calibration for Rx and Tx Channels on Right Side I/O VDDA18PCIE VSS Pin Name PCIE_RESET_GP IO[5:1] 3.5 Functional Description PCIe Resets. Except for PCIE_RESET_GPIO3, they can also be used as GPIOs. There are internal pull-downs of 1.7 k on these pins. Clock Interface Table 3-6 Clock Interface Type Power Domain Ground Domain HT_REFCLKP, HT_REFCLKN I VDDA18HTPLL VSSA_HT Disabled GFX_REFCLKP, GFX_REFCLKN I VDDA18PCIE VSSA_PCIE – External Graphics 0 Clock Differential Pair. The pair is connected to an external clock generator on the motherboard when external graphics controller 0 is used. GFX2_REFCLKP, GFX2_REFCLKN I VDDA18PCIE VSSA_PCIE – External Graphics 2 Clock Differential Pair. The pair is connected to an external clock generator on the motherboard when external graphics controller 2 is used. General Purpose Differential Pair. The pair has to be connected to an external clock generator on the motherboard whether the General Purpose link is used or not. Pin Name Integrated Termination Functional Description GPP_REFCLKP, GPP_REFCLKN I VDDA18PCIE VSSA_PCIE – OSCIN I VDD18 VSS Disabled 43403 AMD 890FX Databook 3.00 3-6 HyperTransport™ 100 MHz Clock Differential Pair from external clock source 14.318MHz Reference clock input from the external clock chip (1.8 volt signaling) © 2012 Advanced Micro Devices, Inc. Proprietary Power Management Pins 3.6 Power Management Pins Table 3-7 Power Management Pins Pin Name ALLOW_LDTSTOP Type Power Domain OD VDD18 VSS Allow LDTSTOP. This signal is used by the RD890 to communicate with the Southbridge and tell it when it can assert the LDTSTOP# signal. 1 = LDTSTOP# can be asserted 0 = LDTSTOP# has to be de-asserted I VDD18 VSS HyperTransport™ Stop. This signal is generated by the Southbridge and is used to determine when the HyperTransport link should be disconnected and go into a low-power state. It is a single-ended signal. LDTSTOP# POWERGOOD I PWM_GPIO[6:1] VSS Input from the motherboard signifying that the power to the RD890 is up and ready. Signal High means all power planes are valid. It is not observed internally until it has been high for more than 6 consecutive REFCLK cycles. The rising edge of this signal is deglitched. I/O VDD18 VSS PWM generators. PWM_GPIO6 and PWM_GPIO[4:3] are also parts of the test interface (see section 7.2, “Test Interface,” on page 7- 1). PWM_GPIO[4:2] are also used as strap pins (see section 3.10, “Strapping Options,” on page 3- 10), and the internal pull-ups on them are automatically disabled when they are used for PWM functionality. Can also be used as GPIOs. I VDD18 VSS Global Hardware Reset. This signal comes from the Southbridge. SYSRESET# 3.7 VDD18 Ground Domain Functional Description Miscellaneous Pins Table 3-8 Miscellaneous Pins Pin Name 3.8 Type Power Ground Integrated Domain Domain Termination Functional Description I2C_CLK I/O VDD18 VSS – I2C interface clock signal. Can also be used as GPIO. I2C_DATA I/O VDD18 VSS – I2C interface data signal. Can also be used as GPIO. STRP_DATA I/O VDD18 VSS – I2C interface data signal for external EEPROM based strap loading. See the RD890 Strap Document for details on the operation. TESTMODE I VDD18 VSS – When High, puts the RD890 in test mode and disables the RD890 from operating normally. DFT_GPIO[5:0] I/O VDD18 VSS Pull Up Outputs for DFT TESTMODE. These pins cannot be used for general GPIO functions. DBG_GPIO[3:0] I/O VDD18 VSS Pull Up Outputs for Debug Bus. These pins cannot be used for general GPIO functions. THERMALDIODE_P, THERMALDIODE_N A-O – – – Diode connections to external SM Bus microcontroller for monitoring IC thermal characteristics. Power Pins Table 3-9 Power Pins Pin Name Voltage Pin Count Ball Reference VDDC 1.1V 18 L14, L16, M13, M15, N12, N14, N16, P13, P15, P17, R12, R14, R16, T13, T15, T17, U14, U16 VDD18 1.8V 5 A18, B18, C18, D18, E18 © 2012 Advanced Micro Devices, Inc. Proprietary Comments Core power I/O Power for GPIO pads 43403 AMD 890FX Databook 3.00 3-7 Power Pins Table 3-9 Power Pins Pin Name VDDPCIE VDDA18PCIE (Continued) Voltage 1.1 V 1.8 V Pin Count Ball Reference Comments 39 A3, B2, C1, C3, D4, E5, F6, G8, G10, H7, H9, H11, K7, L8, M7, N8, P7, R8, T7, V7, W8, Y7, AA8, AA10, AA12, PCI Express interface main I/O and PLL power AA16, AA18, AB7, AB9, AB11, AB13, AB15, AB17, AB19, AC6, AD5, AE4, AF3, AG2 21 A12, A1, B12, B13, C12, C13, D12, D13, E12, E13, F12, F13, G12, G13, G14, H12, H13, H14, L11, V11, V18 PCI Express interface 1.8V I/O power HyperTransport™ Interface digital I/O power VDDHT 1.1V 21 AA22, AB22, AC22, K22, AD23, AE24, AE25, AE26, AE27, AE28, AF27, L21, M22, N21, P22, R21, T22, U21, V22, W21, Y22 VDDHTTX 1.2V 11 C24, C25, C26, C27, C28, D22, D23, E22, F22, G22, H22 HyperTransport Transmit Interface I/O power VDDA18HTPLL 1.8V 1 G21 HyperTransport interface 1.8V PLL Power Total Power Pin Count 43403 AMD 890FX Databook 3.00 3-8 116 © 2012 Advanced Micro Devices, Inc. Proprietary Ground Pins 3.9 Ground Pins Table 3-10 Ground Pins Pin Name VSS Pin Count 261 © 2012 Advanced Micro Devices, Inc. Proprietary Ball Reference Comments A11, A14, A16, A20, A22, A24, A26, A5, A7, A9, AA1, AA11, AA13, AA17, AA19, AA20, AA25, AA28, AA4, AA7, AA9, AB10, AB12, AB14, AB16, AB18, AB20, AB21, AB23, AB26, AB3, AB6, AB8, AC1, AC10, AC12, AC14, AC16, AC18, AC20, AC25, AC28, AC4, AC5, AC8, AD26, AD3, AD4, AE1, AE11, AE13, AE15, AE17, AE19, AE21, AE23, AE5, AE7, AE9, AF10, AF12, AF14, AF16, AF18, AF20, AF22, AF24, AF26, AF28, AF4, AF6, AF8, AG27, AG3, AH11, AH13, AH15, AH17, AH19, AH21, AH23, AH25, AH3, AH5, AH7, AH9, B14, B27, B3, C10, C14, C15, C17, C19, C2, C21, C23, C4, C6, C8, D11, D14, D16, D20, D26, D3, D5, D7, D9, E1, E20, E25, E28, E4, F10, F15, Common Ground F17, F18, F19, F20, F21, F23, F26, F3, F8, G1, G11, G15, G16, G17, G18, G19, G20, G25, G28, G4, G9, H10, H15, H16, H17, H18, H19, H20, H21, H23, H26, H3, H6, J1, J22, J25, J28, J4, J7, K23, K26, K3, K6, K8, L1, L12, L13, L15, L17, L18, L22, L25, L28, L4, L7, M11, M12, M14, M16, M17, M18, M21, M23, M26, M3, M6, M8,N1 N11, N13, N15, N17, N18, N22, N25, N28, N4, N7, P11, P12, P14, P16, P18, P21, P23, P26, P3, P6, P8, R1, R11, R13, R15, R17, R18, R22, 25, R28, R4, R7, T11, T12, T14, T16, T18, T21, T23, T26, T3, T6, T8, U1, U11, U12, U13, U15, U17, U18, U22, U25, U28, U4, U7, V12, V13, V14, V15, V16, V17, V21, V23, V26, V3, V6, W1, W22, W25, W28, W4, W7, Y23, Y26, Y3, Y6, Y8 43403 AMD 890FX Databook 3.00 3-9 Strapping Options 3.10 Strapping Options The RD890 provides strapping options to define specific operating parameters. The strap values are latched into internal registers after the assertion of the POWERGOOD signal to the RD890. Table 3-11, “Strap Definitions for the RD890,” shows the definitions of all the strap functions. These straps are set by one of the following four methods: • • • • Allowing the internal pull-up resistors to set all strap values “1”’s automatically. Attaching pull-down resistors to specific strap pins listed in Table 3-11 to set their values to “0”’s. Downloading the strap values from an I2C serial EEPROM (for debug purpose only; contact your AMD FAE representative for details). Setting through an external debug port, if implemented (contact your AMD FAE representative for details). Table 3-11 Strap Definitions for the RD890 Strap Function Strap Pin Description Reserved PWM_GPIO[5:2] Reserved. Make provision for an external pull-down resistor on each of the pins, but do not install a resistor. Reserved DFT_GPIO0 Reserved. Make provision for an external pull-down resistor on this pin, but do not install a resistor. LOAD_ROM_STRAPS# DFT_GPIO1 Selects loading of strap values from EEPROM 0: I2C master can load strap values from EEPROM if connected, or use hardware default values if not connected 1: Use hardware default values (Default) STRAP_PCIE_GPP_CFG DFT_GPIO[4:2] General Purpose Link Configuration. See Table 3-12 below for details. Reserved DFT_GPIO5 Reserved. Make provision for an external pull-down resistor on this pin, but do not install a resistor. Table 3-12 Strap Definition for STRAP_PCIE_GPP_CFG Strap Pin Value Link Width DFT_GPIO4 DFT_GPIO3 DFT_GPIO2 GPP0 GPP1 GPP2 GPP3 GPP4 GPP5 GPP6 GPP7 GPP8 GPP9 Hardware default (Mode L) or EEPROM strap values (Default) 1 1 1 1 1 0 1 0 1 x2 1 0 0 x2 0 1 1 x2 0 1 0 0 0 1 x4 0 0 0 x4 Hardware default (Mode L) or EEPROM strap values x1 x2 x2 x2 x1 x4 Mode C2 x1 x1 x4 K x1 x1 x1 x1 x4 E x1 x1 x1 x1 x4 L (Hardware Default) x1 x4 C x4 B x1 x2 Note: If the pin straps instead of strap values from EEPROM are used, the GPP configuration will then be determined according to this table and cannot be changed after the system has been powered up. 43403 AMD 890FX Databook 3.00 3-10 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 4 Timing Specifications 4.1 HyperTransport™ Bus Timing For HyperTransport™ bus timing information, please refer to specifications by AMD. 4.2 PCI Express® Differential Clock AC Specifications Table 4-1 Timing Requirements for PCIe® Differential Clocks (GFX_REFCLK, GFX2_REFCLK, and GPP_REFCLK at 100MHz) Symbol 4.3 Description Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate TPERIOD AVG Average Clock Period Accuracy TPERIOD ABS Absolute Period (including jitter and spread spectrum modulation) TCCJITTER Cycle to Cycle Jitter Duty Cycle Duty Cycle Rise-Fall Matching Rising edge rate (REFCLK+) to falling edge rate (REFCLK-) matching Minimum Maximum Unit 0.6 4.0 V/ns 0.6 4.0 V/ns -300 +2800 ppm 9.847 10.203 ns - 150 ps 40 60 % - 20 % Minimum Maximum Unit Note - 140 mV 1 HyperTransport™ Reference Clock Timing Parameters Table 4-2 Timing Requirements for HyperTransport™ Reference Clock (100MHz) Symbol VCROSS Parameter Change in Crossing point voltage over all edges F Frequency 99.5 100 MHz 2 ppm Long Term Accuracy -300 +300 ppm 3 SFALL Output falling edge slew rate -10 -0.5 V/ns 4, 5 SRISE Output rising edge slew rate 0.5 10 V/ns 4,5 Tjc max Jitter, cycle to cycle - 150 ps 6 Tj-accumulated Accumulated jitter over a 10 s period -1 1 ns 7 VD(PK-PK) Peak to Peak Differential Voltage 400 2400 mV 8 VD Differential Voltage 200 1200 mV 9 VD Change in VDDC cycle to cycle -75 75 mV 10 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 4-1 OSCIN Reference Clock Timing Parameters Table 4-2 Timing Requirements for HyperTransport™ Reference Clock (100MHz) (Continued) Symbol DC Parameter Minimum Maximum Unit Note 45 55 % 11 Duty Cycle Notes: More details are available in AMD HyperTransport 3.0 Reference Clock Specification and AMD Family 10h Processor Reference Clock Parameters, document # 34864 1 Single-ended measurement at crossing point. Value is maximum-minimum over all time. DC Value of common mode is not important due to blocking cap. 2 Minimum frequency is a consequence of 0.5% down spread spectrum. 3 Measured with spread spectrum turned off. 4 Only simulated at the receive die pad. This parameter is intended to give guidance for simulation. It cannot be tested on a tester but is guaranteed by design. 5 Differential measurement through the range of ±100mV, differential signal must remain monotonic and within slew rate specification when crossing through this region. 6 Tjc max is the maximum difference of tCYCLE between any two adjacent cycles. 7 Accumulated Tjc over a 10s time period, measured with JIT2 TIE at 50ps interval. 8 VD(PK-PK) is the overall magnitude of the differential signal. 9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design that the ring-back will not cross 0V VD. VD(max) is the largest amplitude allowed. 10 The difference in magnitude of two adjacent VDDC measurements. VDDC is the stable post overshoot and ring-back part of the signal. 11 Defined as tHIGH/tCYCLE 4.4 OSCIN Reference Clock Timing Parameters Table 4-3 Timing Requirements for OSCIN Reference Clock (14.3181818MHz) Symbol Parameter Min Typical Max Unit 0.037 – 1.1 s 1 REFCLK Frequency 0.9 – 27 MHz 2 TIH REFCLK High Time 2.0 – – ns TIL REFCLK Low Time 2.0 – – ns TIR REFCLK Rise Time – – 1.5 ns TIF REFCLK Fall Time – – 1.5 ns TIJCC REFCLK Cycle-to-Cycle Jitter Requirement – – 200 ps TIJPP REFCLK Peak-to-Peak Jitter Requirement – – 200 ps TIJLT REFCLK Long Term Jitter Requirement (1s after scope trigger) – – 500 ps TIP REFCLK Period FIP Note 1 Notes: 1 Time intervals measured at 50% threshold point. 2 FIP is the reciprocal of TIP. 4.5 Power Rail Sequence For the purpose of power rail sequencing, the power rails of the RD890 are divided into groupings described in Table 4-4 below. Table 4-4 Power Rail Groupings for the RD890 Voltage ACPI STATE VDDC 1.1V S0-S2 Core power VDDPCIE VDDPCIE 1.1V S0-S2 PCI Express® main IO power VDDHTTX VDDHTTX 1.2V S0-S2 HyperTransport™ transmit interface IO power HT_1.1V VDDHT 1.1V S0-S2 HyperTransport interface digital IO power Group Name Power rail name VDDC 43403 AMD 890FX Databook 3.00 4-2 Description © 2012 Advanced Micro Devices, Inc. Proprietary Power Rail Sequence Table 4-4 Power Rail Groupings for the RD890 Voltage ACPI STATE VDD18 1.8V S0-S2 I/O power for GPIO pads VDDA18PCIE 1.8V S0-S2 PCI Express interface 1.8V IO and PLL power VDDA18HTPLL 1.8V S0-S2 HyperTransport interface 1.8V PLL power Group Name Power rail name 1.8V Description Note: 1. Power rails from the same group are assumed to be generated by the same voltage regulator. 2. Power rails from different groups but at the same voltage can either be generated by separate regulators or by the same regulators as long as they comply with the requirements specified in the RD890 Motherboard Design Guide. 4.5.1 Power Up Figure 4-1 below illustrates the power up sequencing for the various power groups, and Table 4-5 explains the symbols in the figure, as well as the associated requirements. 1.8V T10 VDDHTTX T11 VDDPCIE T12 HT_1.1V T13 VDDC Figure 4-1 RD890 Power Rail Power Up Sequence Table 4-5 RD890 Power Rail Power-up Sequence Symbol Parameter Requirement Comment T10 1.8V rails to VDDHTTX (1.2V) VDDHTTX ramps after 1.8V rails. See Note 1. T11 VDDHTTX (1.2V) to VDDPCIE (1.1V) VDDPCIE ramps together with or after VDDHTTX See Note 1 and 2. T12 VDDHTTX(1.2V) to HT_1.1V rails HT_1.1V rails ramp together with or after VDDHTTX See Note 1 and 2. T13 VDDHTTX(1.2V) to VDDC (1.1V) VDDC ramps together with or after VDDHTTX See Note 1 and 2. Notes: 1. Power rail A ramps after power rail B means that the voltage of rail A does not exceed that of rail B at any time. 2. Power rail A ramps together with power rail B means that the two rails are controlled by the same enable signal and the difference in their ramping rates is only due to the differences in the loadings. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 4-3 Power Rail Sequence 4.5.2 Power Down For power down, the rails should either be turned off simultaneously or in the reversed order of the power up sequence. Variations in speeds of decay due to different capacitor discharge rates can be safely ignored. 43403 AMD 890FX Databook 3.00 4-4 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 5 Electrical Characteristics and Physical Data 5.1 5.1.1 Electrical Characteristics Maximum and Minimum Ratings Table 5-1 Power Rail Maximum and Minimum Voltage Ratings Pin Typical DC Limit* Min. AC Limit* Max. Min. Max. Unit Comments VDDC 1.1 1.067 1.133 1.045 1.155 V Core power VDD18 1.8 1.746 1.854 1.71 1.89 V 1.8V I/O Powers 1.1 1.067 1.133 1.045 1.155 V PCI Express® Interface Main I/O Power 1.8 1.746 1.854 1.71 1.89 V PCI Express interface 1.8V I/O and PLL power 1.1 1.067 1.133 1.045 1.155 V HyperTransport™ Interface digital I/O power 1.2 1.164 1.236 1.14 1.26 V HyperTransport Transmit Interface I/O power 1.8 1.746 1.854 1.71 1.89 V HyperTransport interface 1.8V PLL power VDDPCIE VDDA18PCIE VDDHT VDDHTTX VDDA18HTPLL * Note: The voltage set-point must be contained within the DC specification in order to ensure proper operation. Voltage ripple and transient events outside the DC specification must remain within the AC specification at all times. Transients must return to within the DC specification within 20s. 5.1.2 DC Characteristics Table 5-1 DC Characteristics for PCIe® Differential Clocks (GFX_REFCLK, GFX2_REFCLK, and GPP_REFCLK at 100MHz) Symbol Description Minimum Maximum Unit VIL Differential Input Low Voltage - -150 mV VIH Differential Input High Voltage +150 - mV VCROSS Absolute Crossing Point Voltage +250 +550 mV VCROSS DELTA Variation of VCROSS over all rising clock edges - +140 mV VRB Ring-back Voltage Margin -100 +100 mV VIMAX Absolute Max Input Voltage - +1.15 V VIMIN Absolute Min Input Voltage - -0.15 V Table 5-2 DC Characteristics for 1.8V GPIO Pads Symbol Description VIH-DC Input High Voltage 1.1 - V 1 VIL-DC Input Low Voltage - 0.7 V 1 VOH Minimum Output High Voltage @ I=8mA 1.4 - V 2, 3 VOL Maximum Output Low Voltage @ I=8mA - 0.4 V 2, 3 IOL Minimum Output Low Current @ V=0.1V 2.0 - mA 2, 3 © 2012 Advanced Micro Devices, Inc. Proprietary Minimum Maximum Unit Notes 43403 AMD 890FX Databook 3.00 5-1 RD890 Thermal Characteristics Table 5-2 DC Characteristics for 1.8V GPIO Pads Symbol Description Minimum Maximum IOH Minimum Output High Current @ V=VDDR-0.1V 2.0 - Unit Notes mA 2, 3 Notes: 1) Measured with edge rate of 1us at PAD pin. 2) For detailed current/voltage characteristics please refer to IBIS model. 3) Measurement taken with SP/SN set to default values, PVT=Noml Case Table 5-3 DC Characteristics for the HyperTransport™ 100MHz Differential Clock (HT_REFCLK) 5.2 Symbol Description Minimum Typical VIL Input Low Voltage – 0V VIH Input High Voltage 1.4V VIMAX Maximum Input Voltage – Maximum Comments 0.2V – 1.8V – – – 2.1V – RD890 Thermal Characteristics This section describes some key thermal parameters of the RD890. For a detailed discussion on these parameters and other thermal design descriptions, including package level thermal data and analysis, please consult the Thermal Design and Analysis Guidelines for RD890. 5.2.1 RD890 Thermal Limits Table 5-4 RD890 Thermal Limits Parameter Minimum Nominal Maximum Unit Note Operating Case Temperature 0 — 95 °C 1 Absolute Rated Junction Temperature — — 115 °C 2 Storage Temperature -40 — 60 ° Ambient Temperature 0 — 45 °C 3 Thermal Design Power — 19.6 — W 4 C Notes: 1 - The maximum operating case temperature is the die top-center temperature measured via a thermocouple based on the methodology given in the document Thermal Design and Analysis Guidelines for RD890 (Chapter 12). This is the temperature at which the functionality of the chip is qualified. 2 - The maximum absolute rated junction temperature is the junction temperature at which the device can operate without causing damage to the ASIC. 3 - The ambient temperature is defined as the temperature of the local intake air at the inlet to the thermal management device. The maximum ambient temperature is dependent on the heat sink design, and the value given here is based on AMD’s reference heat sink solution for the RD890. Refer to Chapter 6 in Thermal Design and Analysis Guidelines for RD890 for heatsink and thermal design guidelines. Refer to Chapter 7 for details of ambient conditions. 4 - Thermal Design Power (TDP) is defined as the highest power dissipated while running currently available worst case applications at nominal voltages. The core voltage was raised to 5% above its nominal value for measuring the ASIC power. Since the core power of modern ASICs using 65nm and smaller process technology can vary significantly, parts specifically screened for higher core power were used for TDP measurement. The TDP is intended only as a design reference, and the value given here is preliminary. 5.2.2 Thermal Diode Characteristics The RD890 has an on-die thermal diode, with its positive and negative terminals connected to the THERMALDIODE_P and THERMALDIODE_N pins respectively. Combined with a thermal sensor circuit, the diode temperature, and hence the ASIC junction temperature, can be derived from a differential voltage reading (V). The equation relating the temperature to V is given below. 43403 AMD 890FX Databook 3.00 5-2 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Thermal Characteristics K T ln N V = -------------------------------------------q where: V = Difference of two base-to-emitter voltage readings, one using current = I and the other using current = N x I N = Ratio of the two thermal diode currents (=10 when using an ADI thermal sensor, e.g.: ADM 1020, 1030) = Ideality factor of the diode K = Boltzman’s Constant T = Temperature in Kelvin q = Electron charge The series resistance of the thermal diode (RT) must be taken into account as it introduces an error in the reading (for every 1.0, approximately 0.8oC is added to the reading). The sensor circuit should be calibrated to offset the RT induced, plus any other known fixed errors. Measured values of diode ideality factor and series resistance for the diode circuit are defined in Thermal Design and Analysis Guidelines for RD890. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 5-3 Package Information 5.3 Package Information Figure 5-2 and Table 5-5 describe the physical dimensions of the RD890 package. Figure 5-3 shows the detailed ball arrangement for the RD890. MOD-00094-03 Figure 5-2 RD890 692-Pin FCBGA Package Outline Table 5-5 RD890 692-Pin FCBGA Package Physical Dimensions Ref. Min. (mm) Typical (mm) Max. (mm) c 0.56 0.66 0.76 A 1.87 2.02 2.17 A1 0.40 0.50 0.60 A2 0.81 0.86 0.91 b 0.50 0.60 0.70 D1 28.80 29.00 29.20 D2 - 5.62 - D3 2.00 - - D4 1.00 - - E1 28.80 29.00 29.20 E2 - 7.39 - E3 2.00 - - E4 1.00 - - F1 - 27.00 - F2 - 27.00 - e - 1.00 - 43403 AMD 890FX Databook 3.00 5-4 © 2012 Advanced Micro Devices, Inc. Proprietary Package Information Table 5-5 RD890 692-Pin FCBGA Package Physical Dimensions Ref. Min. (mm) Typical (mm) Max. (mm) ddd - - 0.20 Note: Maximum height of SMT components is 0.650 mm. Figure 5-3 RD890 Ball Arrangement (Bottom View) 5.3.1 Pressure Specification To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling device, follow the recommendations below: • It is recommended that the maximum load that is evenly applied across the contact area between the thermal management device and the die does not exceed 6 lbf. Note that a total load of 4-6 lbf is adequate to secure the thermal management device and achieve the lowest thermal contact resistance with a temperature drop across the thermal interface material of no more than 3°C. Also, the surface flatness of the metal spreader should be 0.001 inch/1 inch. • Pre-test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and the pressure applied around the ASIC package will not exceed 600 micronstrains under any circumstances. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 5-5 Package Information • 5.3.2 Ensure that any distortion (bow or twist) of the board after SMT and cooling device assembly is within industry guidelines (IPC/EIA J-STD-001). For measurement method, refer to the industry approved technique described in the manual IPC-TM-650, section 2.4.22. Board Solder Reflow Process Recommendations 5.3.2.1 Stencil Opening Size for Solderball Pads on PCB Warpage of the PCB and the package may cause solderjoint quality issues at the surface mount. Therefore, it is recommended that the stencil opening sizes be adjusted to compensate for the warpage. The recommendation is for the stencil aperture of the solderballs to be kept at the same size as the pads. 5.3.2.2 Reflow Profile A reference reflow profile is given below. Please note the following when using RoHS/lead-free solder (SAC105/305/405 Tin-Silver-Cu): • The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT process. Modifications to the reference reflow profile may be required in order to accommodate the requirements of the other components in the application. • • An oven with 10 heating zones or above is recommended. • • • Mechanical stiffening can be used to minimize board warpage during reflow. • To ensure that the reflow profile meets the target specification on both sides of the board, a different profile and oven recipe for the first and second reflow may be required. It is suggested to decrease temperature cooling rate to minimize board warpage. This reflow profile applies only to RoHS/lead-free (high temperature) soldering process and it should not be used for Eutectic solder packages. Damage may result if this condition is violated. Maximum 3 reflows are allowed on the same part. Table 5-6 Recommended Board Solder Reflow Profile - RoHS/Lead-Free Solder Profiling Stage Temperature Process Range Overall Preheat Room temp to 220C 2 mins to 4 mins Soaking Time 130C to 170C Typical 60 – 80 seconds Liquidus 220C Typical 60 – 80 seconds Ramp Rate Ramp up and Cooling <2C / second Peak Max. 245C 235C +/-5C Temperature at peak within 5C 240C to 245C 10 – 30 seconds 43403 AMD 890FX Databook 3.00 5-6 © 2012 Advanced Micro Devices, Inc. Proprietary Package Information o Solder/Part Surface Temp. ( C ) Peak Temp. (235 oC+/-5% typ., 245 oC max.) 250 220 deg.C <2.0oC / Sec. 200 170 oC 150 Soaking Zone 130 oC 100 50 Soldering Zone 60 – 120 sec. max 60 – 80 sec. typical 45 - 90 sec. Max. 60 - 80 sec. typical <2.0o.C / Sec. Pre-heating Zone 2 min to 4 min Max. Heating Time Figure 5-4 RoHS/Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 5-7 Package Information This page is left blank intentionally. 43403 AMD 890FX Databook 3.00 5-8 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 6 Power Management and ACPI 6.1 ACPI Power Management Implementation This chapter describes the support for ACPI power management provided by the RD890. The RD890 system controller supports ACPI Revision 2.0. The hardware, system BIOS, and drivers of the RD890 have the logic required for meeting the power management specifications of PC2001, OnNow, and the Windows Logo Program and Device Requirements version 2.1. Table 6-1, “ACPI States Supported by the RD890,” describes the ACPI states supported by the RD890 system controller. Table 6-1 ACPI States Supported by the RD890 ACPI State Description Processor States: S0/C0: Working State Working State. The processor is executing instructions. S0/C1: Halt CPU Halt state. No instructions are executed. This state has the lowest latency on resume and contributes minimum power savings. S0/C2: Stop Grant Caches Snoopable Stop Grant or Cache Snoopable CPU state. This state offers more power savings but has a higher latency on resume than the C1 state. S0/C3/C1e: Stop Grant Caches Snoopable Processor is put into the Stop Grant state. Caches are still snoopable. The HyperTransport™ link may be disconnected and put into a low power state. System memory may be put into self-refresh. System States: S1: Standby Powered On Suspend System is in Standby mode. This state has low wakeup latency on resume. OEM support of this state is optional. S3: Standby Suspend to RAM System is off but context is saved to RAM. System memory is put into self-refresh. S4: Hibernate Suspend to Disk System is off but context is saved to disk. When the system transitions to the working state, the OS is resumed without a system re-boot. S5: Soft Off System is off. OS re-boots when the system transitions to the working state. G3: Mechanical Off Occurs when system power (AC or battery) is not present or is unable to keep the system in one of the other states. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 6-1 ACPI Power Management Implementation This page intentionally left blank. 43403 AMD 890FX Databook 3.00 6-2 © 2012 Advanced Micro Devices, Inc. Proprietary Chapter 7 Testability 7.1 Test Capability Features The RD890 system controller has integrated test modes and capabilities. These test features cover both the ASIC and board level testing. The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part. The board level tests modes can be used for motherboard manufacturing and debug purposes. The following are the test modes of the RD890 system controller: • Full scan implementation on the digital core logic that provides about 97% fault coverage through ATPG (Automatic Test Pattern Generation Vectors). • Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules. • Improved access to the analog modules and PLLs in the RD890 system controller in order to allow full evaluation and characterization of these modules. • A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) in order to allow board level testing of neighboring devices. • An XOR TREE test mode on all the digital I/O’s to allow for proper soldering verification at the board level. • A VOH/VOL test mode on all digital I/O’s to allow for proper verification of output high and output low voltages at the board level. These test modes can be accessed through the settings on the instruction register of the JTAG circuitry. 7.2 Test Interface Table 7-1 Pins on the Test Interface Pin Name 7.3 7.3.1 Ball number Type Description TESTMODE A19 I TEST_EN: Test Enable (IEEE 1149.1 test port reset) PCIE_RESET_GPIO3 D19 I TMS: Test Mode Select (IEEE 1149.1 test mode select) I2C_DATA C20 I TDI: Test Mode Data In (IEEE 1149.1 data in) I2C_CLK B20 I TCLK: Test Mode Clock (IEEE 1149.1 clock) PWM_GPIO6 B16 O TDO: Test Mode Data Out (IEEE 1149.1 data out) PWM_GPIO4 A15 I TEST_ODD: Control ODD output in VOH/VOL test PWM_GPIO3 F16 I TEST_EVEN: Control EVEN output in VOH/VOL test POWERGOOD A17 I I/O Reset XOR Tree Brief Description of an XOR Tree A sample of a generic XOR tree is shown in the figure below. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 7-1 XOR Tree XOR Start Signal G F A E D C B Figure 7-1 XOR Tree Pin A is assigned to the output direction, and pins B through F are assigned to the input direction. It can be seen that after all pins B to F are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin A. The following is the truth table for the XOR tree shown in Figure 7-1 The XOR start signal is assumed to be logic 1. Table 7-2 Example of an XOR Tree Test Vector number 7.3.2 Input Pin G Input Pin F Input Pin E Input Pin D Input Pin C Input Pin B Output Pin A 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 0 3 1 1 0 0 0 0 1 4 1 1 1 0 0 0 0 5 1 1 1 1 0 0 1 6 1 1 1 1 1 0 0 7 1 1 1 1 1 1 1 Description of the XOR Tree for the RD890 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin. Refer to Section 7.3.4 for the list of the signals included on the XOR tree. There is no specific order to these signals in the tree. A toggle of any of these balls in the XOR tree will cause the output to toggle. 7.3.3 XOR Tree Activation To activate the XOR tree and run a XOR test, perform the sequence below: 1. Supply a 10MHz clock to I2C_CLK (Test Mode Clock) and a differential clock pair to the HT_REFCLKP1/N1, GFX_REFCLKP/N, GFX2_REFCLKP/N and GPP_REFCLKP/N pins. 2. Set POWERGOOD to 0. 3. Set TESTMODE to 1. 4. Set PCIE_RESET_GPIO2 to 0. 5. Wait 5 or more I2C_CLK cycles. 6. Load JTAG instruction register with the instruction 0001 1111. 7. Load JTAG instruction register with the instruction 0010 0000. 8. Load JTAG instruction register with the instruction 0000 1000. 9. Go to Run-Test_Idle state. 10. Set POWERGOOD to 1. 43403 AMD 890FX Databook 3.00 7-2 © 2012 Advanced Micro Devices, Inc. Proprietary XOR Tree 7.3.4 XOR Tree for the RD890 The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the TDO Pin. Refer to Table 7-3 for the list of the signals included on the XOR tree. There is no specific order to these signals in the tree. A toggle of any of these balls in the XOR tree will cause the output to toggle. When the XOR tree is activated, any pin on the XOR tree must be either pulled down or pulled up to the I/O voltage of the pin. Only pins that are not on the XOR tree can be left floating. When differential signal pairs are listed as single entries on the XOR tree, opposite input values should be applied to the two signals in each pair (e.g., for entry no. 1 on the tree, when “1” is applied to HT_RXCAD0P, “0” should be applied to HT_RXCAD0N). Table 7-3 RD890 XOR Tree No. Pin Name Ball Ref. No. Pin Name Ball Ref. 1 HT_RXCAD0P/N AD28/AD27 29 GFX_RX10P/N H5/H4 2 HT_RXCAD1P/N AC27/AC26 30 GFX_RX11P/N J6/J5 3 HT_RXCAD2P/N AB28/AB27 31 GFX_RX12P/N K5/K4 4 HT_RXCAD3P/N AA27/AA26 32 GFX_RX13P/N L6/L5 5 HT_RXCAD4P/N W27/W26 33 GFX_RX14P/N M5/M4 6 HT_RXCAD5P/N V28/V27 34 GFX_RX15P/N N6/N5 7 HT_RXCAD6P/N U27/U26 35 GFX2_RX0P/N P5/P4 8 HT_RXCAD7P/N T28/T27 36 GFX2_RX1P/N R6/R5 9 HT_RXCTL0P/N R27/R26 37 GFX2_RX2P/N T5/T4 10 HT_RXCAD8P/N AD25/AD24 38 GFX2_RX3P/N U6/U5 11 HT_RXCAD9P/N AC24/AC23 39 GFX2_RX4P/N V5/V4 12 HT_RXCAD10P/N AB25/AB24 40 GFX2_RX5P/N W6/W5 13 HT_RXCAD11P/N AA24/AA23 41 GFX2_RX6P/N Y5/Y4 14 HT_RXCAD12P/N W24/W23 42 GFX2_RX7P/N AA6/AA5 15 HT_RXCAD13P/N V25/V24 43 GFX2_RX8P/N AB5/AB4 16 HT_RXCAD14P/N U24/U23 44 GFX2_RX9P/N AD2/AD1 17 HT_RXCAD15P/N T25/T24 45 GFX2_RX10P/N AF2/AF1 18 HT_RXCTL1P/N R24/R23 46 GFX2_RX11P/N AF5/AG5 19 GFX_RX0P/N E11/F11 47 GFX2_RX12P/N AD6/AE6 20 GFX_RX1P/N D10/E10 48 GFX2_RX13P/N AC7/AD7 21 GFX_RX2P/N E9/F9 49 GFX2_RX14P/N AD8/AE8 22 GFX_RX3P/N D8/E8 50 GFX2_RX15P/N AC9/AD9 23 GFX_RX4P/N E7/F7 51 GPP_RX0P/N AH20/AG20 24 GFX_RX5P/N D6/E6 52 GPP_RX1P/N AD19/AC19 25 GFX_RX6P/N B5/C5 53 GPP_RX2P/N AE18/AD18 26 GFX_RX7P/N D2/D1 54 GPP_RX3P/N AD17/AC17 27 GFX_RX8P/N F5/F4 55 GPP_RX4P/N AE16/AD16 28 GFX_RX9P/N G6/G5 56 GPP_RX5P/N AD15/AC15 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 7-3 VOH/VOL Test 7.4 7.4.1 No. Pin Name Ball Ref. 57 SB_RX0P/N AG26/AH26 58 SB_RX1P/N AF25/AG25 59 SB_RX2P/N AD22/AE22 60 SB_RX3P/N AC21/AD21 61 GPP_RX6P/N AE14/AD14 62 GPP_RX7P/N AD13/AC13 63 GPP_RX8P/N AE12/AD12 64 GPP_RX9P/N AD11/AC11 65 PWM_GPIO1 E16 66 PWM_GPIO2 B15 67 PWM_GPIO3 F16 68 PWM_GPIO4 A15 69 PWM_GPIO5 C16 70 PCIE_RESET_GPIO1 B19 71 PCIE_RESET_GPIO4 E19 72 PCIE_RESET_GPIO5 E17 73 DFT_GPIO0 B26 74 DFT_GPIO1 A25 75 DFT_GPIO2 B24 76 DFT_GPIO3 B25 77 DFT_GPIO4 B23 78 DFT_GPIO5 A23 79 DBG_GPIO0 C22 80 DBG_GPIO1 B22 81 DBG_GPIO2 B21 82 DBG_GPIO3 A21 83 ALLOW_LDTSTOP D21 84 LDTSTOP# E15 VOH/VOL Test Brief Description of a VOH/VOL Tree The VOH/VOL logic provides signal output on I/O’s when test patterns are applied to the TEST_ODD and TEST_EVEN pins. A sample of a generic VOH/VOL tree is shown in the figure below. 43403 AMD 890FX Databook 3.00 7-4 © 2012 Advanced Micro Devices, Inc. Proprietary VOH/VOL Test TEST_ODD TEST_EVEN VOH/VOL mode 1 2 3 4 5 6 Figure 7-2 Sample of a Generic VOH/VOL Tree The following is the truth table for the above VOH/VOL tree. Table 7-4 Truth Table for the VOH/VOL Tree Outputs Test Vector Number TEST_ODD Input TEST_EVEN Input Output Pin 1 Output Pin 2 Output Pin 3 Output Pin 4 Output Pin 5 Output Pin 6 1 0 0 0 0 0 0 0 0 2 0 1 0 1 0 1 0 1 3 1 0 1 0 1 0 1 0 4 1 1 1 1 1 1 1 1 Refer to Table 7-5 below for the list of pins that are on the VOH/VOL tree. 7.4.2 VOH/VOL Tree Activation To activate the VOH/VOL tree and run a VOH/VOL test, perform the sequence below: 1. Supply a 10MHz clock to I2C_CLK (Test Mode Clock) and a differential clock pair to the HT_REFCLKP1/N1, GFX_REFCLKP/N, GFX2_REFCLKP/N and GPP_REFCLKP/N pins. 2. Set POWERGOOD to 0. 3. Set TESTMODE to 1. 4. Set PCIE_RESET_GPIO2 to 0. 5. Wait 5 or more I2C_CLK cycles. 6. Load JTAG instruction register with the instruction 0001 1111. 7. Load JTAG instruction register with the instruction 0010 0000. 8. Load JTAG instruction register with the instruction 0101 1101. 9. Go to Run-Test_Idle state. 10. Set POWERGOOD to 1. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 7-5 VOH/VOL Test 7.4.3 VOH/VOL pin list Table 7-5 below shows the RD890 VOH/VOL Tree. There is no specific order of connection. Under the Control column, an “Odd” or “Even” indicates that the logical output of the pin is same as the input to the “TEST_ODD” or the “TEST_EVEN” pin respectively. When a differential signal pair appear in the table as a single entry, the output of the positive (“P”) pin is indicated in the Control column (see last paragraph for explanations) and the output of the negative pin (“N”) will be of the opposite value. E.g., for entry no. 1 on the tree, when TEST_EVEN is 1, HT_TXCAD0P will give a value of 1 and HT_TXCAD0N will give a value of 0. Table 7-5 RD890 VOH/VOL Tree No. Pin Name Ball Ref. Control 1 HT_TXCAD0P/N E26/E27 Even 2 HT_TXCAD1P/N F27/F28 Odd 3 HT_TXCAD2P/N G26/G27 Even 4 HT_TXCAD3P/N H27/H28 Odd 5 HT_TXCAD4P/N K27/K28 Even 6 HT_TXCAD5P/N L26/L27 Odd 7 HT_TXCAD6P/N M27/M28 Even 8 HT_TXCAD7P/N N26/N27 Odd 9 HT_TXCTL0P/N P27/P28 Even 10 HT_TXCAD8P/N E23/E24 Odd 11 HT_TXCAD9P/N F24/F25 Even 12 HT_TXCAD10P/N G23/G24 Odd 13 HT_TXCAD11P/N H24/H25 Even 14 HT_TXCAD12P/N K24/K25 Odd 15 HT_TXCAD13P/N L23/L24 Even 16 HT_TXCAD14P/N M24/M25 Odd 17 HT_TXCAD15P/N N23/N24 Even 18 HT_TXCTL1P/N P24/P25 Odd 19 GFX_TX0P/N B11/C11 Even 20 GFX_TX1P/N A10/B10 Odd 21 GFX_TX2P/N B9/C9 Even 22 GFX_TX3P/N A8/B8 Odd 23 GFX_TX4P/N B7/C7 Even 24 GFX_TX5P/N A6/B6 Odd 25 GFX_TX6P/N A4/B4 Even 26 GFX_TX7P/N E3/E2 Odd 27 GFX_TX8P/N F2/F1 Even 28 GFX_TX9P/N G3/G2 Odd 29 GFX_TX10P/N H2/H1 Even 43403 AMD 890FX Databook 3.00 7-6 No. Pin Name Ball Ref. Control 30 GFX_TX11P/N J3/J2 Odd 31 GFX_TX12P/N K2/K1 Even 32 GFX_TX13P/N L3/L2 Odd 33 GFX_TX14P/N M2/M1 Even 34 GFX_TX15P/N N3/N2 Odd 35 GFX2_TX0P/N P2/P1 Even 36 GFX2_TX1P/N R3/R2 Odd 37 GFX2_TX2P/N T2/T1 Even 38 GFX2_TX3P/N U3/U2 Odd 39 GFX2_TX4P/N V2/V1 Even 40 GFX2_TX5P/N W3/W2 Odd 41 GFX2_TX6P/N Y2/Y1 Even 42 GFX2_TX7P/N AA3/AA2 Odd 43 GFX2_TX8P/N AB2/AB1 Even 44 GFX2_TX9P/N AC3/AC2 Odd 45 GFX2_TX10P/N AE3/AE2 Even 46 GFX2_TX11P/N AG4/AH4 Odd 47 GFX2_TX12P/N AG6/AH6 Even 48 GFX2_TX13P/N AF7/AG7 Odd 49 GFX2_TX14P/N AG8/AH8 Even 50 GFX2_TX15P/N AF9/AG9 Odd 51 GPP_TX0P/N AG19/AF19 Even 52 GPP_TX1P/N AH18/AG18 Odd 53 GPP_TX2P/N AG17/AF17 Even 54 GPP_TX3P/N AH16/AG16 Odd 55 GPP_TX4P/N AG15/AF15 Even 56 GPP_TX5P/N AH14/AG14 Odd 57 SB_TX0P/N AG24/AH24 Even 58 SB_TX1P/N AF23/AG23 Odd © 2012 Advanced Micro Devices, Inc. Proprietary VOH/VOL Test No. Pin Name Ball Ref. Control 59 SB_TX2P/N AF21/AG21 Even 60 SB_TX3P/N AG22/AH22 Odd 61 GPP_TX6P/N AG13/AF13 Even 62 GPP_TX7P/N AH12/AG12 Odd 63 GPP_TX8P/N AG11/AF11 Even 64 GPP_TX9P/N AH10/AG10 Odd 65 PWM_GPIO1 E16 Even 66 PWM_GPIO2 B15 Odd 67 PWM_GPIO5 C16 Even 68 PCIE_RESET_GPIO1 B19 Odd 69 PCIE_RESET_GPIO4 E19 Even 70 PCIE_RESET_GPIO5 E17 Odd 71 DFT_GPIO0 B26 Even 72 DFT_GPIO1 A25 Odd 73 DFT_GPIO2 B24 Even 74 DFT_GPIO3 B25 Odd 75 DFT_GPIO4 B23 Even 76 DFT_GPIO5 A23 Odd 77 DBG_GPIO0 C22 Even 78 DBG_GPIO1 B22 Odd 79 DBG_GPIO2 B21 Even 80 DBG_GPIO3 A21 Odd 81 ALLOW_LDTSTOP D21 Even 82 LDTSTOP# E15 Odd © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 7-7 VOH/VOL Test This page intentionally left blank. 43403 AMD 890FX Databook 3.00 7-8 © 2012 Advanced Micro Devices, Inc. Proprietary Appendix A Pin Listings This appendix contains pin listings for the RD890 sorted in different ways. To go to the listing of interest, use the linked cross-references below: “RD890 Pin Listing Sorted by Ball Reference” on page A-2 “RD890 Pin Listing Sorted by Pin Name” on page A-9 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-1 RD890 Pin Listing Sorted by Ball Reference A.1 RD890 Pin Listing Sorted by Ball Reference Table A-1 RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name A10 GFX_TX1P AA19 VSS AB24 HT_RXCAD10N A11 VSS AA2 GFX2_TX7N AB25 HT_RXCAD10P A12 VDDA18PCIE AA20 VSS AB26 VSS A13 VDDA18PCIE AA21 THERMALDIODE_N AB27 HT_RXCAD2N A14 VSS AA22 VDDHT AB28 HT_RXCAD2P A15 PWM_GPIO4 AA23 HT_RXCAD11N AB3 VSS A16 VSS AA24 HT_RXCAD11P AB4 GFX2_RX8N A17 POWERGOOD AA25 VSS AB5 GFX2_RX8P A18 VDD18 AA26 HT_RXCAD3N AB6 VSS A19 TESTMODE AA27 HT_RXCAD3P AB7 VDDPCIE A20 VSS AA28 VSS AB8 VSS A21 DBG_GPIO3 AA3 GFX2_TX7P AB9 VDDPCIE A22 VSS AA4 VSS AC1 VSS A23 DFT_GPIO5 AA5 GFX2_RX7N AC10 VSS A24 VSS AA6 GFX2_RX7P AC11 GPP_RX9N A25 DFT_GPIO1 AA7 VSS AC12 VSS A26 VSS AA8 VDDPCIE AC13 GPP_RX7N A3 VDDPCIE AA9 VSS AC14 VSS A4 GFX_TX6P AB1 GFX2_TX8N AC15 GPP_RX5N A5 VSS AB10 VSS AC16 VSS A6 GFX_TX5P AB11 VDDPCIE AC17 GPP_RX3N A7 VSS AB12 VSS AC18 VSS A8 GFX_TX3P AB13 VDDPCIE AC19 GPP_RX1N A9 VSS AB14 VSS AC2 GFX2_TX9N AA1 VSS AB15 VDDPCIE AC20 VSS AA10 VDDPCIE AB16 VSS AC21 SB_RX3P AA11 VSS AB17 VDDPCIE AC22 VDDHT AA12 VDDPCIE AB18 VSS AC23 HT_RXCAD9N AA13 VSS AB19 VDDPCIE AC24 HT_RXCAD9P AA14 GPP_REFCLKN AB2 GFX2_TX8P AC25 VSS AA15 GPP_REFCLKP AB20 VSS AC26 HT_RXCAD1N AA16 VDDPCIE AB21 VSS AC27 HT_RXCAD1P AA17 VSS AB22 VDDHT AC28 VSS AA18 VDDPCIE AB23 VSS AC3 GFX2_TX9P 43403 AMD 890FX Databook 3.00 Appendix A-2 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name AC4 VSS AE12 GPP_RX8P AF20 VSS AC5 VSS AE13 VSS AF21 SB_TX2P AC6 VDDPCIE AE14 GPP_RX6P AF22 VSS AC7 GFX2_RX13P AE15 VSS AF23 SB_TX1P AC8 VSS AE16 GPP_RX4P AF24 VSS AC9 GFX2_RX15P AE17 VSS AF25 SB_RX1P AD1 GFX2_RX9N AE18 GPP_RX2P AF26 VSS AD10 PCE_RCALRN AE19 VSS AF27 VDDHT AD11 GPP_RX9P AE2 GFX2_TX10N AF28 VSS AD12 GPP_RX8N AE20 PCE_BCALRP AF3 VDDPCIE AD13 GPP_RX7P AE21 VSS AF4 VSS AD14 GPP_RX6N AE22 SB_RX2N AF5 GFX2_RX11P AD15 GPP_RX5P AE23 VSS AF6 VSS AD16 GPP_RX4N AE24 VDDHT AF7 GFX2_TX13P AD17 GPP_RX3P AE25 VDDHT AF8 VSS AD18 GPP_RX2N AE26 VDDHT AF9 GFX2_TX15P AD19 GPP_RX1P AE27 VDDHT AG10 GPP_TX9N AD2 GFX2_RX9P AE28 VDDHT AG11 GPP_TX8P AD20 PCE_BCALRN AE3 GFX2_TX10P AG12 GPP_TX7N AD21 SB_RX3N AE4 VDDPCIE AG13 GPP_TX6P AD22 SB_RX2P AE5 VSS AG14 GPP_TX5N AD23 VDDHT AE6 GFX2_RX12N AG15 GPP_TX4P AD24 HT_RXCAD8N AE7 VSS AG16 GPP_TX3N AD25 HT_RXCAD8P AE8 GFX2_RX14N AG17 GPP_TX2P AD26 VSS AE9 VSS AG18 GPP_TX1N AD27 HT_RXCAD0N AF1 GFX2_RX10N AG19 GPP_TX0P AD28 HT_RXCAD0P AF10 VSS AG2 VDDPCIE AD3 VSS AF11 GPP_TX8N AG20 GPP_RX0N AD4 VSS AF12 VSS AG21 SB_TX2N AD5 VDDPCIE AF13 GPP_TX6N AG22 SB_TX3P AD6 GFX2_RX12P AF14 VSS AG23 SB_TX1N AD7 GFX2_RX13N AF15 GPP_TX4N AG24 SB_TX0P AD8 GFX2_RX14P AF16 VSS AG25 SB_RX1N AD9 GFX2_RX15N AF17 GPP_TX2N AG26 SB_RX0P AE1 VSS AF18 VSS AG27 VSS AE10 PCE_RCALRP AF19 GPP_TX0N AG3 VSS AE11 VSS AF2 GFX2_RX10P AG4 GFX2_TX11P © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-3 RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name AG5 GFX2_RX11N B17 OSCIN C25 VDDHTTX AG6 GFX2_TX12P B18 VDD18 C26 VDDHTTX AG7 GFX2_TX13N B19 C27 VDDHTTX AG8 GFX2_TX14P PCIE_RESET_GPIO 1 C28 VDDHTTX B2 VDDPCIE C3 VDDPCIE B20 I2C_CLK C4 VSS B21 DBG_GPIO2 C5 GFX_RX6N B22 DBG_GPIO1 C6 VSS B23 DFT_GPIO4 C7 GFX_TX4N B24 DFT_GPIO2 C8 VSS B25 DFT_GPIO3 C9 GFX_TX2N B26 DFT_GPIO0 D1 GFX_RX7N B27 VSS D10 GFX_RX1P B3 VSS D11 VSS B4 GFX_TX6N D12 VDDA18PCIE B5 GFX_RX6P D13 VDDA18PCIE B6 GFX_TX5N D14 VSS B7 GFX_TX4P D15 SYSRESET# B8 GFX_TX3N D16 VSS B9 GFX_TX2P C1 VDDPCIE D17 PCIE_RESET_GPIO 2 C10 VSS D18 VDD18 C11 GFX_TX0N D19 C12 VDDA18PCIE PCIE_RESET_GPIO 3 C13 VDDA18PCIE D2 GFX_RX7P C14 VSS D20 VSS C15 VSS D21 ALLOW_LDTSTOP C16 PWM_GPIO5 D22 VDDHTTX C17 VSS D23 VDDHTTX C18 VDD18 D24 HT_RXCALN C19 VSS D25 HT_RXCALP C2 VSS D26 VSS C20 I2C_DATA D27 HT_TXCALN C21 VSS D28 HT_TXCALP C22 DBG_GPIO0 D3 VSS C23 VSS D4 VDDPCIE C24 VDDHTTX D5 VSS AG9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 GFX2_TX15N GPP_TX9P VSS GPP_TX7P VSS GPP_TX5P VSS GPP_TX3P VSS GPP_TX1P VSS GPP_RX0P VSS SB_TX3N VSS SB_TX0N AH25 VSS AH26 SB_RX0N AH3 VSS AH4 GFX2_TX11N AH5 AH6 AH7 AH8 AH9 B10 B11 B12 B13 B14 B15 B16 VSS GFX2_TX12N VSS GFX2_TX14N VSS GFX_TX1N GFX_TX0P VDDA18PCIE VDDA18PCIE VSS PWM_GPIO2 PWM_GPIO6 43403 AMD 890FX Databook 3.00 Appendix A-4 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name D6 GFX_RX5P F12 VDDA18PCIE G2 GFX_TX9N D7 VSS F13 VDDA18PCIE G20 VSS D8 GFX_RX3P F14 PCE_TCALRP G21 VDDA18HTPLL D9 VSS F15 VSS G22 VDDHTTX E1 VSS F16 PWM_GPIO3 G23 HT_TXCAD10P E10 GFX_RX1N F17 VSS G24 HT_TXCAD10N E11 GFX_RX0P F18 VSS G25 VSS E12 VDDA18PCIE F19 VSS G26 HT_TXCAD2P E13 VDDA18PCIE F2 GFX_TX8P G27 HT_TXCAD2N E14 PCE_TCALRN F20 VSS G28 VSS E15 LDTSTOP# F21 VSS G3 GFX_TX9P E16 PWM_GPIO1 F22 VDDHTTX G4 VSS E17 PCIE_RESET_GPIO 5 F23 VSS G5 GFX_RX9N F24 HT_TXCAD9P G6 GFX_RX9P E18 VDD18 F25 HT_TXCAD9N G7 VDDPCIE E19 PCIE_RESET_GPIO 4 F26 VSS G8 VDDPCIE E2 GFX_TX7N F27 HT_TXCAD1P G9 VSS E20 VSS F28 HT_TXCAD1N H1 GFX_TX10N E21 STRP_DATA F3 VSS H10 VSS E22 VDDHTTX F4 GFX_RX8N H11 VDDPCIE E23 HT_TXCAD8P F5 GFX_RX8P H12 VDDA18PCIE E24 HT_TXCAD8N F6 VDDPCIE H13 VDDA18PCIE E25 VSS F7 GFX_RX4N H14 VDDA18PCIE E26 HT_TXCAD0P F8 VSS H15 VSS E27 HT_TXCAD0N F9 GFX_RX2N H16 VSS E28 VSS G1 VSS H17 VSS E3 GFX_TX7P G10 VDDPCIE H18 VSS E4 VSS G11 VSS H19 VSS E5 VDDPCIE G12 VDDA18PCIE H2 GFX_TX10P E6 GFX_RX5N G13 VDDA18PCIE H20 VSS E7 GFX_RX4P G14 VDDA18PCIE H21 VSS E8 GFX_RX3N G15 VSS H22 VDDHTTX E9 GFX_RX2P G16 VSS H23 VSS F1 GFX_TX8N G17 VSS H24 HT_TXCAD11P F10 VSS G18 VSS H25 HT_TXCAD11N F11 GFX_RX0N G19 VSS H26 VSS © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-5 RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name H27 HT_TXCAD3P K4 GFX_RX12N M17 VSS H28 HT_TXCAD3N K5 GFX_RX12P M18 VSS H3 VSS K6 VSS M2 GFX_TX14P H4 GFX_RX10N K7 VDDPCIE M21 VSS H5 GFX_RX10P K8 VSS M22 VDDHT H6 VSS L1 VSS M23 VSS H7 VDDPCIE L11 VDDA18PCIE M24 HT_TXCAD14P H8 GFX_REFCLKN L12 VSS M25 HT_TXCAD14N H9 VDDPCIE L13 VSS M26 VSS J1 VSS L14 VDDC M27 HT_TXCAD6P J2 GFX_TX11N L15 VSS M28 HT_TXCAD6N J21 HT_REFCLKN L16 VDDC M3 VSS J22 VSS L17 VSS M4 GFX_RX14N J23 HT_TXCLK1P L18 VSS M5 GFX_RX14P J24 HT_TXCLK1N L2 GFX_TX13N M6 VSS J25 VSS L21 VDDHT M7 VDDPCIE J26 HT_TXCLK0P L22 VSS M8 VSS J27 HT_TXCLK0N L23 HT_TXCAD13P N1 VSS J28 VSS L24 HT_TXCAD13N N11 VSS J3 GFX_TX11P L25 VSS N12 VDDC J4 VSS L26 HT_TXCAD5P N13 VSS J5 GFX_RX11N L27 HT_TXCAD5N N14 VDDC J6 GFX_RX11P L28 VSS N15 VSS J7 VSS L3 GFX_TX13P N16 VDDC J8 GFX_REFCLKP L4 VSS N17 VSS K1 GFX_TX12N L5 GFX_RX13N N18 VSS K2 GFX_TX12P L6 GFX_RX13P N2 GFX_TX15N K21 HT_REFCLKP L7 VSS N21 VDDHT K22 VDDHT L8 VDDPCIE N22 VSS K23 VSS M1 GFX_TX14N N23 HT_TXCAD15P K24 HT_TXCAD12P M11 VSS N24 HT_TXCAD15N K25 HT_TXCAD12N M12 VSS N25 VSS K26 VSS M13 VDDC N26 HT_TXCAD7P K27 HT_TXCAD4P M14 VSS N27 HT_TXCAD7N K28 HT_TXCAD4N M15 VDDC N28 VSS K3 VSS M16 VSS N3 GFX_TX15P 43403 AMD 890FX Databook 3.00 Appendix A-6 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name Ball # Ball Name N4 VSS R17 VSS T4 GFX2_RX2N N5 GFX_RX15N R18 VSS T5 GFX2_RX2P N6 GFX_RX15P R2 GFX2_TX1N T6 VSS N7 VSS R21 VDDHT T7 VDDPCIE N8 VDDPCIE R22 VSS T8 VSS P1 GFX2_TX0N R23 HT_RXCTL1N U1 VSS P11 VSS R24 HT_RXCTL1P U11 VSS P12 VSS R25 VSS U12 VSS P13 VDDC R26 HT_RXCTL0N U13 VSS P14 VSS R27 HT_RXCTL0P U14 VDDC P15 VDDC R28 VSS U15 VSS P16 VSS R3 GFX2_TX1P U16 VDDC P17 VDDC R4 VSS U17 VSS P18 VSS R5 GFX2_RX1N U18 VSS P2 GFX2_TX0P R6 GFX2_RX1P U2 GFX2_TX3N P21 VSS R7 VSS U21 VDDHT P22 VDDHT R8 VDDPCIE U22 VSS P23 VSS T1 GFX2_TX2N U23 HT_RXCAD14N P24 HT_TXCTL1P T11 VSS U24 HT_RXCAD14P P25 HT_TXCTL1N T12 VSS U25 VSS P26 VSS T13 VDDC U26 HT_RXCAD6N P27 HT_TXCTL0P T14 VSS U27 HT_RXCAD6P P28 HT_TXCTL0N T15 VDDC U28 VSS P3 VSS T16 VSS U3 GFX2_TX3P P4 GFX2_RX0N T17 VDDC U4 VSS P5 GFX2_RX0P T18 VSS U5 GFX2_RX3N P6 VSS T2 GFX2_TX2P U6 GFX2_RX3P P7 VDDPCIE T21 VSS U7 VSS P8 VSS T22 VDDHT U8 GFX2_REFCLKN R1 VSS T23 VSS V1 GFX2_TX4N R11 VSS T24 HT_RXCAD15N V11 VDDA18PCIE R12 VDDC T25 HT_RXCAD15P V12 VSS R13 VSS T26 VSS V13 VSS R14 VDDC T27 HT_RXCAD7N V14 VSS R15 VSS T28 HT_RXCAD7P V15 VSS R16 VDDC T3 VSS V16 VSS © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-7 RD890 Pin Listing Sorted by Ball Reference Ball # Ball Name Ball # Ball Name V17 VSS Y22 VDDHT V18 VDDA18PCIE Y23 VSS V2 GFX2_TX4P Y24 HT_RXCLK1N V21 VSS Y25 HT_RXCLK1P V22 VDDHT Y26 VSS V23 VSS Y27 HT_RXCLK0N V24 HT_RXCAD13N Y28 HT_RXCLK0P V25 HT_RXCAD13P Y3 VSS V26 VSS Y4 GFX2_RX6N V27 HT_RXCAD5N Y5 GFX2_RX6P V28 HT_RXCAD5P Y6 VSS V3 VSS Y7 VDDPCIE V4 GFX2_RX4N Y8 VSS V5 GFX2_RX4P V6 VSS V7 VDDPCIE V8 GFX2_REFCLKP W1 VSS W2 GFX2_TX5N W21 VDDHT W22 VSS W23 HT_RXCAD12N W24 HT_RXCAD12P W25 VSS W26 HT_RXCAD4N W27 HT_RXCAD4P W28 VSS W3 GFX2_TX5P W4 VSS W5 GFX2_RX5N W6 GFX2_RX5P W7 VSS W8 VDDPCIE Y1 GFX2_TX6N Y2 GFX2_TX6P Y21 THERMALDIODE_P 43403 AMD 890FX Databook 3.00 Appendix A-8 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference A.2 RD890 Pin Listing Sorted by Pin Name Ball Name Ball # Ball Name Ball # Ball Name Ball # ALLOW_LDTSTOP D21 GFX_RX5N E6 GFX_TX6P A4 DBG_GPIO0 C22 GFX_RX5P D6 GFX_TX7N E2 DBG_GPIO1 B22 GFX_RX6N C5 GFX_TX7P E3 DBG_GPIO2 B21 GFX_RX6P B5 GFX_TX8N F1 DBG_GPIO3 A21 GFX_RX7N D1 GFX_TX8P F2 DFT_GPIO0 B26 GFX_RX7P D2 GFX_TX9N G2 DFT_GPIO1 A25 GFX_RX8N F4 GFX_TX9P G3 DFT_GPIO2 B24 GFX_RX8P F5 GFX2_REFCLKN U8 DFT_GPIO3 B25 GFX_RX9N G5 GFX2_REFCLKP V8 DFT_GPIO4 B23 GFX_RX9P G6 GFX2_RX0N P4 DFT_GPIO5 A23 GFX_TX0N C11 GFX2_RX0P P5 GFX_REFCLKN H8 GFX_TX0P B11 GFX2_RX10N AF1 GFX_REFCLKP J8 GFX_TX10N H1 GFX2_RX10P AF2 GFX_RX0N F11 GFX_TX10P H2 GFX2_RX11N AG5 GFX_RX0P E11 GFX_TX11N J2 GFX2_RX11P AF5 GFX_RX10N H4 GFX_TX11P J3 GFX2_RX12N AE6 GFX_RX10P H5 GFX_TX12N K1 GFX2_RX12P AD6 GFX_RX11N J5 GFX_TX12P K2 GFX2_RX13N AD7 GFX_RX11P J6 GFX_TX13N L2 GFX2_RX13P AC7 GFX_RX12N K4 GFX_TX13P L3 GFX2_RX14N AE8 GFX_RX12P K5 GFX_TX14N M1 GFX2_RX14P AD8 GFX_RX13N L5 GFX_TX14P M2 GFX2_RX15N AD9 GFX_RX13P L6 GFX_TX15N N2 GFX2_RX15P AC9 GFX_RX14N M4 GFX_TX15P N3 GFX2_RX1N R5 GFX_RX14P M5 GFX_TX1N B10 GFX2_RX1P R6 GFX_RX15N N5 GFX_TX1P A10 GFX2_RX2N T4 GFX_RX15P N6 GFX_TX2N C9 GFX2_RX2P T5 GFX_RX1N E10 GFX_TX2P B9 GFX2_RX3N U5 GFX_RX1P D10 GFX_TX3N B8 GFX2_RX3P U6 GFX_RX2N F9 GFX_TX3P A8 GFX2_RX4N V4 GFX_RX2P E9 GFX_TX4N C7 GFX2_RX4P V5 GFX_RX3N E8 GFX_TX4P B7 GFX2_RX5N W5 GFX_RX3P D8 GFX_TX5N B6 GFX2_RX5P W6 GFX_RX4N F7 GFX_TX5P A6 GFX2_RX6N Y4 GFX_RX4P E7 GFX_TX6N B4 GFX2_RX6P Y5 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-9 RD890 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # GFX2_RX7N AA5 GFX2_TX9N AC2 GPP_TX6N AF13 GFX2_RX7P AA6 GFX2_TX9P AC3 GPP_TX6P AG13 GFX2_RX8N AB4 GPP_REFCLKN AA14 GPP_TX7N AG12 GFX2_RX8P AB5 GPP_REFCLKP AA15 GPP_TX7P AH12 GFX2_RX9N AD1 GPP_RX0N AG20 GPP_TX8N AF11 GFX2_RX9P AD2 GPP_RX0P AH20 GPP_TX8P AG11 GFX2_TX0N P1 GPP_RX1N AC19 GPP_TX9N AG10 GFX2_TX0P P2 GPP_RX1P AD19 GPP_TX9P AH10 GFX2_TX10N AE2 GPP_RX2N AD18 HT_REFCLKN J21 GFX2_TX10P AE3 GPP_RX2P AE18 HT_REFCLKP K21 GFX2_TX11N AH4 GPP_RX3N AC17 HT_RXCAD0N AD27 GFX2_TX11P AG4 GPP_RX3P AD17 HT_RXCAD0P AD28 GFX2_TX12N AH6 GPP_RX4N AD16 HT_RXCAD10N AB24 GFX2_TX12P AG6 GPP_RX4P AE16 HT_RXCAD10P AB25 GFX2_TX13N AG7 GPP_RX5N AC15 HT_RXCAD11N AA23 GFX2_TX13P AF7 GPP_RX5P AD15 HT_RXCAD11P AA24 GFX2_TX14N AH8 GPP_RX6N AD14 HT_RXCAD12N W23 GFX2_TX14P AG8 GPP_RX6P AE14 HT_RXCAD12P W24 GFX2_TX15N AG9 GPP_RX7N AC13 HT_RXCAD13N V24 GFX2_TX15P AF9 GPP_RX7P AD13 HT_RXCAD13P V25 GFX2_TX1N R2 GPP_RX8N AD12 HT_RXCAD14N U23 GFX2_TX1P R3 GPP_RX8P AE12 HT_RXCAD14P U24 GFX2_TX2N T1 GPP_RX9N AC11 HT_RXCAD15N T24 GFX2_TX2P T2 GPP_RX9P AD11 HT_RXCAD15P T25 GFX2_TX3N U2 GPP_TX0N AF19 HT_RXCAD1N AC26 GFX2_TX3P U3 GPP_TX0P AG19 HT_RXCAD1P AC27 GFX2_TX4N V1 GPP_TX1N AG18 HT_RXCAD2N AB27 GFX2_TX4P V2 GPP_TX1P AH18 HT_RXCAD2P AB28 GFX2_TX5N W2 GPP_TX2N AF17 HT_RXCAD3N AA26 GFX2_TX5P W3 GPP_TX2P AG17 HT_RXCAD3P AA27 GFX2_TX6N Y1 GPP_TX3N AG16 HT_RXCAD4N W26 GFX2_TX6P Y2 GPP_TX3P AH16 HT_RXCAD4P W27 GFX2_TX7N AA2 GPP_TX4N AF15 HT_RXCAD5N V27 GFX2_TX7P AA3 GPP_TX4P AG15 HT_RXCAD5P V28 GFX2_TX8N AB1 GPP_TX5N AG14 HT_RXCAD6N U26 GFX2_TX8P AB2 GPP_TX5P AH14 HT_RXCAD6P U27 43403 AMD 890FX Databook 3.00 Appendix A-10 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # HT_RXCAD7N T27 HT_TXCAD4N K28 D19 HT_RXCAD7P T28 HT_TXCAD4P K27 PCIE_RESET_GPIO 3 HT_RXCAD8N AD24 HT_TXCAD5N L27 PCIE_RESET_GPIO 4 E19 HT_RXCAD8P AD25 HT_TXCAD5P L26 E17 HT_RXCAD9N AC23 HT_TXCAD6N M28 PCIE_RESET_GPIO 5 HT_RXCAD9P AC24 HT_TXCAD6P M27 POWERGOOD A17 HT_RXCALN D24 HT_TXCAD7N N27 PWM_GPIO1 E16 HT_RXCALP D25 HT_TXCAD7P N26 PWM_GPIO2 B15 HT_RXCLK0N Y27 HT_TXCAD8N E24 PWM_GPIO3 F16 HT_RXCLK0P Y28 HT_TXCAD8P E23 PWM_GPIO4 A15 HT_RXCLK1N Y24 HT_TXCAD9N F25 PWM_GPIO5 C16 HT_RXCLK1P Y25 HT_TXCAD9P F24 PWM_GPIO6 B16 HT_RXCTL0N R26 HT_TXCALN D27 SB_RX0N AH26 HT_RXCTL0P R27 HT_TXCALP D28 SB_RX0P AG26 HT_RXCTL1N R23 HT_TXCLK0N J27 SB_RX1N AG25 HT_RXCTL1P R24 HT_TXCLK0P J26 SB_RX1P AF25 HT_TXCAD0N E27 HT_TXCLK1N J24 SB_RX2N AE22 HT_TXCAD0P E26 HT_TXCLK1P J23 SB_RX2P AD22 HT_TXCAD10N G24 HT_TXCTL0N P28 SB_RX3N AD21 HT_TXCAD10P G23 HT_TXCTL0P P27 SB_RX3P AC21 HT_TXCAD11N H25 HT_TXCTL1N P25 SB_TX0N AH24 HT_TXCAD11P H24 HT_TXCTL1P P24 SB_TX0P AG24 HT_TXCAD12N K25 I2C_CLK B20 SB_TX1N AG23 HT_TXCAD12P K24 I2C_DATA C20 SB_TX1P AF23 HT_TXCAD13N L24 LDTSTOP# E15 SB_TX2N AG21 HT_TXCAD13P L23 OSCIN B17 SB_TX2P AF21 HT_TXCAD14N M25 PCE_BCALRN AD20 SB_TX3N AH22 HT_TXCAD14P M24 PCE_BCALRP AE20 SB_TX3P AG22 HT_TXCAD15N N24 PCE_RCALRN AD10 STRP_DATA E21 HT_TXCAD15P N23 PCE_RCALRP AE10 SYSRESET# D15 HT_TXCAD1N F28 PCE_TCALRN E14 TESTMODE A19 HT_TXCAD1P F27 PCE_TCALRP F14 THERMALDIODE_N AA21 HT_TXCAD2N G27 THERMALDIODE_P Y21 B19 HT_TXCAD2P G26 PCIE_RESET_GPIO 1 VDD18 A18 HT_TXCAD3N H28 PCIE_RESET_GPIO 2 D17 VDD18 B18 HT_TXCAD3P H27 VDD18 C18 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-11 RD890 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # VDD18 D18 VDDC R16 VDDHTTX G22 VDD18 E18 VDDC T13 VDDHTTX H22 VDDA18HTPLL G21 VDDC T15 VDDPCIE A3 VDDA18PCIE A12 VDDC T17 VDDPCIE AA10 VDDA18PCIE A13 VDDC U14 VDDPCIE AA12 VDDA18PCIE B12 VDDC U16 VDDPCIE AA16 VDDA18PCIE B13 VDDHT AA22 VDDPCIE AA18 VDDA18PCIE C12 VDDHT AB22 VDDPCIE AA8 VDDA18PCIE C13 VDDHT AC22 VDDPCIE AB11 VDDA18PCIE D12 VDDHT AD23 VDDPCIE AB13 VDDA18PCIE D13 VDDHT AE24 VDDPCIE AB15 VDDA18PCIE E12 VDDHT AE25 VDDPCIE AB17 VDDA18PCIE E13 VDDHT AE26 VDDPCIE AB19 VDDA18PCIE F12 VDDHT AE27 VDDPCIE AB7 VDDA18PCIE F13 VDDHT AE28 VDDPCIE AB9 VDDA18PCIE G12 VDDHT AF27 VDDPCIE AC6 VDDA18PCIE G13 VDDHT K22 VDDPCIE AD5 VDDA18PCIE G14 VDDHT L21 VDDPCIE AE4 VDDA18PCIE H12 VDDHT M22 VDDPCIE AF3 VDDA18PCIE H13 VDDHT N21 VDDPCIE AG2 VDDA18PCIE H14 VDDHT P22 VDDPCIE B2 VDDA18PCIE L11 VDDHT R21 VDDPCIE C1 VDDA18PCIE V11 VDDHT T22 VDDPCIE C3 VDDA18PCIE V18 VDDHT U21 VDDPCIE D4 VDDC L14 VDDHT V22 VDDPCIE E5 VDDC L16 VDDHT W21 VDDPCIE F6 VDDC M13 VDDHT Y22 VDDPCIE G10 VDDC M15 VDDHTTX C24 VDDPCIE G7 VDDC N12 VDDHTTX C25 VDDPCIE G8 VDDC N14 VDDHTTX C26 VDDPCIE H11 VDDC N16 VDDHTTX C27 VDDPCIE H7 VDDC P13 VDDHTTX C28 VDDPCIE H9 VDDC P15 VDDHTTX D22 VDDPCIE K7 VDDC P17 VDDHTTX D23 VDDPCIE L8 VDDC R12 VDDHTTX E22 VDDPCIE M7 VDDC R14 VDDHTTX F22 VDDPCIE N8 43403 AMD 890FX Databook 3.00 Appendix A-12 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # VDDPCIE P7 VSS AB3 VSS AF24 VDDPCIE R8 VSS AB6 VSS AF26 VDDPCIE T7 VSS AB8 VSS AF28 VDDPCIE V7 VSS AC1 VSS AF4 VDDPCIE W8 VSS AC10 VSS AF6 VDDPCIE Y7 VSS AC12 VSS AF8 VSS A11 VSS AC14 VSS AG27 VSS A14 VSS AC16 VSS AG3 VSS A16 VSS AC18 VSS AH11 VSS A20 VSS AC20 VSS AH13 VSS A22 VSS AC25 VSS AH15 VSS A24 VSS AC28 VSS AH17 VSS A26 VSS AC4 VSS AH19 VSS A5 VSS AC5 VSS AH21 VSS A7 VSS AC8 VSS AH23 VSS A9 VSS AD26 VSS AH25 VSS AA1 VSS AD3 VSS AH3 VSS AA11 VSS AD4 VSS AH5 VSS AA13 VSS AE1 VSS AH7 VSS AA17 VSS AE11 VSS AH9 VSS AA19 VSS AE13 VSS B14 VSS AA20 VSS AE15 VSS B27 VSS AA25 VSS AE17 VSS B3 VSS AA28 VSS AE19 VSS C10 VSS AA4 VSS AE21 VSS C14 VSS AA7 VSS AE23 VSS C15 VSS AA9 VSS AE5 VSS C17 VSS AB10 VSS AE7 VSS C19 VSS AB12 VSS AE9 VSS C2 VSS AB14 VSS AF10 VSS C21 VSS AB16 VSS AF12 VSS C23 VSS AB18 VSS AF14 VSS C4 VSS AB20 VSS AF16 VSS C6 VSS AB21 VSS AF18 VSS C8 VSS AB23 VSS AF20 VSS D11 VSS AB26 VSS AF22 VSS D14 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-13 RD890 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # Ball Name Ball # VSS D16 VSS H15 VSS M16 VSS D20 VSS H16 VSS M17 VSS D26 VSS H17 VSS M18 VSS D3 VSS H18 VSS M21 VSS D5 VSS H19 VSS M23 VSS D7 VSS H20 VSS M26 VSS D9 VSS H21 VSS M3 VSS E1 VSS H23 VSS M6 VSS E20 VSS H26 VSS M8 VSS E25 VSS H3 VSS N1 VSS E28 VSS H6 VSS N11 VSS E4 VSS J1 VSS N13 VSS F10 VSS J22 VSS N15 VSS F15 VSS J25 VSS N17 VSS F17 VSS J28 VSS N18 VSS F18 VSS J4 VSS N22 VSS F19 VSS J7 VSS N25 VSS F20 VSS K23 VSS N28 VSS F21 VSS K26 VSS N4 VSS F23 VSS K3 VSS N7 VSS F26 VSS K6 VSS P11 VSS F3 VSS K8 VSS P12 VSS F8 VSS L1 VSS P14 VSS G1 VSS L12 VSS P16 VSS G11 VSS L13 VSS P18 VSS G15 VSS L15 VSS P21 VSS G16 VSS L17 VSS P23 VSS G17 VSS L18 VSS P26 VSS G18 VSS L22 VSS P3 VSS G19 VSS L25 VSS P6 VSS G20 VSS L28 VSS P8 VSS G25 VSS L4 VSS R1 VSS G28 VSS L7 VSS R11 VSS G4 VSS M11 VSS R13 VSS G9 VSS M12 VSS R15 VSS H10 VSS M14 VSS R17 43403 AMD 890FX Databook 3.00 Appendix A-14 © 2012 Advanced Micro Devices, Inc. Proprietary RD890 Pin Listing Sorted by Ball Reference Ball Name Ball # Ball Name Ball # VSS R18 VSS V23 VSS R22 VSS V26 VSS R25 VSS V3 VSS R28 VSS V6 VSS R4 VSS W1 VSS R7 VSS W22 VSS T11 VSS W25 VSS T12 VSS W28 VSS T14 VSS W4 VSS T16 VSS W7 VSS T18 VSS Y23 VSS T21 VSS Y26 VSS T23 VSS Y3 VSS T26 VSS Y6 VSS T3 VSS Y8 VSS T6 VSS T8 VSS U1 VSS U11 VSS U12 VSS U13 VSS U15 VSS U17 VSS U18 VSS U22 VSS U25 VSS U28 VSS U4 VSS U7 VSS V12 VSS V13 VSS V14 VSS V15 VSS V16 VSS V17 VSS V21 © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix A-15 RD890 Pin Listing Sorted by Ball Reference This page is left blank intentionally. 43403 AMD 890FX Databook 3.00 Appendix A-16 © 2012 Advanced Micro Devices, Inc. Proprietary Appendix B Revision History Rev. 3.00 (Jan 2012) • First public release based on rev. 1.30 of the NDA version, with the following change: • Updated Section 3.5, “Clock Interface”: Made connection of GPP_REFCLKP/N mandatory. © 2012 Advanced Micro Devices, Inc. Proprietary 43403 AMD 890FX Databook 3.00 Appendix B-1 This page intentionally left blank. 43403 AMD 890FX Databook 3.00 Appendix B-2 © 2012 Advanced Micro Devices, Inc. Proprietary