1/4 STRUCTURE Silicon Monolithic Integrated Circuit PRODUCT SERIES 1ch Piezo Driver built-in 15MHz Oscillator TYPE BH6456GUL FEATURES ・Built-in 15MHz Oscillator ・Built in 1ch H Bridge Driver ・2-wire serial interface (I2C-compatible) Absolute maximum ratings (Ta=+25°C) Parameter Power supply voltage Motor power supply voltage Power save input voltage Control input voltage Power dissipation Operating temperature range Junction temperature Storage temperature range H-bridge output current Symbol VCC VM VPS VIN Pd Limit -0.3 to +4.5 -0.3 to +5.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 530※1 Unit V V V V mW Topr -25 to +85 °C Tjmax Tstg Iout +125 -55 to +125 -500 to +500※2 °C °C mA ※1 Conditions: mounted on a glass epoxy board (50mm 58mm 1.75mm; 8 layers). In case of Ta>25°C, reduced by 5.3 mW/°C. ※2 Must not exceed Pd, ASO, or Tjmax of 125°C. Operating Conditions (Ta= -25°C to +85°C) Parameter Power supply voltage Motor power supply voltage Power save input voltage Control input voltage 2-wire serial interface transmission rate H-bridge output current Symbol VCC VM VPS VIN SCL Iout Min. 2.3 2.3 0 0 - ※3 Must not exceed Pd, ASO. This product is not designed for protection against radioactive rays. Status of this document REV. A Typ. 3.0 3.0 - Max. 3.6 4.8 VCC VCC 400 400※3 Unit V V V V kHz mA 2/4 ○Electrical Characteristics (Unless otherwise specified Ta=25°C, VCC=VM=3.0V) Parameter Overall Circuit current during standby operation Circuit current UVLO UVLO voltage Power save input High level input voltage Low level input voltage High level input current Low level input current Control input(SDA,SCL) High level input voltage Low level input voltage Low level output voltage High level input current Low level input current H Bridge Drive Output ON-Resistance Cycle length of sequence drive Output rise time Output fall time ※4 Min. Limit Typ. Max. ICCST - 0 1 μA PS=L ICC - 3.2 6.4 mA PS=H, SCL=400kHz, OSC active VUVLO 1.8 - 2.2 V VPSH VPSL IPSH IPSL 1.5 0 15 -3 30 0 VCC 0.5 60 - V V μA μA VINH=3.0V VINL=0V VINH VINL VOL IINH IINL 1.5 0 -10 -10 - VCC 0.5 0.4 10 10 V V V μA μA IIN=3.0mA (SDA) Input voltage=VCC Input voltage=GND RONP RONN - 0.7 0.7 1.0 1.0 Ω TMIN 10.35 10.67 11.00 μs ※4 Built in CLK 160 count μs ※5 μs ※5 7.5Ω load condition 7.5Ω load condition Symbol Tr Tf - 0.1 0.02 0.8 0.4 Unit Conditions Ω The time that 1 cycle of sequence drive at the below setting of 2-wire serial data ta[7:0]=8’h13, brake1[7:0]=8’h03, tb[7:0]=8’h1e, brake2[7:0]=8’h6b, osc[2:0]=3’h0 ※5 Output switching wave 90% 90% 100% Output voltage 10% 10% Tf 0% Tr ○2-wire serial interface specification (Fast mode : SCL=400kHz) Write mode : S Read mode : S 0 0 0 0 0 0 S=Start condition P=Stop condition 1 1 1 1 0 0 0 0 A PS T2 T1 T0 W3 W2 W1 W0 A D7 D6 D5 D4 D3 D2 D1 D0 A P ↑ ↑ Write Up date 0 0 A PS T2 T1 T0 W3 W2 W1 W0 A S 0 0 0 1 1 ↑ Write A=Acknowledge PS=Power save W3～W0=Resister address ｎA=not Acknowledge T2～T0=Test bit D7～D0=Data REV. A 0 0 Master is output Slave is output 1 A D7 D6 D5 D4 D3 D2 D1 D0 nA P ↑ Read 3/4 ○Characteristics of the SDA and SCL bus lines for 2-wire serial interface. (Unless otherwise specified, Ta=-25～+85°C, VCC=2.3～3.6V ) Parameter Symbol FAST-MODE※ Min. 6 STANDARD-MODE※ Typ. Max. Min. 6 Typ. Max. Unit SCL clock frequency fSCL - - 400 - - 100 kHz High period of the SCL clock tHIGH 0.6 - - 4.0 - - μs Low period of the SCL clock tLOW 1.3 - - 4.7 - - μs Rise time of SDA signal tR - - 0.3 - - 1.0 μs Fall time of SDA signal tF - - 0.3 - - 0.3 μs tHD:STA 0.6 - - 4.0 - - μs Set-up time (repeated) START condition tSU:STA 0.6 - - 4.7 - - μs Data hold time tHD:DAT 0 - 0.9 0 - 3.45 μs Data set-up time tSU:DAT 100 - - 250 - - ns Set-up time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes which must be suppressed by the input filter tSU:STO 0.6 - - 4.0 - - μs tBUF 1.3 - - 4.7 - - μs tI 0 - 50 0 - 50 ns Hold time (repeated) START condition ※6 Standard-mode and Fast-mode 2-wire serial interface devices must be able to transmit or receive at that speed. The maximum bit transfer rates of 100 kbit/s for Standard-mode devices and 400 kbit/s for Fast-mode devices This transfer rates is provided the maximum transfer rates, for example it is able to drive 100 kbit/s of clocks with Fast-mode. ○Definition of timing on the 2-wire serial interface tHIGH tF tR SCL SCL tSU : DAT tHD : STA tHD : DAT tLOW tSU : STA tSU : STO tHD : STA SDA SDA tBUF Fig.1 Definition of timing for serial data Fig.2 Definition of timing for START and STOP bit ○Package outline ○Pin Arrangement（Top View） 1PIN MARK 1.0±0.05 STOP BIT START BIT 1 2 3 4 A VM OUTB SCL SDA B OUTA GND VCC PS AAU Top View Lot No. (φ0.15) INDEX POST 0.225±0.05 P=0.5×3 0.25±0.05 φ0.25±0.1 Fig4. BH6456GUL Pin Arrangement (Top View) ○Block Diagram Side View P=0.5×1 0.1±0.05 0.55MAX 1.95±0.05 VCC SDA 4A SCL 3A 2-wire Serial Interface TSD UVLO 3B Band Gap VREG 1A VM Bottom View PS Pre Driver 4B Controller 1B OUTA H Bridge 15MHz OSC 2A OUTB 2B GND Fig5. BH6456GUL Block Diagram Fig3. VCSP50L1 Package (Unit；mm) REV. A 4/4 ○Resister map Address W3 W2 W1 W0 D7 D6 D5 D4 D3 D2 D1 0H 0 0 0 0 HiZE initB[2] initB[1] 1H 0 0 0 1 ta[7] ta[6] ta[5] 2H 0 0 1 0 brake1[7] brake1[6] 3H 0 0 1 1 tb[7] tb[6] 4H 0 1 0 0 brake2[7] 5H 0 1 0 1 cnt[7] 6H 0 1 1 0 7H 0 1 1 1 8H 1 0 0 9H 1 0 0 AH 1 0 BH 1 0 CH 1 1 D０ InitB[0] init START MODE dir ta[4] ta[3] ta[2] ta[1] ta[0] brake1[5] brake1[4] brake1[3] brake1[2] brake1[1] brake1[0] tb[5] tb[4] tb[3] tb[2] tb[1] tb[0] brake2[6] brake2[5] brake2[4] brake2[3] brake2[2] brake2[1] brake2[0] cnt[6] cnt[5] cnt[4] cnt[3] cnt[2] cnt[1] cnt[0] cnt[15] cnt[14] cnt[13] cnt[12] cnt[11] cnt[10] cnt[9] cnt[8] pa pb osc[2] osc[1] osc[0] cntck[2] cntck[1] cntck[0] 0 TEST TEST TEST TEST TEST TEST TEST TEST 1 TEST TEST TEST TEST TEST TEST TEST TEST 1 0 TEST TEST TEST TEST TEST TEST EXT initEXT 1 1 TEST TEST TEST TEST TEST TEST TEST TEST 0 0 TEST TEST TEST TEST TEST TEST TEST TEST * A low signal should be input to the TEST bit at all times ○Operation Notes (1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range (Topr) may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. The implementation of a physical safety measure such as a fuse should be considered when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. (2) Power supply lines Regenerated current may flow as a result of the inductance of printed circuit board. Insert capacitors between the power supply and ground pins to serve as a route for regenerated current. Determine the capacitance in full consideration of all the characteristics of the electrolytic capacitor, because the electrolytic capacitor may loose some capacitance at low temperatures. If the connected power supply does not have sufficient current absorption capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a physical safety measure such as the insertion of a voltage clamp diode between the power supply and ground pins. (3) Ground potential Ensure a minimum GND pin potential in all operating conditions. (4) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. (5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. (6) ASO When using the IC, set that it does not exceed absolute maximum ratings or ASO. (7) Thermal shutdown circuit This IC incorporates a thermal shutdown circuit (TSD). If the temperature of the chip reaches the following temperature, the motor output will be opened. TSD is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. (8) TSD ON temperature [°C] (Typ.) Hysteresis temperature [°C] (Typ.) 150 20 PS terminal Release PS after rising VCC. PS works resetting logic as well. If keep connecting PS with VCC, resetting cannot be done cause misoperating or destroy. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. 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