1/4 ◆Structure Silicon monolithic integrated circuit ◆Product Single Channel 16-bit CIS/CCD Analog Front End ◆Type BU6574FV ◆Features ・Correlated double sampling (CDS) ・Programmable gain amplifier (8bit resolution) ・16bit 6MSPS ADC ・Serial control interface ・Offset calibration DAC (8bit resolution) ・Internally generated voltage references ・4bit wide multiplexed data output format ◆Absolute maximum ratings (Ta=25℃) Parameter Symbol Supply voltage 1 VAVDD Supply voltage 2 VDVDD I/O supply voltage VVDDIO Digital input voltage *1 VID Digital output voltage *2 VOD Analog input voltage *3 VIA Analog output voltage *4 VOA Storage temperature Tstg Power dissipation *5 Pd Ratings -0.2 to 4.0 -0.2 to 4.0 -0.2 to 4.0 -0.2 to VVDDIO + 0.3 -0.2 to VVDDIO + 0.3 -0.2 to VAVDD + 0.3 -0.2 to VAVDD + 0.3 -25 to 125 400 *1 : Pin No.3,4,6,8,9 *2 : Pin No.10,11,12,13 *3 : Pin No.20 *5 : Reduced by 4mW for each increase in Ta of 1℃ over 25℃ ◆Operating conditions (Ta = 0℃ to 70℃) Parameter Symbol Supply voltage 1 VAVDD Supply voltage 2 VDVDD I/O supply voltage VVDDIO MIN 3.135 3.135 3.0 *4 : Pin No.16,17,18,19 TYP 3.3 3.3 3.3 This product is not designed for protection against radioactive rays Status of this document The Japanese version of this document is the formal specification. A customer may use this translation version only for a reference to help reading the formal version. If there are any differences in translation version of this document, formal version takes priority. REV. A Unit V V V V V V V ℃ mW MAX 3.465 3.465 3.6 Unit V V V 2/4 ◆Electrical characteristics (Unless otherwise noted, VAVDD=VDVDD=VVDDIO = 3.3V, Ta = 25℃) Parameter Symbol Overall System Specification Input signal limits VIN Conversion Rate RATE Digital Inputs High level input voltage VIH Low level input voltage VIL High level input current IIH Low level input current IIL Digital Outputs High level output voltage VOH Low level output voltage VOL Supply Currents Total supply current ITOTAL active Total Analog AVDD, IAVDD Supply current - active Total digital DVDD, IDVDD Supply current - active Total digital I/O, IVDDIO Supply current - active Supply current – full IPD power down mode MIN TYP MAX Unit 0.26 - - 2.7 6 V MSPS 0.7*VVDDIO - - 0.2*VVDDIO 1 1 V V uA uA VVDDIO-0.5 - - 0.5 V V 70 mA 50 mA 10 mA 10 mA 60 uA 35.7 41.7 32 34 1.5 3.0 2.2 4.4 - 30 REV. A Conditions IOH = 1mA IOL = 1mA MCLK = 12MHz MCLK = 24MHz MCLK = 12MHz MCLK = 24MHz MCLK = 12MHz MCLK = 24MHz MCLK = 12MHz MCLK = 24MHz MCLK=Low 3/4 ◆Package outline Product BU6574 Lot No. 1PIN MARK SSOP-B20 (Unit:mm) ◆Pin description ◆Block diagram AVDD 14 AGND 1 AGND VIN VSMP MCLK 3 4 17 BANDGAP REFERENCE TIMING CONTROL CM 16 CN 13 B[3]/SDO 12 B[2] 11 B[1] 10 B[0] 15 20 RLC CDS PGA L A T C H 16-bit ADC OFFSET DAC 19 8 8 VRLC/VBIAS RLCDAC CONTROL REGISTER DIGITAL INTERFACE 6 9 SEN SCK 8 SDI 2 7 5 DVDD VDDIO DGND REV. A CP 18 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name AGND DVDD VSMP MCLK DGND SEN VDDIO SDI SCK B[0] B[1] B[2] B[3]/SDO AVDD AGND CN CP CM VRLC/VBIAS VIN 4/4 ●Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Power supply and GND line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. Pay attention to the interference by common impedance of layout pattern when there are plural power supplies and GND lines. Especially, when there are GND pattern for small signal and GND pattern for large current included the external circuits, separate each GND pattern. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (4) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (5) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (6) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. REV. 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