1/4 Structure Silicon Monolithic IC Products High side switch IC Type BD82065FVJ Features Low on resistance 70mΩ MOSFET Switch 1A Continuous current load Active “High” control logic Soft start circuit Over current detection Thermal shutdown Under voltage lockout Open drain error flag output Reverse-current protection when power switch off TSSOP-B8J Package ESD protection ◇Absolute maximum ratings (Ta=25°C) Parameter Symbol Rating Unit Supply voltage VIN -0.3 ~ 6.0 V Enable voltage VEN -0.3 ~ 6.0 V /OC voltage V/OC -0.3 ~ 6.0 V /OC sink current IS/OC ~ 5 mA OUT voltage VOUT -0.3 ~ 6.0 V Storage temperature TSTG -55 ~ 150 °C *1 Power dissipation PD 587.5 *1 Mounted on 70mm*70mm*1.6mm glass-epoxy PCB. Derating : 4.7mW/°C above Ta=25°C. ＊ This product is not designed for protection against radioactive rays. mW ◇Operating conditions Parameter Symbol Min. Typ. Max. Unit VIN 2.7 - 5.5 V Operating temperature TOPR -40 - 85 °C Continuous output current IOUT 0.0 - 1.0 A Operating voltage REV. A 2/4 ◇Electric characteristics Unless otherwise specified VIN = 5.0V, Ta = 25°C Parameter Symbol Min. Typ. Max. Unit Condition Operating Current IDD - 110 160 μA VEN = 5V, VOUT = Open Standby Current ISTB - 0.01 1 μA VEN = 0V, VOUT = Open VEN 2.0 - - V High input VEN - - 0.8 V Low input IEN -1.0 0.01 1.0 μA VEN = 0V or 5V /OC output LOW voltage V/OC - - 0.5 V I/OC = 0.5mA /OC output leak current IL/OC - 0.01 1 μA V/OC = 5V /OC delay time T/OC 10 15 20 ms ON resistance RON - 70 110 mΩ Current Limit Threshold ITH 1.5 2.4 3.0 A Short-circuit current ISC 1.1 1.5 2.1 A Output rise time TON1 - 0.8 10 ms RL = 10Ω Output rise delay time TON2 - 1.1 20 ms RL = 10Ω Output fall time TOFF1 - 5 20 μs RL = 10Ω Output fall delay time TOFF2 - 10 40 μs RL = 10Ω Switch leak current ILSW - - 1.0 μA VEN = 0V, VOUT = 0V Reverse leak current ILREV - - 1.0 μA VOUT = 5.5V, VIN = 0V VTUVH 2.1 2.3 2.5 V Increasing VIN VTUVL 2.0 2.2 2.4 V Decreasing VIN Current consumption I/O EN input voltage EN input current Power switch IOUT = 500mA VOUT = 0V, CL = 47μF RMS UVLO UVLO Threshold ◇Measurement circuit ◇Timing chart at output rise / fall time TOFF1 TON1 VIN A VOUT IN RL GND CL 90% 10% 10% A OUT 90% TOFF2 IOUT TON2 VEN EN VEN /OC 50% REV. A 50% 3/4 ◇Block diagram OUT GND IN Charge Pump UVLO IN OUT OCD OUT Gate Logic /OC EN TSD ◇Pin description Pin No. Pin Name 1 GND 2,3 IN 4 EN 5 /OC 6,7,8 OUT Function Ground Power supply input. Input terminal to the power switch and power supply input terminal of the internal circuit. Enable input. Power switch on at High level. Over current output. Low level at over current, over temperature detection. Open drain output. Power switch output. ◇Package D 8 2 0 6 5 Lot No. TSSOP-B8J (Unit : mm) REV. A 4/4 ●Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Power supply and GND line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. Pay attention to the interference by common impedance of layout pattern when there are plural power supplies and GND lines. Especially, when there are GND pattern for small signal and GND pattern for large current included the external circuits, separate each GND pattern. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use a capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (3) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (4) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (5) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (6) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (7) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (8) Thermal shutdown circuit (TSD) When junction temperatures become 170°C (typ) or higher, the thermal shutdown circuit operates and turns a switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (9) Thermal design Perform thermal design in which there are adequate margins by taking into account the power dissipation (Pd) in actual states of use. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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