Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 U ULTRA- LOW ON O RES SISTANC CE, 6-A DUAL L LOAD SWITCH S WITH CON NTROLL LED TU URN-ON FEATUR RES DES SCRIPTIO ON ▓ Integrated dual chann nel load switcch The APE8990 A is a small, ultra-low RON dual load ▓ Input Volttage Range: 0.8V to 5.5V V switch h with conttrolled turn on. It con ntains two ▓ Ultra-low ON-Resista ance, RON = 20mΩ 2 per N-cha annel MOSFETs that can n operate ove er an input channel voltag ge range of 0.8V 0 to 5.5V and supportt maximum ▓ 6A Maxim mum Continu uous Currentt per channell contin nuous curren nt up to 6A e each. Each lo oad switch ▓ Low Thre eshold Contro ol Input is co ontrolled by an on/off input (ON), which is ▓ Adjustablle Rise Time e capab ble of interrfacing dire ectly with lo ow-voltage ▓ Quick Ou utput Discharrge Transisto or contro ol signals. ▓ Over-Tem mperature Prrotection Additional feature es include a 150Ω on-chip load ▓ RoHS Co ompliant and Halogen Fre ee Product resisttor for outpu ut quick disccharge when n switch is turned d off, in orde er to avoid inrush curren nt, the rise APPLICATIONS ▓ Telecom Systems ▓ Industriall Systems ▓ Set-Top-B Box ▓ Consume er Electronicss ▓ Notebookks / Netbooks time is i adjustable e by an exte ernal ceramic c capacitor on the e CTx pin. The APE8990 A is available in an ultra-sm mall, space saving 3mmx2mm m 14-pin DFN N package with w thermal pad. TYPICA AL APPLICATION +5V ON1 VIN1 VBIAS VOU UT1 VIN1 ON2 VIN2 VIN2 CIN22 RL1 APE8990 CIN1 VOUT1 COUT1 O VOU UT2 CT1 CT2 CT1 Data and speecifications suubject to changge without nottice GN ND VOUT2 RL2 COUT2 O CT2 1 20121106V1.0 2 0 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 ORDERING / PA ACKAGE INFORM MATION T Top View DFN 3x2-14L APE8990X X-HF Halogen n Free Produ uct Packag ge Type GN3B: DFN 3x2-14 L VIN1 1 14 VOUT1 VIN1 2 13 VOUT1 ON1 3 V VBIAS 4 Exposed E Pad ON2 5 11 GND 10 CT2 9 VOUT2 VIN2 6 VIN2 7 12 CT1 GND 8 VOUT2 ABSOLU UTE MAX XIMUM RATINGS R S (at TA=25°C C) VIN1, VIN2 2 -0.3V V to 6V VOUT1, VO OUT2 VIN+ +0.3V VON1, VON N2 -0.3V V to 6V VBIAS -0.3+6V IMAX 6A Storage Temperature Range R (TST) -65 to t +150°C Junction Te emperature (TJ) 150°°C Lead Temp perature (Soldering, 10se ec.) 260°°C Thermal Re esistance from Junction to t Ambient (R RθJA) DF FN-14L (3mm mX2mm) 65°C C/W RECOM MMENDED D OPERA ATING CONDITIO C ONS VIN1,2 0.8V V to 5.5V VBIAS 4.75 5V to 5.5V VON1,2 0V to 5.5V VOUT1,2 VIN1 1,2 CIN1,2 ≧4.7uF Operating Temperature T e Range -40°C to 85°C 2 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 ELECTR RICAL SP PECIFICA ATIONS (VIN1, 2=0.8 to 5.5V, VB BIAS=5V, TA =25°C, unle ess otherwise e specified) P PARAMETER R SYM TEST CO ONDITION MIN 1=VIN2=VON N1=VON2=5 5V VIN1 TYP MA AX UNIT 120 180 uA 1 uA Quiescent Current C IBIAS Shutdown Current C ISD ON Resistance (each sw witch) (Note1) RON VON Nx=VBIAS=5V, IOUTx=1A A 20 26 2 mΩ Output Pull Down Resisstance RON VBIA AS=5V, VONx=0V 150 250 Ω ONx Input Leakage L Currrent ION VON Nx=5V or GND 1 uA ONx Logic High H VIH Switch on ONx Logic Low L VIL Switch off Thermal Shutdown Thre eshold TSD 150 °C THYS Hystteresis 30 °C (Note1) IOUT T1=IOUT2=0 0A N1=VON2=GND, VON VOU UT1=VOUT2= =0 1.0 V 0.5 0 V Note1: Guarantee by de esign, not pro oduction testted. 3 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 PIN DES SCRIPTIO ONS PIN No. PIN SYMBOL 1, 2 V VIN1 C Channel 1 in nput, bypass this input with a ceramicc capacitor to o ground. 3 O ON1 C Channel 1 en nable contro ol input, active e high. Do no ot leave floatting. 4 VB BIAS 5 O ON2 C Channel 2 en nable contro ol input, active e high. Do no ot leave floatting. 6,7 V VIN2 C Channel 2 in nput, bypass this input with a ceramicc capacitor to o ground. 8,9 VO OUT2 10 C CT2 A capacitor to t ground sett the rise time of VOUT2. 11 G GND G Ground. 12 C CT1 A capacitor to t ground sett the rise time of VOUT1. 13,14 VO OUT1 PIN DESC CRIPTION 5 bias volta 5V age. C Channel 2 ou utput. C Channel 1 ou utput. BLOCK DIAGRA AM VIN1 VBIAS VOUT1 Oscillator Charge Pump Output 1 D ischarge Control Logic VIN2 Thermal Protection VOUT2 ON1 ON2 Output 2 D ischarge GND CT T1 CT2 4 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS VBIAS=5V, Io=0A, CIN=1µF, = COUT=0 0.1µF, ch1:O ON1, ch2:VOU UT1, ch3:ON N2, ch4:VOU UT2 R V VIN=0.8V Fig.1 Turn-on Response, Fig.2 Turn-on T Resp ponse, VIN=1.2V R V VIN=1.5V Fig.3 Turn-on Response, Fig.4 Turn-on T Resp ponse, VIN=1.8V 5 Turn-on Response, R V VIN=3.3V Fig.5 Fig.6 Turn-on T Resp ponse, VIN=5.0V 5 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS (C Continued d) VBIAS=5V, Io=0A, CIN=1µF, = COUT=0 0.1µF, ch1:O ON1, ch2:VOU UT1, ch3:ON N2, ch4:VOU UT2 R V VIN=0.8V Fig.7 Turn-off Response, Fig.8 Turn-off T Resp ponse, VIN=1.2V 9 Turn-off Response, R V VIN=1.5V Fig.9 Fig.10 Turn-off Ressponse, VIN= =1.8V Fig.1 11 Turn-off Response, VIN=3.3V V =5.0V Fig.12 Turn-off Ressponse, VIN= 6 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS (C Continued d) 1800 260 VOUT Rise Time (us) Turn-on Delay Time (us) CT=1nF 1600 230 CT=1nF 200 CT=0.47nF 170 CT=0.22nF 140 110 CT=0.47nF CT=0.22nF 1400 1200 1000 80 800 600 400 200 VB BIAB=5V, Cout= =0.1uF, Io=0A 50 0.8 1.4 2.0 2.6 3.2 VIN (V) 3 3.8 4.4 VBIAB= =5V, Cout=0.1uF F, Io=0A 0 0.8 5.0 Fig.13 tD-ON vs. VIN N 2.6 3.2 V (V) VIN 3.8 4.4 5.0 400 CT=1nF 0.9 CT=0.47 7nF 0.8 350 CT=0.22 2nF VOUT Fall Time (us) Turn-off Delay Time (us) 2.0 Fig.14 tR vs. VIN 1.0 0.7 0.6 0.5 0.4 0.3 0.2 300 250 200 150 0.1 VB BIAB=5V, Cout= =0.1uF, Io=0A 0.0 0.8 1.4 2.0 2.6 3.2 VIN (V) 3 3.8 4.4 VBIAB= =5V, Cout=0.1uF F, Io=0A 100 5.0 0 0.8 N Fig.15 tD-OFF vs. VIN 1.4 2.0 2.6 3.2 V (V) VIN 3.8 4.4 5.0 Fig.16 tF vs. VIN 1.0 140 0.9 120 0.8 100 0.7 80 VON (V) IBIAS (uA) 1.4 60 0.6 0.5 0.4 0.3 40 0.2 20 VBIAS=5V 0 VON-L 0.0 0 0 -20 -40 VON-H 0.1 2 20 40 60 TJ (°C) 80 100 120 0 Fig.17 Quiescent Current vs. Temperature T -40 -20 0 2 20 40 TJ (°C) 60 6 80 Fig.18 ON O Threshold vs. Temperature 7 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 APPLICATION IN NFORMA ATION On/Off Con ntrol The load sw witch is conttrolled by the e ON pin. Th he ONx pin is i active high h and has a low thresho old making itt capable of interfacing with w low volta age signals. The ONx pin n can be use ed with standard 1.2V, 1.8V, 2.5V orr 3.3V GPIO logic thresho old. Do not le eave the ONxx pin float. The Figure1 19 show the VOUTx turn--on/off waveform. tD-ON: VOUT T turn on dela ay tR: VOUT risse time tD-OFF: VOUT T turn off dellay tF: VOUT fall time ON O 90% 90% 1 10% 10% VO OUT tD-ON tR tD-OFF tF Fig19 ON/OFF Wa aveform Output Rise Time Control me of each VOUTx V is adjustable by an a external capacitor on the t CTx pin. The rise tim me shows on n The rise tim below Table e 1 are typica al measured value. Pleasse refer it for determined rise time. CT (nF) R Rise Time, tR (µs),10%~90 0%, COUT=0.1µF,CIN=1uF F V VIN=0.8V V VIN=1.05V VIN=1.2V VIN=1.5V VIN=1.8V VIN=2.5V VIN=3.3V VIN=5V 0 27 31 34 38 40 48 59 75 0.22 72 93 107 131 158 220 284 418 0.47 126 159 178 233 280 400 520 776 1 250 327 378 485 584 780 1045 1657 2.2 509 725 827 1027 1235 1777 2391 3593 4.7 1012 1387 1699 1898 2269 3451 4670 7418 10 2008 2865 3425 4328 5203 7491 10142 15409 <Table 1> 8 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 APPLICATION IN NFORMA ATION (Continued)) Input Capa acitor An input cap pacitor is reccommended to be placed d between VINx and GND D to limit the vvoltage drop on the inputt supply durin ng high curre ent applicatio on. Output Cap pacitor Setting a CIN greater th han the COUTT is highly re ecommended d. Since the internal bod dy diode is in n the NMOS S switch, this prevents the e current flow ws through th he body diode e from VOUT Tx to VINx when the syste em supply iss removed. Layout Con nsiderations s The Figure 20 shows the reference layout for AP PE8990. Belo ow lists help start layout. 1. The currrent loop of two load swiitch should be b separated and symme etrized to eacch other. 2. Keep th he high curre ent paths (VIN N, VOUT and d GND; blue circle) wide and short to o obtain the best b effect. 3. The inp put and outpu ut capacitorss should be close c to the device d as po ossible to min nimize the pa arasitic trace e inductances. 4. Place th he thermal vias under the e exposed pa ad of the dev vice (green circle). c This h help for therm mal diffusion n away fro om the devicce. Fig20 APE E8990 Referrence Layoutt 9 Advanc A ced Pow wer E Electron nics Co orp. AP PE8990 MARKIN NG INFORMATION DFN 3x2-14 4L 8 8990 YW WWS Part Numb ber Date Code e (YWWS) Y:Year WW ：Week S ： Sequenc ce 100