Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 2M MHz, 3A Synchrronous Step Do own Converterr FEATUR RES DES SCRIPTIO ON Two 50m mΩ (typical) MOSFETs M forr High The APE1543 A is a synchronou us step down n converter Efficiencyy at 3A Load ds designed with in ntegrated MO OSFETs. Th he current 200kHz to t 2MHz Switching Frequ uency mode e PWM DC//DC converte er decrease es external 0.803V ± 1% Voltage e Reference comp ponent coun nts and up to 2MHz switching Synchron nizes to Exte ernal Clock frrom 300kHz to t freque ency also red duces the ind ductor size. 2MHz The APE1543 integrates 5 50mΩ MOS SFET and Adjustable Slow Startt/Sequencing g 500µA A operation current to m maximize the efficiency. UV and OV O Power Go ood Output The 1% high acccurate of re eference voltage over Low Ope erating and Shutdown S Qu uiescent tempe erature proviides well load regulation.. APE1543 Current works s in dual op perating mod des. PSM mode m is for Cycle by Cycle Curre ent Limit, The ermal and high efficiency e in light loading. PWM mode e is for low Frequenccy Fold Backk Protection noise operation. RoHS Co ompliant and d 100% Lead d (Pb)-Free The soft start tim me is adjusstable by an external capac citor at SS pin. p The UVLO threshold d is set at APPLICATIONS DSPs, FP PGAs, ASIC,, and Microprocessors I/O Supp plies and 2.6V internally, can be increase by a programmable ressistor at the EN pin. The e APE1543 also features f the frequency ffold back an nd thermal System Power Supplies shutd down to protect the device ag gainst the over-c current fault condition. TYPICA AL APPLICATION APE E1543 CB VIN Cin 10uF VIN BOOT VIN LX 0.1uF R3 L1 1uH H R4 Cc 2. 7nF Rc 7.5k RT 180k Css s VIN LX EN LX COMP PGND RT/CLK PGND SS VOUT=1.8V Cout 22uF*2 R1 12. 5k CF 100pF R2 10k FB 10nF F GND Data and speecifications suubject to changge without nottice PGD RPG 100k PGOOD VIN 1 20120418V1.00 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 ORDERING / PA ACKAGE INFORM MATION Top View w QFN 3x3-16L APE154 43 X 2 PGND 3 PGND 4 BOOT VIN PGD 1 EN VIN VIN Packag ge Type VN3 : QFN Q 3x3-16L L 16 15 4 14 13 Exposed d Pad PG GND 5 6 7 8 12 LX 11 L LX 10 LX 9 SS GND FB COMP CO RT/CLK ABSOLU UTE MAX XIMUM RATINGS R S (at TA=25°C C) VIN -0.3V V to 6V EN -0.3V V to 6V LX -0.3V V to 6V BOOT LX+6V RT/CLK -0.3V V to 6V FB, SS -0.3V V to 6V PGD -0.3V V to 6V PGD Sink Current C 10m mA GND, PGND -0.3V V to 0.3V Storage Temperature Range R (TST) -65 to t +150°C Junction Te emperature (TJ) 150°°C Lead Temp perature (Soldering, 10se ec.) 260°°C Thermal Re esistance from Junction to t Ambient (R RθJA) QFN 3x3-16L 60°C C/W RECOM MMENDED D OPERA ATING CONDITIO C ONS VIN 2.95 5V to 6V EN -0.3V V to 6V LX -0.3V V to 6V Operating Temperature T e Range -40°C to 85°C 2 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 ELECTR RICAL SP PECIFICA ATIONS (VIN=2.95 to t 6V, TA =25 5°C, unless otherwise o spe ecified) PAR RAMETER SYM M TEST CONDITION MIN TYP MAX M UNIT 6 V 2.8 2 V Input Operation Voltage V Rang ge Under Volta age Lockout Threshold VIN UVLO O 2.95 Rising 2.6 hysteresiss 200 mV 500 µA 3 µA Rising 1.25 V Falling 1.18 V VEN + 50m mV -3.2 µA VEN - 50m mV -0.65 µA Quiescent Current C IQ VIN=5V, VFB=0.9V, RT T=400kΩ Shutdown Current C ISD EN=0V, 0.95V≦VIN≦ 0 ≦6V EN Thresho old VEN EN Input Cu urrent IEN Reference Voltage V VFB VIN=2.95 5 to 6V 0.795 0.803 0..811 V Controller High Side Switch S Resistance (Note1) Low Side Sw witch Resista ance (Note1) Switching Current C Limit RDRVHH RDRVLL BOOT-LX X=5V 50 mΩ BOOT-LX X=2.95V 64 mΩ VIN=5V 50 mΩ VIN=2.95V V 64 mΩ ILM A 5 LX Rise/Fall Time (Note1) VIN=5V 1.5 V/ns BOOT Charrge Resistance VIN=5V 16 Ω 7 nA ICOMP = ± 2µA, VCOMP=1V = 225 µA/V VCOMP=1V V, 0.1V overd drive ±20 µA 13 A/V Error Ampllifier COMP Leakkage Currentt EA Transconductance (NNote1) gmEAA COMP Sinkk/Source Currrent Current Sen nse to COMP P Transcondu uctance (Note1)) gmCSS 3 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 ELECTR RICAL SP PECIFICA ATIONS (Continueed) (TA =25 ºC, unless otherrwise specifie ed) PAR RAMETER TEST CONDITION SYM M MIN TYP MAX M UNIT Resistor Timing and External Cloc ck (RT/CLK)) Switching Frequency Ra ange Switching Frequency fsw RT mode 200 2000 kHz CLK mod de 300 2000 kHz RT=400kkΩ 400 600 6 kHz 500 Minimum CL LK ON Time TCLK_M MIN 75 ns RT/CLK Voltage VRT/CLLK RT=400kkΩ 0.5 V High RT/CLK Thrreshold 2.2 V 0.4 0 Low Delay Time (Note1) tD RT/CLK falling f to LX rising r edge, V 150 ns 1.8 µA 20 mA 20 µA VFB-R1 Rising 93 %VFB VFB-F11 Falling 105 %VFB VFB-R22 Rising 91 %VFB VFB-F22 Falling 107 %VFB VFB=VREF, VPGD=5.5V 0.1 µA 10 Ω IPGD=3.5m mA 0.3 V VPGD<0.5V V at 100µA 1.2 V fsw=500kkHz, with RT resistor Soft Start (SS) SS Charge Current ISS Vss=0.4V V UVLO, EN N, Tthermal fault, SS Discharg ge Current ISS-D VIN=5V, Vss=0.5V V Over-currrent, VFB=0V V Power Goo od (PGD) FB Thresho old (Good) FB Thresho old (Fault) PGD Leakage Current IPGD PGD On Re esistance (Notee1) RPGDD PGD Output Low Minimum VIIN for Valid PGD P Output Thermal Sh hutdown Thermal Shutdown Threshold (NNote1) TSD Hysteresiis 150 o 20 o C C Note1: Guarantee by de esign, not pro oduction testted. 4 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 PIN DES SCRIPTIO ONS PIN No. PIN SYMBOL 1, 2, 16 V VIN 3, 4 PG GND P Power groun nd. 5 G GND A Analog groun nd. 6 F FB 7 CO OMP 8 RT T/CLK 9 S SS S Soft-start pin n. Connect an n external ca apacitor to ad djust the outp put rise time.. 10, 11, 12 2 L LX S Switching no ode. 13 BO OOT 14 P PGD 15 E EN 17 Expos sed pad PIN DESC CRIPTION I Input supply voltage from m 2.95V to 6V V. O Output feedb back pin. C Compensatio on pin. Conn nect frequenccy compensa ation components at thiss p pin. R Resistor timing or external clock inpu ut pin. S Supply inputt for internal high-side N--MOSFET ga ate drive (bo oot terminal).. C Connect a bo ootstrap cap pacitor from this pin to LX X node. P Power good output pin. PGD is an open-drain o output. Pull up to VIN raill w a pull-up with p resistor. E Enable pin, internal pull-u up current so ource. C Connect to power p ground d directly. 5 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 BLOCK DIAGRA AM PGD D EN VIN 0.6uA Shutdown Shutdown + + 93% Logic 1.25V Shutdown Logic - 0.803V 1.8uA Thermal Shutdown + A 2.55uA 107% UVLO Boot Charge BOOT COMP FB SS + + + Logic and P PWM Latch h LX Over -Current Recovery Maximum Clamp + Slope on Compensatio Frequen ncy Shift Shutdown GND PGND Current Sens se Oscillattor RT/CL LK 6 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS EN EN E VLX VLX VOUT VOUT PGD PGD ILX ILX L F Fig.1 Enable, 5Vi to 1.8V Vo/0A Fig.2 Enable, 5V Vi to 1.8Vo/3 3A EN EN E VLX VLX VOUT VOUT PGD PGD ILX ILX L Fig.1 Enable e, 3.3Vi to 1.8 8Vo/0A 3Vi to 1.8Vo/3A Fig.2 Enable, 3.3 VLX VLX VOUT, 100 0mV/div VOUT, 100mV//div IOUT, 0~3A A IOUT O , 0~3A 5 Load Tran nsient, Vin=5 5V, Vo=1.8V Fig.5 oad Transientt, Vin=3.3V, Vo=1.8V V Fig.6 Lo 7 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS (C Continued d) VOSC VOSC VLX VLX Fig.7 External E PWM M at RT pin, fosc=300kHz VLX VOUT ILX Fig.9 Output O Ripple e, Vin=5V, Vo o=1.8V, Io=0A A VLX VOUT ILX Fig.11 Output O Ripple e, Vin=5V, Vo o=1.8V, Io=3 3A Fig.8 Exte ernal PWM at RT pin, fosc=2MHz VLX VOUT ILX Fig g.10 Outpu ut Ripple, Vin n=3.3V, Vo=1 1.8V, Io=0A VLX VOUT ILX Fig g.12 Outpu ut Ripple, Vin n=3.3V, Vo=1 1.8V, Io=3A 8 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS (C Continued d) 100 90 0.9V Vo,1MHz 90 80 80 70 70 Efficiency (%) Efficiency (%) 100 1.8Vo,1MHz 60 50 40 30 20 60 50 40 30 20 Vin=5V 10 Vin=5V 10 Vin=3.3V 0 Vin=3.3V 0 1 10 100 Io (mA) 1 1000 10 F Fig.13 Efficciency for Vo= =1.8V 2.0 VIH 2.9 2.8 1.6 2.7 1.4 2.6 1.2 2.5 2.4 VENH 1.8 VIL VEN (V) Vin (V) 1000 1 Fig.1 14 Efficienccy for Vo=0.9 9 3.0 VENL 1.0 0.8 2.3 0.6 2.2 0.4 2.1 0.2 2.0 0.0 -40 -20 0 20 40 Tc (℃) 60 -40 80 Fig.15 UVLO Thrreshold vs. Temperature Te 10 0.85 9 0.84 8 0.83 7 0.82 6 0.81 5 0.79 3 0.78 2 0.77 Vin=5V 0 0 20 0 40 TJ (℃) 60 0 80 Vin=5 5V,1MHz 0.80 4 1 -2 20 Fig.16 EN E Threshold d vs. Temperature VFB (V) ISD (uA) 100 Io (mA) 0.76 0.75 -40 -20 0 20 40 TJ (℃) 60 80 T Fig.17 Shutdown Current vs. Temperature -40 -2 20 0 20 TJ((℃) 40 60 0 80 Fig.18 Feedback Volta age vs. Temp perature 9 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 TYPICA AL PERFO ORMANC CE CHAR RACTERISTICS (C Continued d) 1200 2200 2 Vin=5V, Vo=1.8V, Io=2A, RT= =180kΩ 2000 2 1150 1800 1600 1400 1200 fsw (kHz) fsw (kHz) 1100 1050 1000 1000 800 600 400 950 200 900 0 -40 0 -20 0 20 40 TJ (℃) 60 80 0 200 400 600 RT(kΩ) 800 1000 Fig.19 Switching Frequency F vss. Temperature Fig.20 Switching Frequ uency vs. RT T resistor 1.82 0.95 Vin=5V 1.81 Vin=3.3V 1.80 Vin=5V V 0.94 Vin=3.3V V 0.93 0.92 1.78 0.91 Vo (V) Vo (V) 1.79 1.77 0.90 1.76 0.89 1.75 0.88 1.74 0.87 1.73 0.86 1.8Vo, 1MHz 1.72 0.9V Vo, 1MHz 0.85 0 500 1000 0 1500 2000 0 Io (mA) 2500 0 3000 0 Fig.21 Lo oad Regulatiion 50 00 1000 15 500 2000 Io (mA) 25 500 3000 Fig.22 Load Regulation 0.95 1.81 0.94 1.80 0.93 1.79 0.92 1.78 0.91 Vo (V) Vo (V) 1.82 1.77 0.90 1.76 0.89 1.75 0.88 1.74 0.87 0A 1.73 0A 0.86 2A 1.72 2A 0.85 3 3.5 4 4.5 Vin (V) Fig.23 Line L Regulation 5 5.5 3 3.5 4 4.5 Vin n (V) 5 5.5 Regulation Fiig.24 Line R 100 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 APPLICATION IN NFORMA ATION The APE15 543 is design ned in low no oise, adjusta able fixed frequency, and d current mod de PWM con ntrol. At lightt load conditiion, the APE E1543 opera ates in powe er save, puls se-skip mode e (PSM) which blanks th he ON pulse e automatically to mainta ain high efficciency. In PSM, the inte ernal Zero-C Cross compa arator looks for inductorr current. Wh hen zero current is deteccted, the con nverter enters PSM and turns low-sid de MOSFET off on each h cycle. When n the outputt load curren nt increases from light lo oad to heavyy load, the in nductor curre ent does nott cross zero and reachess to the conttinuous cond duction. The transition loa ad point betw ween discon ntinuous and d continuous conduction mode, m IOUT(LBB), can be callculated by: IOUT (LB ) = _ ( VIN 1 N VOUT ) × VOUT O 2 × L × f sw VIN Under-Volttage Lockou ut The APE15 543 has VIN under-voltag ge lockout prrotection (UV VLO). This iss a non-latch hed protection. When the e VIN voltage e is lower th han 2.6V, the e APE1543 is off. If hig gher UVLO iss needed, u use EN pin as a TYPICAL L APPLICATION circuit to o adjust the UVLO U thresh hold by using two externa al resistors, R R3 and R4. When W the EN N pin floats, the t internal 0.6µA curre ent source provides p the APE1543 default d opera ation. If the EN voltage e exceeds 1.2 25V, an add ditional 2.55µA hysteressis current is s added. If the t EN volta age is below w 1.18V, the e hysteresis current c is rem moved. R3 R4 0.944 VUVLO VUVLO H VUVLO 2.58 10 L L 1.18 R3 1.18 R R3 3.15 1 10 The UVLO has two thre esholds, VUVVLO-H for pow wer up when the input vo oltage is risin ng and VUVLO r O-L for power down when the input vo oltage is fallin ng. Soft Start The APE1543 has an internal 1.8µA A current source which ch harges extern nal capacitor to implemen nt a soft startt time. When the EN pin voltage risess above the enable thres shold, the co onverter ente ers its start-up sequence.. The soft sta art time can be b calculated d by: t SS ms CSS nF VREEF V ISS µA CSS nF 0.803 V 1.8 µA Output Voltage Setting g The output voltage is ad djusted with a resistor divvider from the e output to th he FB pin. It can be calcu ulated as: VOUT 0.80 03V R1 R2 1 111 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 APPLICATION IN NFORMA ATION (Continued)) Power Goo od Output The APE1543 provides a power goo od (PGD) outtput, which is s an open-dra ain output requiring a pull-up resistor.. Typically co onnect to +5V V voltage sou urce or less through t a res sistor betwee en the valuess of 1kΩ and 100kΩ. The e PGD compa arator continuously monittors the FB voltage. v In sh hutdown and soft start perriod, PGD is actively low.. If the FB voltage rises above 93% orr falls below 105% of the internal reference voltag ge, the PGD is i high. If the e FB voltage falls below 91% or risess above 107 7% of the intternal reference voltage,, the PGD becomes b low w immediatelyy which enters the fault condition. Switch freq quency The switchin ng frequencyy is adjustable from 200kkHz to 2MHz by a preset resistor r conn nected to the e RT/CLK pin n. This pin is fixed f at 0.5V when using an external resistor to ground g to dettermine the sswitching freq quency. The e external ressistor, RT, is given as: RT kΩ 311890 kHz . fSW S The high sw witching frequ uency allowss lower value e inductor an nd smaller ou utput capacitor. Howeverr, the highestt switching frrequency causes more switching s losss. A moderrate switching frequencyy of 1MHz is s selected to o achieve botth a small solution size an nd a high effficiency operation. So tha at, RT is calcculated to be 180kΩ. Synchronizze The RT/CLK K pin is also used to syncchronize the converter to an external clock. Conne ect a square wave with a 75ns on tim me at least to o the RT/CLK K pin to determine the sy ynchronizatio on frequencyy ranging from m 300kHz to o 2MHz. The amplitude of o square wa ave must co onverse lowe er than 0.6V and higher than 1.6V. The internall LK pin is pulled above e the 1.6V threshold and the pin becomes a amplifier iss disabled iff the RT/CL synchroniza ation input. The T rising edg ge of the LX is synchroniized to the fa alling edge off external clo ock. Frequency Compensation The APE15 543 has the transconduc t ctance ampliffier with TypeⅡ compen nsation contrrol loop. Figu ure25 showss the small signal equivalent model for f the APE1 1543 control loop which can check ffrequency re esponse and d dynamic loa ad response. The APE1543 adds a compensatin ng ramp to the t switch cu urrent signal. This slope e compensation prevents sub-harmon nic oscillation ns when duty y cycle increa ases. Currrent Sense LX VOUT Co R1 RL FB COMP Cc EA VREF ESR R2 Rc Fig.25 Sim mple small signal s model 122 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 APPLICATION IN NFORMA ATION (Continued)) In Figure25 5, the error amplifier a is a transcondu uctance amp plifier with a gm of 225µ µA/V. The cu urrent sense e transconducctance with a gm of 13A A/V is the pro oportion of th he variation in i switch currrent and the e variation in n COMP pin voltage. v The small signal transfer funcction is dominated by a DC D gain and d developed by y a pole at fP and a zero at a fZ. GAIN f fZ gmCS C RL 1 2π RL COUT 1 2π fC fP R ESR COUT fZ Proper com mpensation of o the syste em is allowe ed for a calc culable band dwidth. The targeted co ompensation n network is to t provide th he closed loop transfer function f with h 0dB crosso over frequen ncy (fc, one tenth of fsw w typically) an nd sufficient phase marg gin (greater than 45°). As s the load cu urrent decrea ases, the ga ain increasess and the pole e frequency lowers to keep the same e 0dB crossover frequenccy for the varried load con nditions. The compen nsation netw work Rc, Cc can c take as following: f RC 2π fC VOUT COUT VREF gmEA gm mCS Choose the e compensa ation resistorr (Rc) to set the desired crossover frequency. f CC RL COUT RC Choose the e compensa ation capacitor (Cc) to acchieve the desired d phasse margin. Inductor Se election The inducto or value dete ermines the ripple r currentt and the ripp ple voltage of o the converrter. This inductor choice e provides tra ade-offs betw ween size vss. efficiency. Low inducto or values cau use large rip pple currents, resulting in n the smallesst size, but poor p efficienccy and high output noise e. The inducctor selection n is based on o the ripple e current whicch is typicallyy set betwee en 1/10 to 3/1 10 of the max ximum load current. c The switching fre equency and d ripple curren nt determine e the inductorr which can be b calculated d as follows: L= VOUT ( VIN _ VOUT ) ∆IL × fSW S × VIN The ripple current c can be b given by: ∆IL = VOUT ( VIN _ VOUT ) L × fSW × VIN 133 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 APPLICATION IN NFORMA ATION (Continued)) Output Cap pacitor Sele ection The output capacitor ne eeds to be selected s base ed on three consideratio ons, the outp put ripple, loa ad transient,, and the mod dulator pole. Below equa ation shows the t minimum m output capa acitance necessary to perform this. COUT 2 ∆IOUT fSW ∆VOUT The low ES SR ceramic capacitor is recommend ded. Low ES SR capacitors are prefe erred to keep p the outputt voltage ripp ple low. The output o voltag ge ripple can be estimated by: ∆VOUT ESR R⁄∆IL 144 Advanc A ced Pow wer E Electron nics Co orp. AP PE1543 MARKIN NG INFORMATION QFN 3x3-16 6L Part Numbe er Package Co ode 154 43VN3 YWW WSSS Date Code (YWWSSS) Y : Year WW : Week ence SSS : Seque 155