Ap pplication Notte PIC--014 February 2013 Design of Critic cal Cond duction Mode (C CRM) PF FC Circu uit with the t AOZ711 11 Introductio on This application note introduces the pra actical design n procedure. It includes how w to design th he inductor, select s the bulk capacito or, MOSFET, boost diode e, current sen nse resistance, Ct capacittor, the contro ol loop comp pensation network and so on. We im mplement a 39 95V, 160W, CRM C PFC converter using the AOZ7111 to verify the e design. The converte er exhibits fea atures such as a high PF, lo ow standby power p dissipa ation, high effficiency, and a robust protection. e mode active e power facto or correction controller c dessigned for cosst-effective bo oost PFC The AOZ7111 is a voltage application th hat operates in critical conduction mod de (CRM). Itss voltage mo ode scheme does d not nee ed an AC input line-sen nsing network k, which is ussually necessa ary for a curre ent mode CR RM PFC contrroller. Also, it receives a ZCD signa al pulse from m the currentt sense resisstor; thereforre, ZCD auxiiliary winding g is not need ded. The AOZ7111 is available a in a SO-8 packag ge. It provides ou utput over-voltage protection, over-current protection n, open-feedb back protectio on, and underr-voltage lockout prote ection. The un nique AC inpu ut fault detecttion circuit ma akes the system more robust during AC C absent test. The additional OVP pin can be used to double check the output volttage if the fe eedback resisstor gets damaged. Th he controller implements co omprehensive e safety featu ures for robusst designs. Basic Prin nciple of CR RM PFC Converter IL L Id Iin AC C POW ER DM CAPAC CITOR BULK K CAPCIT TOR AOZ 7111 Ids Rsense Figure 1. PFC Converter C witth AOZ7111 As shown in n Figure 1, the t PFC boo ost converterr requires a coil, a diode e and a pow wer switch. In n critical conduction mode, m the indu uctor current IL starts from m zero up to peak p current. If the turn-on n time (ton) is constant for a fixed tim me, the peak current will be b proportional to the inpu ut voltage as shown in Fig gure 2. The averaged a triangular currrent in each switching perriod is also prroportional to o the input volltage, thus the input curren nt drawn from the sourrce follows the input voltag ge waveform with w very high h accuracy. Rev. 1.0 www w.aosmd.com Pag ge 1 of 21 Applicatio on Note PIC-014 P IL Peak Inductor current Input ave erage current V GS T ON Figure 2. Waveforms W o Inductor Current of C and Driver D Design Pro ocedure A 160W PFC C application with w universa al input range e is selected as a a design example; e it sh hows users th he design procedure ste ep by step. D1 D2 L BD Vcc IC1 CM1 R28 CX2 Vcc C4 CX1 R14 R21 R15 R22 R16 R23 C11 C12 INV R9 COMP O OVP CS G GND C6 C5 R20 AOZ7111 R8 FL1 R19 R13 D3 O OUT Ct C3 + R12 CN C DC OUTPUT Q1 R26 Vo D7 C7 R11 C8 ZD3 17 R1 R24 R1 18 C9 R25 R27 C10 R5 R1 R2 R3 VAR FU NTC CN AC INPUT Figure 3. 3 AOZ7111 Evaluation E B Board Schem matic Rev. 1.0 www w.aosmd.com Pag ge 2 of 21 Applicatio on Note PIC-014 P STEP1-Defin ne the Speciffication The spec of the t converter is shown in the t table below. Minimum Input Voltage e Vac(min) = 90V Maximum m Input Voltage Vac(max) = 264V V Minimum Line L Frequenccy fline(min) = 47Hzz l Maximum Line L Frequency fline(max) = 63Hzz Nominal Output O Voltage Vout = 395V Output Ripple R Voltage e ∆V Vout(ripple) = 10V V Hold Up Time thold = 20ms Maximum Output Voltag ge Vout(max) = 440V V M Minimum Swiitching Frequency fsw(min) = 57kHzz s Full Load Output O Current Iout = 0.405A Full Load Output Powe er Pout = 160W Target Full Load Efficien ncy η = 95% M Minimum Full Load L Power Factor F PF = 0.95 STEP2-Powe er Stage Com mponent Selection 1. Powe er Inductor Se election The boost in nductor value e is determin ned by the output o powerr and the minimum switcching frequen ncy. It is calculated byy the equation n below: L Vac 2 1 2 fsw (min)) Pout 2 2 V ac Vout (e eq-1) Where L is th he boost inductance. The minimum m frequency occurs o at maxximum input voltage (Vac(m a full load condition c as shown s in max) = 264V) and Figure 4. Acccording to eq--1, the inducto or value is calculated as: L 1 2 60 10 0 3 160 264 2 0.95 2 2 264 395 189 H e value as 20 00µH. We select the Rev. 1.0 www w.aosmd.com Pag ge 3 of 21 Applicatio on Note PIC-014 P Figurre 4. Switch Frequency F v Input RMS vs. S Voltage (att sinusoid top) At minimum input voltage and maximu um output pow wer, the inductor peak currrent reachess the maximum, which causes the greatest stress s to the power componentss. The inducto or peak current is calculate ed by: ILpk 2 2 2 Pout Vacc 2 2 2 160 5.29 A 90 0 0.95 (e eq-2) Assuming EE ER3019NA co ore is selected d and setting B (max) as 0.23T, 0 the prim mary winding should be: Ninductror ILpk L Ae B(max) 5.29 200 H 1 .7mm 2 0.21 130 39Ts (e eq-3) The number of turns of th he boost indu uctor is deterrmined as 39 9. Figure 5 sh hows the app pearance of ER3019N E core and bob bbin (Ae = 130 0.7mm2, Aw = 81.8mm2). According A to th he typical B-H H characteristtics of ferrite core c from SAMWHA (P PL-7), the saturation flux density d decrea ases as the temperature increases, so the high tem mperature characteristiccs should be considered c (ssaturation flux x B (max) = 0.41mT @ 100 0deg). Figure 5. EER3019N E Fe errite Specific cations When Φ0.10 0mm × 50 (litz wire) is ussed, the RMS current of inductor coill, current den nsity and the e window coefficient arre: ILrms L 2 Pout 2 3 ILdensity L Rev. 1.0 Vac (min) 2.16 0.1 2 2 50 2 160 2 3 0.95 90 0 5.53 A mm 2 www w.aosmd.com 2.16 A (e eq-4) (e eq-5) Pag ge 4 of 21 Applicatio on Note PIC-014 P 0.12 50 N p 0.3 2 Naux 2 Aco 2 Aw 15.31 0.35 0.19 9 81.8 ws the windin ng of the inducctor: Figure 6 show E EER3019N 1,2 1,2 Np Np 3,4 3,4 Figure 6. Winding W the Inductor Winding speccification Pin N Np 3,4 4 1,2 Insulattion tape D Diameter Φ0.10m mm × 50 (litz wire) w 0.05mm Turns 39 3 Spec. 20 00µH (5%) Test conditio T on 100KHz,1V Test condition: Pin Inducctance 3,4 4 1,2 2. Bulk Capacitor Se election According to the ripple spe ecification of 10Vp-p, the ca apacitor should be: Cbulk 0.40 05 Iouut 129 9 F 2 fline(min)) Vout ( ripple ) 2 3.14 50 10 (e eq-6) According to the minimum m allowable output o voltage e 315V (0.8×Vout) during one o cycle line e (20ms) drop p-out, the ould be: capacitor sho Cbulk Pout thold 2 1 V 2 1 V out out (min) 2 2 160 20m 1 2 3952 1 2 3152 113 F (e eq-7) The output ca apacitor mustt be larger tha an 129µF, so the two electtrical capacito or (68µ/450V)) parallel are selected. s SFET and Outtput Diode Se election 3. MOS To begin, we e need to know w the voltage stress of the MOSFET: Vds (max) Voutt (max) Vd (maxx) 440 1.26 2 441.26V eq-8) (e Where Vds(max) is the maxim mum voltage stress of MO OSFET. Rev. 1.0 www w.aosmd.com Pag ge 5 of 21 Applicatio on Note PIC-014 P The Vd(max) iss the maximum forward vo oltage drop off output diode e. We can select AOS’s AOTF11C60 MOSFET, M its maximum Rds(on) is 0.4Ω Ω, maximum Coss (energy related) is 90 0pF at drain-source voltage e is 480V, Cexxt is zero. The output diode BYV29X X is selected, Vf(max) is 1.26V at 25°C, 8A A. The MOSFET T and Output Diode RMS current c are ca alculated as: 8 2 2 Vac (min) Ids( rm ms ) IL( rms ) 2 1 3 Vout 8 2 2 90 1.84 A 2 1 2 . 16 3 395 I 0.405 Id (ave ) out 0.42 26 A 0.95 (e eq-9) (e eq-10) The MOSFET T loss can be e divided into three parts: conduction c losss, turn-off losss, and turn-o on loss. Conduction lo oss can be ob btained as: 2 2 Pds(con ) Ids( rms r ) Rds (on ) 1.84 0.4 1.35W (e eq-11) Turn-off loss can be calculated as: Pds(off ) 1 V out 2 Iin( rms ) toff fsw (min) 1 395 1.87 50ns 57k 1.05W 2 (e eq-12) Where Iin(rms) is the input RMS R current, toff is the turn--off time and fsw(min) is the minimum m swittch frequencyy. Turn-on loss can be calculated as: Pds(on ) 1 2 2 1 Coss Cext Vout 2 fsw (m 9W min) 2 90 p 395 70 1000 0.49 (e eq-13) Coss is the output o capacittance of the MOSFET. Cext is an exte ernally added d capacitor att drain and source s of MOSFET. Th he total loss of o MOSFET iss: Pds ( total ) Pds ( con ) Pds ( off ) Pds (on ) 2.89W (e eq-14) The power lo oss of the outp put diode is calculated as: Pd ( loss ) Id ( avve ) Vf (max) 0.426 1.26 0.54W (e eq-15) 4. Curre ent-Sense Re esistor Selection and CS Circuit C Design The first role of Rcs is to set s shut down n mode over current c protecction level. Acccording to th he eq-2, the maximum m inductor curre ent is ILpk, and d sensing resiistor is calcula ated as: Rcs Vocp1 ILpk 0.7 0.132 5.29 (e eq-16) Choosing 0.1 1Ω as Rcs, pow wer loss is ca alculated as: Pr ( loss ) IL( rmss )2 Rcs 2.16 1 2 0.1W 0.47W (e eq-17) Recommend ded power ratiing of sensing g resistor is 2W. Rev. 1.0 www w.aosmd.com Pag ge 6 of 21 Applicatio on Note PIC-014 P STEP3-The CS C pin delay y time consta ant selection n The second role r of Rcs is detecting d the zero current point of the boost b inductorr. The negativve signal Vcs iss applied to the current sense pin. When W Vcs is higher h than th he threshold (-15mV), ( it means m the indu uctor current is nearly zero. In order to minimize the constantt turn-on time e deterioration n and turn-on loss, we sho ould trigger the gate at the drain sou urce voltage’s s valley point,, which may need n addition nal delay by the t external resistor r and capacitor. c The required delay time is s one-half of the resonant period; p approxximately: Rzcd Czcd 650ns 6 2 2 Ceff L 2 (e eq-18) Where Ceff iss the effectiv ve capacitor shown s at the e MOSFET drain d to sourcce; Czcd and Rzcd are the external capacitance and a resistor at a CS pin; "65 50ns" is the IC C internal set delay time. CH1: Driverr Voltage – CH2:: Vds (MOSFET’s s Drain and Dou urce Voltage) – CH3: Inductor Current C Figure 7. Realistic CRM C Wavefo orms with Rzccd and Czcd @230V/Full @ Lo oad The time bettween both do otted lines is the delay tim me. We can select s the app propriated Rzccd and Czcd to o achieve minimum dra ain voltage turrn-on. These values are found experime entally. STEP4-The Ct capacitor selection When the PF FC operates in i critical conduction mode e, a boost converter prese ents two phasses. During th he power switch condu uction time, th he current ram mps-up from zero z to the en nvelope level.. At that mom ment, the power switch turns off and the current ra amps-down to o zero. The maximum m on-ttime of the co ontroller occurrs when Vcompp is at the maximum. Th he Ct capacittor is sized to o ensure thatt the required d on-time is reached at ma aximum outp put power and the minim mum input vo oltage conditio on: L ILpk (t ) L 2 2 2Iin sin(t ) 2 L Iin Pout ton 2 2L 2 V 2Vac sin(t ) 2Vac s Vacc 2 ac a in (t ) (e eq-19) In regards to o the AOZ711 11; the on tim me was contrrolled with the capacitor connected c to the Ct pin. A current source charg ges the Ct cap pacitor to a vo oltage (Vct(off)) derived from COMP pin voltage. ton o Rev. 1.0 Ct Vct (ooff ) (e eq-20) Ichargerr www w.aosmd.com Pag ge 7 of 21 Applicatio on Note PIC-014 P Vct (off ) Vcompp Vct (offset ) 2 Pout L Icharger (e eq-21) Vac 2 Ct atasheet of AOZ7111, A we e have: Vct(m pical); Vct(offseet) = 1V (typical), Icharger = 250µA From the da max) = 8V (typ (maximum), then: t Ct(min) 2 Pout L Ichargger Vac Vcomp Vct (offset ) 2 2 160 1 200 250 0.95 90 2 8V p 260 pF (e eq-22) A value of 47 70p/50V proviides sufficientt margin. STEP5-FB, OVP, O and UV VP Divider Re esistors Sele ection Rfb1 and Rfb2 form a resisttor divider tha at scales dow wn Vout before e it is applied to the INV pin. The error amplifier adjusts the on-time o of the e drive to ma aintain the FB B pin voltage e equal to the e error amplifier reference e voltage (Vref). The divvider network k bias current (Ibias) selectio on is the first step in the ca alculation. The divider netw work bias current is selected to optim mize the trade e-off of noise immunity and d power dissip pation. Rfb1 iss calculated as: R fb1 3 V Vout 395 4.9M I bias 880A (e eq-23) A bias curren nt of 80µA pro ovides an accceptable trade-off of powe er dissipation to noise imm munity. A serie es of five resistors of 1MΩ/0805 are e selected. Vref Rfb1 2.5V 5M 31.85k Vout Vref 395 2.5V Rfb 2 (e eq-24) Rfb2 is selecte ed by a resisttor of 30K/080 05 and a resisstor of 1.8K/0 0805 which arre in series. Vout R fb1 R fb f 2 R fb 2 Vref 5M 31.8k 2.5 395.6V 31.8k eq-25) (e wo integrated d OVP circuitss to prevent the output fro om exceeding g a safe volta age. The The AOZ7111 includes tw s FB to the intternal comparrator’s referen nce (Vref1 = 2..685V) to dete ermine if an OVP O fault first OVP circcuit compares occurs. Vovp1 Rout 1 Rout 2 5M 31.8k Vref 1 2.685 425V Rout 2 31.8k (e eq-26) O circuit compares c the external new w resistor divid der (Rout3 and d Rout4) applie ed to pin 4’s reference r The second OVP (Vref2 = 2.75V V) to double check the output voltage e. Rovp1 is the e same as th he Rfb1. The Rovp2 is reselected as 24.9k/0805 and a 5.9k/0805 5 which are in series. Vovp 2 Rout 3 Rout 4 5M 30.8k Vref 2 2.75 449V Rouut 4 30.8k (eq-27) STEP6-Compensation Network Selec ction After designin ng the powerr componentss, we will help p the user dessign the control loop comp pensation nettwork. To find a compe ensation netw work, it is ne ecessary to get the contrrol loop mod del of this co onverter. Thiss can be synthesized as a shown in Figure F 8. Rev. 1.0 www w.aosmd.com Pag ge 8 of 21 Applicatio on Note PIC-014 P Viinrms Vref(s ) + mp(s) Ramp Contrrol Errror amplifier Vcom G Gcomp(s) G3(s) ton(s) PPWM modulator Illpk(s) G2(s) Power sttage G1(s)) Vout(s) ZCD Feedback H(s) Figure 8. Control C Loop of PFC 1. Powe er Stage We assume that t the contrrol action take es place on th he peak ampliitude of variou us quantities inside the loo op. The first step p is to determiine the transfe er function off power stage, defined as: G1(s ) dVout dVout dIouut dILpk dIout dILppk eq-28) (e uctor current, Iout is DC outp put current. Where Vout iss the DC output voltage, ILppk is the peak value of indu The power sttage can be modeled: m a co ontrol current source (with shunt resista ance Re) that drives the ou utput bulk capacitor Co and the loa ad resistance e RL (= Vout/IIout). The zero o due to ES SR associated d with Co is far from crossover fre equency thus it is neglected d. The current source s can be b characterizzed with the following f conssideration: the low frequen ncy compone ent of the boost diode current c is foun nd by averagiing the discha arge portion of o inductor current over a given g switch cycle. c Cout Id_avee Re Vout RLL Figure 9. Power P Stage Model and Boost B PFC Current C Rev. 1.0 www w.aosmd.com Pag ge 9 of 21 Applicatio on Note PIC-014 P The low frequ uency currentt averaged ovver a half-cycle yields the DC D output currrent Id(ave): Id ( avve ) 1 Ts Ts 1 0 2 2 2 Vin 2 Vin sin(t ) I ILppk sin(t ) dt Lpk k 2 Vouut 4 Vout (e eq-29) Where ILpk is the peak indu uctor current at ωt = π / 2. Vin is effectivve (RMS) inpu ut voltage. Therefore, we e can obtain the t transfer fu unction G1(s) of o Vout-to-ILpk: 1 2 Vout (s ) Id (ave )(s ) 1 G1(s ) Vout (s ) ILpk (s ) RL s 2 2 Vin ILpk (s ) 4 Vout RL Co 1 2 2 1 2 2 2 Vin 4 Vout 1 1 RL eq-30) (e s 2 RL Co RL (e eq-31) s 2 RL Co The transfer function G2(s) of ILpk-to-ton iss: G2(s ) ILpk (s ) ton (s ) 2 2 Vin L (e eq-32) Ct Icharger (e eq-33) The transfer function G3(s) of ton-to-Vcomp is: G3(s ) ton (s ) Vcomp(s ) an obtain the whole transfe er function Gpower(s) of Vout-tto-Vcomp: Finally, we ca p Gpow wer ( s ) Vout (s ) Vcompp(s ) G1(s ) G2(s ) G3(s ) Ct Icharger 2 Vin 1 i RL 4 Vout L 1 s Where Ct is 470pF, 4 Icharger is 200µA, Vouut is 395V, RL is full load (9 975Ω), Co is 136µF, 1 p Gpow wer ( s ) 470 10 12 200 12 2302 4 395 3 200 10 0 6 975 1 (e eq-34) p s 2 2 RLCo R . (e eq-35) 975 136 10 6 Calculated bo ode plot of tra ansfer function Gpower(s): Rev. 1.0 www w.aosmd.com Page 10 of 21 Applicatio on Note PIC-014 P 2. Compensation E/A A Transfer Fu unction The transfer function of E//A: Gcomp(s ) Vcoomp(s ) We can obtain that the zero is fcz Go Vout o (s ) Go 1 2 R1C1 1 1 s 1 s 2 fczz s 2 fcp p , the pole p is fcp 2 1 2 .5 1 Gm Vout C1 C2 2 1 (e eq-36) 1 C 1C 2 2 R1 C 1C 2 , the DC gain is calculated as: fcrfz 2 2 (e eq-37) fcr fp The Gm is the e transconduc ctance (100µS S) of the E/A.. 3. The Whole W Open Loop Transfe er Function Gwhoole(s ) Gpowerr (s ) Ct Icharger Vin 2 4 Vout L RL s 2 1 R C L o Go s 1 1 2 fz s 1 s (e eq-38) 2 fp dback Networrk implementa ation 4. Feed Desired crossover c freq quency: fcr = 15Hz Zero: fczz = 14.6Hz Pole: fcp p = 117Hz We know tha at when f fc on Gwhole ( j ) equals to 1, then Gwhole ( j ) 1, 2 fcr , cr , the functio p 2 RLCo Gwhole( j ) we can obtain: Ct Icharger Vi 2 RL in 4 Vout L 2 1 2 1 2pfcr 2 2 We know 2pfcr 1,C1C 2, so 2 1 2pfcr obtain as: Gwhole( j ) 2.38 10 6 1 2 fc Go 2 fcr , 1 p C1C 2 2 1 fcr 2 fz 2 2 1 fcr fp 1 eq-39) (e C11 substittute the numerical values, we can 1 2.5 115 10 6 2 2 395 C1 2 395 200 0 10 6 68 2 10 6 2 fcr 2 2302 (e eq-40) Series compe ensation capa acitor: C1 2.35 106 2302 1 6 6 2 395 200 2 10 688 2 10 2 fcr( real ) 2 2.5 115 106 362nF F 395 (e eq-41) Rev. 1.0 www w.aosmd.com Page 11 of 21 Applicatio on Note PIC-014 P 0.33µF/50V is i selected. Series compe ensation resis stor: R1 1 1 32.1K 2 C1 fcz( reall ) 2 3.14 0.33 10 6 15 (e eq-42) 33K/0805 is selected. s Parallel comp pensation cap pacitor: Cps Cp // Cs Cp 1 1 41nF 2 Rs fcp 2 3.14 33 10 1 3 117 Cs Cps Cs Cps (e eq-43) 0.33 F 41 4 nF 46.8nF n 0.33 F 41 4 nF (e eq-44) 47nF/50V is selected. s 5. Calcu ulated Overall Loop Bode Plot Gwhole(s ) Gpower (s ) Gcoomp(s ) Ct Ichargger Vin 2 4 Vout L RL 1 s 2 Go 1 1 s 1 RL Co s 2 fz s 2 fp (e eq-45) Calculated bo ode plot: Rev. 1.0 Crosss frequency: fcr ( reall ) root Gwhole( 2f ) 1, f 15.944Hz Phasse Margin: 18 80 180 1 arg Gwhole( 2fcr ) 48.36 deg d www w.aosmd.com (e eq-46) (e eq-47) Page 12 of 21 Applicatio on Note PIC-014 P Appendix1 1 Experime ental Verifiication The table is the t experimen ntal results off the converte er. Vin 90Vac 1 115V ac 2 230V ac 2 264V ac Pout(W) 80 160 80 160 80 160 80 160 Pin(W W) 84.4 4 169..5 83.5 5 166..6 82.6 63 163..1 82.6 62 162..9 ŋ (%) 94 4.8 94 4.4 95 5.8 96 6.0 96 6.8 98 8.1 96 6.8 98 8.2 PF 0.994 0.997 0.991 0.996 0.945 0.977 0.900 0.950 THD 11.5 7.1 13.5 8.3 24.8 11.9 42.5 23.3 Start-up waveforms of outtput voltage: Figures F 10 an nd 11 show th he start-up tim me for 115Vacc full load and d no load. p in the close ed loop soft-sttart. The inductor current increases smoothly due to keep CH2 2: DC Output Vo oltage – CH4: Ind ductor Current Figure 10. Start-Up S Wav veform of Vouut at 115Vac Full Load CH2 2: DC Output Vo oltage – CH4: Ind ductor Current Figure 11. Start-Up S Wav veform of Vouut at 115Vac No N Load Rev. 1.0 www w.aosmd.com Page 13 of 21 Applicatio on Note PIC-014 P Figures 12 and a 13 show the output voltage v respo onse when the AC input iss omitted for 20ms and 40ms. 4 As Figure 12 ob bserved that Vcomp increassed when the e AC input is absent for 20ms, 2 the peak inductor current c is limited cycle--by-cycle by OCP O compara ator. But whe en the AC input is absent for f over 20mss, the Vcomp iss reduced to zero rapidlly and restarts s smoothly when AC is applied again as Figure 13 shown. CH1: Vcomp – CH2: DC Outp put Voltage – CH H3: Sense Resis stor Voltage – CH4: C AC Input Current C Figure 12. AC-Absent for 20ms De etection Operation CH1: Vcomp – CH2: DC Outp put Voltage – CH H3: Sense Resistor Voltage – CH4: C AC Input Current C Figure 13. AC-Absent for 40ms De etection Operation Rev. 1.0 www w.aosmd.com Page 14 of 21 Applicatio on Note PIC-014 P Figures 14 an nd 15 show th he output response and ind ductor curren nt for 115Vac full f load and 115V 1 ac no load. CH2 2: DC Output Vo oltage – CH4: Ind ductor Current Figure e 14. Output Response of o Dynamic Load (60W—1 160W@230Vac a ) CH2 2: DC Output Vo oltage – CH4: Ind ductor Current Figure e 15. Output Response of o Dynamic Load (160W— —60W@230Vac a ) Rev. 1.0 www w.aosmd.com Page 15 of 21 Applicatio on Note PIC-014 P Loop gain. Th he frequency response is measured at four condition ns. Figure 16 shows that at a 264Vac inpu ut voltage the crossover frequency is s 20.44Hz an nd the phase margin is 57..0deg. Figure 17 show 230 0Vac input voltage, the equency is 18 8.44Hz and the t phase ma argin is 54.7d deg. Figure 18 1 show 115Vac input volttage, the crossover fre crossover fre equency is 6.91Hz 6 and th he phase ma argin is 52.7d deg. Figure 19 show 90V Vac input volttage, the crossover fre equency is 5.2 2Hz and the phase p margin is 52.1deg. Figure 16. Phase Margin @264Vac L a -50Hz Full Load Figure 17. Phase Margin @230Vac L a -50Hz Full Load Rev. 1.0 www w.aosmd.com Page 16 of 21 Applicatio on Note PIC-014 Figure 18. Phase Margin @115V Vac-50Hz Full Load Figure 19. 1 Phase Ma argin @90Vacc-50Hz Full Load L Rev. 1.0 www w.aosmd.com Page 17 of 21 Applicatio on Note PIC-014 P Appendix 2: PCB LA AYOUT Fig gure 20. Reco ommended PCB P Layout PCB Layout Guide The following g points are good PCB layo out guild-line for a PFC sta age. 1. To ke eep the IC GND G pin as clean as possible, the powe er stage grou und and the signal s ground must be sepa arated. Then both groundss are connectted by a sepa arated signal line. At the same s time, th he signal groun nd end of thiis line should d be connect to the end of o current sen nse resistor which w is conn nected to powe er ground as shown in Figure 20. Figurre 21 shows that if the sign nal ground en nd connects directly d to the power p stage ground, g the CS C pin is easily interrupted.. Figure 22 sh hows, the inductor current ramp-up to a higher level and become es distorted since s the signal ground iss interrupted by noise an nd the IC not detect the zero current signal. cann Rev. 1.0 www w.aosmd.com Page 18 of 21 Applicatio on Note PIC-014 P Brreak-off this line e which connectts from the end of sig gnal ground pin (pin ( 6) to the currrent sense resistor en nd which joins the e power ground. Connect this end C d directly to the p power stage grou und. Figure 21. Bad B Layout (The Signal Ground G Conn nects Directlly to Power Ground) G C CH2: Inductor Cu urrent – CH4: In nput Current Figure e 22. Interrup pted Input Cu urrent Wavefform and Ind ductor Current Rev. 1.0 www w.aosmd.com Page 19 of 21 Applicatio on Note PIC-014 P 2. The PFC MOSFET gate drive loop l path sho ould be minim mized 3. Minim mize the trace length to IN NV pin. Since e the feedback node is high impedancce, the trace from the outpu ut resistor div vider to INV pin should be as a short as po ossible. 4. Switcching current sense (CS pin) p is very im mportant for the t stable op peration of PF FC stage. No ormally, a RC filter is recomm mended to re educe the noisse applied to CS pin. 5. The Vcc decouplin ng capacitor Cvcc needs to be b placed as closed as po ossible to IC Vcc and GND pin. p Appendix 2: BILL OF MA ATERIALS (B BOM) signation Ref Des F FU NT TC VA AR CX1 FL1 CX2 B BD CM1 L Q Q1 D D2 C11,C12 R R5 D D1 R12~ ~R16, R19~R23 R R17 R R18 R R24 R R25 C C10 C C9 R R11 C C8 R R27 R R26 R R28 D3 3,D7 ZD3(optional) R R8 C C5 C C6 C C7 R R9 C C4 C C3 IC C1 Rev. 1.0 Value 5A/250V V SCK-044 4K 10D-471 0.22µ/275V VAC 25mH 0.33µF/275 5VAC D15XB6 60 0.68µF/63 30V 200µH AOT11CF F60 BYV29X X 68µF/450 0V 0.1Ω/5W W 1N5408 8 Description Fuse, 5A A/250V NTC, SCK-044K VAR, 10 0D-471 X CAP, 0.22µ µF/275VAC Com mmon mode EMI E filter, 25m mH X CAP, 0.33µ µF/275VAC AC C Bridge rectifier, D15XB60 D filter cap, 0.68µF/630V DM 0 PFC chockk, 200µH AOT11CF60 P PFC boost dio ode, BYV29X B Bulk cap, KMF F 450V/68µF R Rense resisto or, 0.1Ω/5W Diode, 1N5408 1MΩ Thick Film Res, 1% 1206 27KΩ 4.22KΩ Ω 27KΩ 3.9KΩ 1nF/50V V 10nF/50 0V 240Ω 100pF/50 0V 10KΩ 10Ω 2.4Ω LL4148 8 3.9V Zen ner 0Ω 470pF/50 0V 0.22uF/50 0V 47nF/50 0V 10KΩ 0.1µF/50 0V 22µF/50 0V AOZ7111 Thick Film Res, 1% Thick Film Res, 1% Thick Film Res, 1% Thick Film Res, 1% Ce eramic Cap, 50V, 5 X5R/X7R R Ce eramic Cap, 50V, 5 X5R/X7R R Thick Film Res, 1% Ce eramic Cap, 50V, 5 X5R/X7R R Thick Film Res, 1% Thick Film Res, 1% Thick Film Res, 1% 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 3.9V Zene er 0.5W Thick Film Res, 1% Ce eramic Cap, 50V, 5 X5R/X7R R Ce eramic Cap, 50V, 5 X5R/X7R R Ce eramic Cap, 50V, 5 X5R/X7R R Thick Film Res, 1% Ce eramic Cap, 50V, 5 X5R/X7R R EC Cap p, 50V CRM PFC Controller C 0603 0603 0603 0603 0603 0603 5*11 SO-8 www w.aosmd.com Packag ge EER301 19 TO-220F TO-220F Manufac cturer AOS S NXP P Samyoung DO-241 1 AOS S Page 20 of 21 Applicatio on Note PIC-014 P LEGAL DISCL LAIMER Alpha and Om mega Semicond ductor makes no n representations or warranties with respe ect to the accuracy or comple eteness of the information n provided herein and takess no liabilities for the conseq quences of usse of such info ormation or an ny product described here ein. Alpha and d Omega Semiiconductor reserves the right to make cha anges to such information att any time without furtherr notice. This do ocument does not constitute the t grant of an ny intellectual property p rights or o representatio on of noninfringement of any third partty’s intellectual property rightss. LIFE SUPPOR RT POLICY ALPHA AND OMEGA O SEMIC CONDUCTOR PRODUCTS ARE A NOT AUT THORIZED FO OR USE AS CR RITICAL COMP PONENTS IN LIFE SUPP PORT DEVICES S OR SYSTEM MS. As used herein n: 1. Life supportt devices or sys stems are devicces or systems which h, (a) are intend ded for surgical implant into the body or (b)) support or sus stain life, and (c) ( whose failure to perfo orm when prope erly used in acccordance with instructions forr use provided in the labeling, can be reasonably exp pected to resullt in a significan nt injury of the user. Rev. 1.0 2. A critical c compon nent in any com mponent of a liffe supp port, device, or system whose failure to perfo orm can be re easonably expe ected to cause the failure of th he life supp port device or syystem, or to afffect its safety or o effecctiveness. www w.aosmd.com Page 21 of 21