MB15E07SR - Spansion

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–21378–3E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 2.5 GHz Prescaler
MB15E07SR
■ DESCRIPTION
The Fujitsu Semiconductor MB15E07SR is a serial input Phase Locked Loop (PLL) frequency synthesizer
with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling
pulse swallowing operation.
The supply voltage range is between 2.7 V and 5.0 V. A refined charge pump supplies well-balanced output
currents of 1.0 mA and 4.0 mA. The charge pump current is selectable by serial data.
The phase noise of MB15E07SR was drastically improved comparing wuth the former single PLL,
MB15E07SL. The data format of serial data and the pin assignments except for φP, φR and OSCout pins
are same as the former one, so it is easy to replace the former one.
MB15E07SR is ideally suited for the base station of GSM (Global System for Mobile Communications) and
PCS.
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
High frequency operation: 2.5 GHz Max
Low power supply voltage: VCC = 2.7 V to 5.0 V
Ultra Low power supply current:ICC = 8.0 mA Typ (VCC = Vp = 3.75 V, Ta = +25°C, in locking state)
Direct power saving function:Power supply current in power saving mode
Typ 0.1 μA (VCC = Vp = 3.75 V, Ta = +25°C)
Dual modulus prescaler: 32/33 or 64/65
Serial input 14-bit programmable reference divider: R = 3 to 16,383
Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
Software selectable charge pump current
On-chip phase control for phase comparator
Built-in digital locking detector circuit to detect PLL locking and unlocking
Operating temperature: Ta = –40 °C to +85 °C
Copyright©2003-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.10
MB15E07SR
■ PIN ASSIGNMENTS
16-pin TSSOP
OSCIN
1
16
NC
NC
2
15
NC
VP
3
14
LD/fout
VCC
4
13
NC
Top view
DO
5
12
PS
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
(FPT-16P-M07)
2
DS04–21378–3E
MB15E07SR
■ PIN DESCRIPTIONS
Pin no.
TSSOP
Pin
name
I/O
1
OSCIN
I
Programmable reference divider input. Connection to a TCXO.
2
NC
–
No connection.
3
VP
–
Power supply voltage input for the charge pump.
4
VCC
–
Power supply voltage input.
5
DO
O
Charge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
6
GND
–
Ground.
7
Xfin
I
Prescaler complementary input, which should be grounded via a capacitor.
8
fin
I
Prescaler input.
Connection to an external VCO should be done via AC coupling.
9
Clock
I
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10
Data
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
11
LE
I
Load enable signal input. (Open is prohibited.)
When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
Descriptions
12
PS
I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
13
NC
–
No connection.
14
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15
NC
–
No connection.
16
NC
–
No connection.
DS04–21378–3E
3
MB15E07SR
■ BLOCK DIAGRAM
OSCIN
fr
1
Reference
oscillator circuit
Binary 14-bit
reference couter
SW
FC
LDS CS
4-bit latch
Phase
comparator
14-bit latch
PS
12
LE 11
Intermittent
mode control
(power save)
C
N
T
Lock
detector
19-bit shift register
LD/fr/fp
selector
1-bit
control
latch
14
3
7-bit latch
Data
Binary 7-bit
swallow
counter
10
Clock 9
Xfin 7
fin
GND
VCC
4
8
Charge
pump
11-bit latch
5
LD/fout
VP
DO
Binary 11-bit
programmable
counter
fp
Prescaler
32/33
64/65
SW
6
4
DS04–21378–3E
MB15E07SR
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
Condition
VCC
Rating
Unit
Min
Max
–
–0.5
5.5
V
VP
–
VCC
6.0
V
VI
–
–0.5
VCC + 0.5
V
VO
Except Do
GND
VCC
V
VO
Do
GND
VP
V
Tstg
–
–55
+125
°C
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Typ
Max
VCC
2.7
3.75
5.0
V
VP
VCC
–
5.5
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS04–21378–3E
5
MB15E07SR
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 5.0 V, Ta = –40°C to +85°C)
Symbol
Parameter
Typ
Max
fIN = 2500 MHz,
VCC = VP = 3.75 V
–
8.0
–
mA
IPS
PS = “L”
–
0.1*2
20
μA
fin
fIN
50 Ω system
100
–
2500
MHz
OSCIN
OSCIN
3
–
40
MHz
fin*3
Pfin
100 MHz to 300 MHz
–6
–
+2
dBm
300 MHz to 2500 MHz
–15
–
+2
dBm
Vp-p
ICC*1
Power saving current
Input sensitivity
“L” level input voltage
“H” level input current
“L” level input current
“H” level input current
“L” level input current
“H” level output voltage
“L” level output voltage
VOSC
–
0.5
–
VCC
Data,
Clock,
LE, PS
VIH
–
VCC × 0.7
–
–
VIL
–
–
–
VCC × 0.3
Data,
Clock,
LE, PS
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
IIH
–
0
–
+100
I *
–
–100
–
0
OSCIN
IL 4
LD/fout
“H” level output voltage
VOH
VCC = VP = 3.75 V, IOH = –1 mA VCC – 0.4
–
–
VOL
VCC = VP = 3.75 V, IOL = 1 mA
–
–
0.4
VDOH
VCC = VP = 3.75 V,
IDOH = –0.5 mA
VP – 0.4
–
–
VDOL
VCC = VP = 3.75 V,
IDOL = 0.5 mA
–
–
0.4
IOFF
VCC = VP = 3.75 V,
VOFF = 0.5 V to VP – 0.5 V
–
–
2.5
Do
“L” level output voltage
High impedance cutoff
current
“H” level output current
“L” level output current
Do
LD/fout
“H” level output current
–
–
–
–1.0
IOL
–
1.0
–
–
CS bit = “1”
–
–4.0
–
CS bit = “0”
–
–1.0
–
CS bit = “1”
–
4.0
–
CS bit = “0”
–
1.0
–
IDOH*4
“L” level output current
IDOL
IDOL/IDOH I
vs VDO
vs Ta
VCC = 3.75 V,
VP = 3.75 V,
VDO = VP/2
Ta = +25°C
V
μA
μA
V
V
IOH
Do
Charge pump current
rate
–
OSCIN*
3
“H” level input voltage
Unit
Min
Power supply current*1
Operating frequency
Value
Condition
nA
mA
mA
DOMT*5
VDO = VP/2
–
5
–
%
DOVD*6
0.5 V ≤ VDO ≤ VP – 0.7 V
–
10
–
%
DOTA*7
– 40°C ≤ Ta ≤ +85°C
–
3
–
%
I
I
*1: Conditions; fosc = 13 MHz, Vosc = 1.2 VPP , Ta = +25°C, in locking state.
*2: VCC = VP = 3.75 V, fosc = 13 MHz, Vosc = 1.2 VPP , Ta = +25°C, in power saving mode
*3: AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency.
*4: The symbol “–” (minus) means direction of current flow.
*5: VCC = VP = 3.0 V, Ta = +25°C
(||I3| – |I4||) / [(|I3| + |I4|) /2] × 100(%)
(Continued)
6
DS04–21378–3E
MB15E07SR
(Continued)
*6: VCC = VP = 3.0 V, Ta = +25°C [(||I2| – |I1||) /2] / [(|I1| + |I2|) /2] × 100(%) (Applied to each IDOL, IDOH)
*7: VCC = VP = 3.0 V, VDO = VP/2 (||IDO(+85°C)| – |IDO(–40°C)|| /2) / (|IDO(+85°C)| + |IDO(–40°C)| /2) × 100(%) (Applied to each
IDOL, IDOH)
I1
I3
I2
IDOL
IDOH
I4
I2
I1
0.5
Vp/2
Vp − 0.7 V Vp
Charge Pump Output Voltage (V)
DS04–21378–3E
7
MB15E07SR
■ FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M
: Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is
taken high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT)
Destination of serial data
H
For the programmable reference divider
L
For the programmable divider
(1) Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
SW
FC LDS CS
CNT
R1 to R14
SW
FC
LDS
CS
: Control bit
: Divide ratio setting bit for the programmable reference counter (3 to 16,383)
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/fOUT signal select bit
: Charge pump current select bit
18
19
[Table 1]
[Table 2]
[Table 5]
[Table 8]
[Table 7]
[Table 6]
Note: Start data input with MSB first.
8
DS04–21378–3E
MB15E07SR
Programmable Counter
MSB
LSB
Data Flow
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
CNT
: Control bit
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
[Table 1]
[Table 3]
[Table 4]
Note: Data input with MSB first.
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R)
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N)
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 3 is prohibited.
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A)
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
DS04–21378–3E
9
MB15E07SR
Table 5. Prescaler Data Setting
SW
Prescaler divide ratio
1
32/33
0
64/65
Table 6. Charge Pump Current Setting
CS
Current value
1
±4.0 mA
0
±1.0 mA
Table 7. LD/fout Output Select Data Setting
LD/fOUT output signal
LDS
1
fout signal
0
LD signal
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output
level (DO) is reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit.
The relationship between the FC bit and DO is shown below.
Table 8. FC Bit Data Setting (LDS = “1”)
FC = 1
DO
fr > fP
H
fr < fP
L
fr = fP
Z*
FC = 0
LD/fout
DO
LD/fout
L
fout = fr
H
fout = fp
Z*
*: High impedance
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
When the LPF and VCO characteristics are similar
to (1), set FC bit high.
When the VCO characteristics are similar to (2),
set FC bit low.
(1)
VCO
Output
Frequency
PLL
LPF
VCO
(2)
Note : Give attention to the polarity for using active type LPF.
10
LPF Output Voltage
DS04–21378–3E
MB15E07SR
3. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal
operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency
(fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an
increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the
error signal from the phase detector when it returns to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 μs.
The serial data input after the power supply becames stable, and then the power saving mode is released
after completed the data input.
OFF
ON
tV ≥ 1 μs
VCC
Clock
Data
LE
tPS ≥ 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 μs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS: L → H) 100 ns later after setting serial data.
DS04–21378–3E
11
MB15E07SR
■ SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
Invalid data
∼
Data
MSB
LSB
∼
∼
Clock
t2
t1
t3
t6
t7
LE
∼
t4
t5
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
Min
Typ
Max
Unit
Parameter
Min
Typ
Max
Unit
t1
20
–
–
ns
t5
100
–
–
ns
t2
20
–
–
ns
t6
20
–
–
ns
t3
30
–
–
ns
t7
100
–
–
ns
t4
30
–
–
ns
Note: LE should be “L” when the data is transferred into the shift register.
12
DS04–21378–3E
MB15E07SR
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
t WU
t WL
LD
[FC = “H”]
DO
[FC = “L”]
DO
Notes : • Phase error detection range: –2 π to +2 π
• Pulses on Do signal during locked state are output to prevent dead zone.
• LD output becomes low when phase is tWU or more. LD output becomes high when phase
error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency.
tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz)
tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz)
• LD becomes high during the power saving mode (PS = “L”).
DS04–21378–3E
13
MB15E07SR
■ MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF
0.1 μF
1000 pF
0.1 μF
1000 pF
S.G.
S.G.
50 Ω
fin
Xfin GND
DO
VCC
VP
NC
OSCIN
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
Clock Data LE
PS
NC LD/fout NC
VCC
50 Ω
NC
Oscilloscope
Controller (setting divide ratio)
14
DS04–21378–3E
MB15E07SR
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Input sensitivity - Input frequency
Ta = +25 °C
10
Input sensitivity Pfin (dBm)
0
Catalog guaranteed range
−10
−20
−30
VCC = 2.7 V
VCC = 3.75 V
VCC = 5.0 V
VCC = 5.25 V
SPEC
−40
−50
0
500
1000
1500
2000
2500
3000
3500
4000
Input frequency fIN (MHz)
2. OSCIN Input Sensitivity
Input sensitivity - Input frequency
Ta = +25 °C
Input sensitivity VOSC (dBm)
10
Catalog
guaranteed
range
0
−10
−20
−30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.75 V
VCC = 5.0 V
SPEC
−40
−50
0
20
40
60
80
100
120
140
160
180
Input frequency fOSC (MHz)
DS04–21378–3E
15
MB15E07SR
3. Do output current
• 1.0 mA mode
IDO - VDO
Charge pump output current IDO (mA)
10.00
Ta = + 25 °C
VCC = 3.75 V
Vp = 3.75 V
2.000
/div
−10.00
0.00
1.00/div
7.00
Charge pump output voltage VDO (V)
• 4.0 mA mode
IDO - VDO
Charge pump output current IDO (mA)
10.00
Ta = + 25 °C
VCC = 3.75 V
Vp = 3.75 V
2.000
/div
−10.00
0.00
1.00/div
7.00
Charge pump output voltage VDO (V)
16
DS04–21378–3E
MB15E07SR
4. fin input impedance
4
22.184 Ω
61.264 Ω 3.9002 nH
2 500.000 000 MHz
1 : 78.328 Ω
−319.34 Ω
300 MHz
4
2 : 22.145 Ω
−77.82 Ω
1 GHz
3
3 : 14.324 Ω
13.364 Ω
2 GHz
1
2
START
300.000 000 MHz
STOP 2 500.000 000 MHz
5. OSCIN input impedance
4 32.719 Ω
−801.28 Ω 4.9656 pF
2 500.000 000 MHz
1:
633.5 Ω
−9.258 kΩ
3 MHz
2 : 038.63 Ω
−3.0145 kΩ
10 MHz
3 : 083.94 Ω
−1.5534 kΩ
20 MHz
4
213
START
DS04–21378–3E
3.000 000 000 MHz
STOP 40.000 000 MHz
17
MB15E07SR
■ REFERENCE INFORMATION
Test Circuit
S.G.
fVCO = 1730 MHz
KV = 42 MHz/V
fr = 200 kHz
fOSC = 13 MHz
LPF
OSCIN
fin
LPF
Do
1000 pF
Spectrum
Analyzer
VCO
VCC =VP = 3.75 V
VVCO = 3.3 V
Ta = +25 °C
CP : 4.0 mA mode
27 kΩ
2.7 kΩ
120 pF
15000 pF
• PLL Reference Leakage
REF −10.0 dB
MKRΔ 200 kHz −80.39 dBc
DELTA MKR
200 kHz
NOISE/1 Hz
−116.53 dBc/Hz
CENTER 1.732004 GHz
RBW 3 kHz
VBW 30 Hz
SWP 23 s
SPAN 1.00 MHz
ATT 10 dB
• PLL Phase Noise
REF −10.0 dB
VAVG 10
DELTA MKR
10 1.00 kHz
10
CENTER 1.73200392 GHz
RBW 30 Hz
VBW 100 Hz
MKRΔ 1.00 kHz −81.66 dBc/Hz
NOISE/1 Hz
−81.66 dBc/Hz
SWP 2.0 s
SPAN 10.00 kHz
ATT 10 dB
(Continued)
18
DS04–21378–3E
MB15E07SR
(Continued)
1805 MHz→ 1730 MHz within ± 1 kHz
Hch→Lch
375 μs
1730 MHz→ 1805 MHz within ± 1 kHz
Lch→Hch
390 μs
Δ Mkr x : 375.00233 μs
y : −75.0818 MHz
Δ Mkr x : 389.98165 μs
y : 74.8653 MHz
100.0050
MHz
100.0050
MHz
2.88
kHz/01v
2.88
kHz/01v
99.99500
MHz
99.99500
MHz
0 s
0 s
2.0000000 μs
Δ Mkr x : 389.98165 μs
y : 74.8653 MHz
2.0000000 μs
Δ Mkr x : 375.08233 μs
y : −75.0018 MHz
100.0050
MHz
250.0000
MHz
2.88
kHz/01v
50.0000
MHz/01v
99.99500
MHz
0
Hz
0 s
DS04–21378–3E
2.0000000 μs
0 s
2.0000000 μs
19
MB15E07SR
■ APPLICATION EXAMPLE
OUTPUT
VCO
LPF
Lock Det.
From
a controller
NC
NC
LD/fout
NC
PS
LE
Data
Clock
16
15
14
13
12
11
10
9
MB15E07SR
1
2
3
4
5
6
7
8
OSCIN
NC
VP
VCC
DO
GND
Xfin
fin
1000 pF
1000 pF
1000 pF
0.1 F
0.1 F
TCXO
VP: 5.5 V Max
■ USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting device into or removing device from a socket.
-Protect leads with a conductive sheet when transporting a board-mounted device.
20
DS04–21378–3E
MB15E07SR
■ ORDERING INFORMATION
Part number
MB15E07SRPFT
DS04–21378–3E
Package
Remarks
16-pin, Plastic TSSOP
(FPT-16P-M07)
21
MB15E07SR
■ PACKAGE DIMENSIONS
16-pin plastic TSSOP
(FPT-16P-M07)
16-pin plastic TSSOP
(FPT-16P-M07)
Lead pitch
0.65 mm
Package width ×
package length
4.40 × 5.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.10mm MAX
Weight
0.06g
Code
(Reference)
P-TSSOP16-4.4×5.0-0.65
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
*1 5.00±0.10(.197±.004)
0.17±0.05
(.007±.002)
9
16
*2 4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(Mounting height)
(.041±.002)
LEAD No.
1
8
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8°
+0.03
(0.50(.020))
0.10(.004)
C
22
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F16020S-c-3-5
0.60±0.15
(.024±.006)
+.001
0.07 –0.07 .003 –.003
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
DS04–21378–3E
MB15E07SR
MEMO
DS04–21378–3E
23
MB15E07SR
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department