FUJITSU MB15E07L

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21355-1E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 2.5 GHz prescaler
MB15E07L
■ DESCRIPTION
The Fujitsu MB15E07L is serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler.
A 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 4.5 mA typ. This
operates with a supply voltage of 3.0 V (typ.)
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result
of this, MB15E07L is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile
Communications).
■ FEATURES
• High frequency operation: 2.5 GHz max. (@ P = 64/65)
2.0 GHz max. (@ P = 32/33)
• Low power supply voltage: VCC = 2.7 to 3.6 V
• Very Low power supply current: ICC = 4.5 mA typ. (VCC = 3 V)
• Power saving function: IPS = 0.1 µA typ. (VCC = 3 V)
• Pulse swallow function: 32/33 or 64/65
• Serial input 14-bit programmable reference divider: R = 5 to 16,383
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 5 to 2,047
• Wide operating temperature: Ta = –40 to +85°C
• Plastic 16-pin SSOP package (FPT-16P-M05) and 16-pads BCC package (LCC-16P-M02)
■ PACKAGES
16-pin, plastic SSOP
(FPT-16P-M05)
16-pads, plastic BCC
(LCC-16P-M02)
MB15E07L
■ PIN ASSIGNMENTS
SSOP-16 pin
OSCIN
1
16
φR
OSCOUT
2
15
φP
VP
3
14
LD/fout
VCC
4
13
ZC
DO
5
12
PS
GND
6
11
LE
Xfin
7
10
Data
fin
8
9
Clock
Top
View
(FPT-16P-M05)
BCC-16 pads
OSCIN φR
OSCOUT
1
VP
2
VCC
3
DO
4
GND
5
Xfin
6
16
15
Top view
7
8
fin Clock
(LCC-16P-M02)
2
14
φP
13
LD/fout
12
ZC
11
PS
10
LE
9
Data
MB15E07L
■ PIN DESCRIPTIONS
Pin no.
SSOP-16
BCC-16
Pin
name
I/O
Descriptions
1
16
OSCIN
I
Programmable reference divider input.
Oscillator input.
Connection for an crystal or a TCXO.
TCXO should be connected with a coupling capacitor.
2
1
OSCOUT
O
Oscillator output.
Connection for an external crystal.
3
2
VP
–
Power supply voltage input for the charge pump.
4
3
VCC
–
Power supply voltage input.
5
4
DO
O
Charge pump output.
Phase of the charge pump can be reversed by FC bit.
6
5
GND
–
Ground.
7
6
Xfin
I
Prescaler complementary input, and should be grounded via a
capacitor.
8
7
fin
I
Prescaler input.
Connection with an external VCO should be done with AC coupling.
9
8
Clock
I
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10
9
Data
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = “H” ; Data is transmitted to the programmable reference
counter.
Control bit = “L” ; Data is transmitted to the programmable counter.
11
10
LE
I
Load enable signal input (Open is prohibited.)
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
I
Forced high-impedance control for the charge pump (with internal pull
up resistor.)
ZC = “H” ; Normal DO output.
ZC = “L” ; DO becomes high impedance.
12
13
11
12
PS
ZC
14
13
LD/fout
O
Lock detect signal output (LD)/phase comparator monitoring output
(fout).
The output signal is selected by LDS bit in the serial data.
LDS = “H” ; outputs fout (fr/fp monitoring output)
LDS = “L” ; outputs LD (“H” at locking, ”L” at unlocking.)
15
14
φP
O
Phase comparator output for an external charge pump. Nch open
drain output.
16
15
φR
O
Phase comparator output for an external charge pump. CMOS
output.
3
MB15E07L
■ BLOCK DIAGRAM
OSCIN 1
fr
Crystal
oscillator
circuit
fp
Programmable
reference divider
OSCOUT 2
Lock
detector
fr
Intermittent
mode control
(power save)
SW
17-bit latch
LE
LE 11
14-bit latch
16 φR
15 φP
LD
Binary 14-bit
reference counter
PS 12
Phase
comparator
LDS
FC
LD/fr/fp
selector
3-bit latch
14 LD/fout
fp
1-bit
control
latch
19-bit shift register
C
N
T
Data 10
13 ZC
19-bit shift register
Super
charger
Clock 9
5 DO
18-bit latch
LE
7-bit latch
11-bit latch
SW
Programmable divider
Xfin 7
fin 8
Prescaler
32/33,
64/65
Binary 7-bit
swallow
counter
Binary 11-bit
programmable
counter
GND 6
VCC 4
Note: SSOP-16 pin
4
3 VP
MD
Control circuit
fp
MB15E07L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Remark
Min.
Max.
VCC
–0.5
+4.0
V
VP
VCC
+6.0
V
Input voltage
VI
–0.5
VCC +0.5
V
Output voltage
VO
–0.5
VCC +0.5
V
IO
–10
+10
mA
Except DO output
Ido
–25
+25
mA
DO output
Tstg
–55
+125
°C
Power supply voltage
Output current
Storage temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min.
Typ.
Max.
VCC
2.7
3.0
3.6
V
VP
VCC
–
6.0
V
Input voltage
VI
GND
–
VCC
V
Operating temperature
Ta
–40
–
+85
°C
Power supply voltage
Remark
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
HandIing Precautions
• This device should be transported and stores in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15E07L
■ ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Power supply current*1
ICC*1
fin = 2500 MHz,
fosc = 12 MHz, P = 64/65
–
4.5
–
mA
Power saving current
Ips*2
ZC = “H” or open
–
–
10
µA
Operating frequency
fin
P = 32/33
100
–
2000
P = 64/65
100
–
2500
3
–
40
MHz
–10
–
+2
dBm
VP-P
Crystal oscillator operating frequency
Input sensitivity
Input voltage
Input current
fOSC
min. 500 mVP-P
fin*3
Vfin
50 Ω system
(Refer to the test circuit.)
OSCIN*3
VOSC
–
0.5
–
VCC
Data, Clock,
LE, PS, ZC
VIH
–
VCC × 0.7
–
–
VIL
–
–
–
VCC × 0.3
Data, Clock,
LE, PS
IIH*4
–
–1.0
–
+1.0
IIL*4
–
–1.0
–
+1.0
IIH*4
–
–1.0
–
+1.0
–100
–
0
ZC
OSCIN
Output voltage
High impedance
cutoff current
*4
IIL
IIH
–
0
–
+100
IIL*4
–
–100
–
0
–
–
0.4
VCC – 0.4
–
–
–
–
0.4
VP – 0.4
–
–
VOL
Open drain output
φR,
LD/fout
VOH
VCC = 3 V, IOH = –1 mA
VOL
VCC = 3 V, IOL = 1 mA
MHz
V
µA
µA
µA
V
V
VDOH
VCC = 3 V, IOH = –1 mA
VDOL
VCC = 3 V, IOL = 1 mA
–
–
0.4
DO
IOFF
VCC = 3 V, VP = 6 V
VOOP = GND to 6 V
–
–
3.0
nA
φP
IOL
Open drain output
1.0
–
–
mA
φR,
LD/fout
*4
IOH
–
–1.0
–
–
IOL
–
–
–
1.0
VCC = 3 V, VP = 3 V,
VDOH = 2.0 V, Ta = +25°C
–11
–
–6
VCC = 3 V, VP = 3 V
VDOL = 1.0 V, Ta = +25°C
8
Output current
IDOH*4, 5
DO
IDOL
*1:
*2:
*3:
*4:
*5:
Pull up input
φP
DO
6
(VCC = 2.7 to 3.6 V, Ta = –40 to +85°C)
Value
Unit
Min.
Typ.
Max.
*4
Conditions; VCC = 3.0 V, Ta = +25°C, in locking state.
VCC = 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode.
AC coupling with a 1000 pF capacitor connected.
The symbol “–” (minus) means direction of current flow.
Ta = +25°C
V
mA
mA
–
15
MB15E07L
■ FUNCTION DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M
: Preset divide ratio of modules prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
H
17 bit latch (for the programmable reference divider)
L
18 bit latch (for the programmable divider)
(1) Shift register configuration
Programmable reference counter
MSB
Data flow
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14 SW FC LDS
CNT
R1 to R14
SW
FC
LDS
16
: Control bit
: Divide ratio setting bit for the programmable reference counter (5 to 16,383)
: Divide ratio setting bit for the prescaler (32/33 or 64/65)
: Phase control bit for the phase comparator
: LD/fout signal select bit
17
18
[Table. 1]
[Table. 2]
[Table. 5]
[Table. 7]
[Table. 6]
Note: Start data input with MSB first
7
MB15E07L
Programmable reference counter
MSB
Data flow
LSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C
N
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
T
CNT
: Control bit
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
[Table. 1]
[Table. 3]
[Table. 4]
Note: Start data input with MSB first
Table.2 Binary 14-bit Programmable Reference Counter Data Setting
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
5
0
0
0
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
0
1
1
0
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
1
1
1
1
1
1
1
1
Note: • Divide ratio less than 5 is prohibited.
8
MB15E07L
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1
1
1
1
1
1
1
Table.5 Prescaler Data Setting
SW
Prescaler divide ratio
H
32/33
L
64/65
Table.6 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout signal
L
LD signal
(2) Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor
pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is
shown below.
Table.7 FC Bit Data Setting (LDS = “H”)
FC = High
FC = Low
DO
φR
φP
fr > fp
H
L
L
fr < fp
L
H
Z*
fr = fp
Z*
L
Z*
LD/fout
fout = fr
DO
φR
φP
L
H
Z*
H
L
L
Z*
L
Z*
LD/fout
fout = fp
* : High impedance
9
MB15E07L
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
∗: When the LPF and VCO characteristics are
(1)
similar to (1), set FC bit high.
∗: When the VCO characteristics are similar to
(2), set FC bit low.
VCO
output
frequency
PLL
LPF
VCO
(2)
LPF input voltage
Table.8 PS Pin Setting
PS pin
Status
H
Normal mode
L
Power saving mode
Table.9 ZC Pin Setting
ZC pin
10
DO output
H
Normal output
L
High impedance
MB15E07L
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current consumption can be limited to
10 µA (max.). Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power
saving mode. In general, the power consumption can be saved by the intermittent operation that powering down
or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator
output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and
comparison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA (max.).
Note: • While the power saving mode is executed, ZC pin should be set at “H” or open. If ZC is set at “L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set “L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
ON
VCC
Clock
Data
LE
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data after power supply remains stable.
(3) Relase power saving mode (PS : L → H) after setting serial data.
11
MB15E07L
4. Serial Data Input Timing
1st. data
2nd. data
Control bit Invalid data
~
LSB
MSB
Data
~
~
Clock
t1
t3
t2
t6
t7
LE
~
t4
t5
On rising edge of the clock, one bit of the data is transferred into the shift register.
12
Parameter
Min.
t1
20
t2
Typ.
Max.
Unit
Parameter
–
–
ns
t5
100
20
–
–
ns
t6
t3
30
–
–
ns
t7
t4
30
–
–
ns
Min.
Typ.
Max.
Unit
–
–
ns
20
–
–
ns
100
–
–
ns
MB15E07L
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[ FC = “H” ]
φP
φR
H
DO
Z
L
[ FC = “L” ]
φP
φR
H
DO
L
Z
Notes: 1. Phase error detection range: –2π to +2π
2. Pulses on DO output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cycles or more.
4. tWU and tWL depend on OSCIN input frequency.
tWU > 4/fosc (e. g. tWU > 312.5 ns, foscin = 12.8 MHz)
tWL < 8/fosc (e. g. tWL < 625.0 ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = “L”.)
13
MB15E07L
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Input frequency vs. Input sensitivity (Prescaler = 64/65)
(dBm)
+10
Ta = +25°C
,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,
Input sensitivity (V fin)
0
SPEC
–10
–20
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
–30
–40
0
1000
3000 (MHz)
2000
Input frequency (fin)
Input frequency vs. Input sensitivity (Prescaler = 32/33)
(dBm)
+10
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
Input sensitivity (V fin)
0
Ta = +25°C
SPEC
–10
–20
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
–30
–40
0
1000
2000
Input frequency (fin)
14
3000 (MHz)
MB15E07L
2. OSCIN Input Sensitivity
(dBm)
+10
,,,,,,
,,,,,,
,,,,,,
Input frequency vs. Input sensitivity
SPEC
Input sensitivity (VOSC)
0
Ta = +25°C
–10
–20
–30
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
–40
0
50
100
150 (MHz)
Input frequency (fosc)
15
MB15E07L
3. DO Output Current
IOH vs. VOH
(V)
5.000
Ta = +25°C
VCC = 3.0 V
VP = 3.0 V, 5.0 V
VOH
.5000
/div
.0000
.0000
IDO
2.500/div
(mA)
IOH
IOL vs. VOL
(V)
5.000
Ta = +25°C
VCC = 3.0 V
VP = 3.0 V, 5.0 V
VOL
.5000
/div
.0000
.0000
IDO
2.500/div
IOL
16
(mA)
–25.00
–25.00
MB15E07L
4. fin Input Impedance
1; 10.715 Ω
–50.275 Ω
1 GHz
2; 11.118 Ω
–10.846 Ω
1.5 GHz
4
3
3; 16.718 Ω
20.081 Ω
2 GHz
4; 43.439 Ω
38.307 Ω
2.5 GHz
2
1
5. OSCIN Input Impedance
1;
4.656 kΩ
–19.064 kΩ
3 MHz
2;
704.75 Ω
–5.3735 kΩ
10 MHz
3;
388.25 Ω
–2.775 kΩ
20 MHz
4;
136.38 Ω
–1.5275 kΩ
40 MHz
4
1
2
3
17
MB15E07L
■ TEST CIRCUIT (FOR MEASURING INPUT SENSITIVITY fin/OSCIN)
VCC
VP
0.1 µF
1000 pF
1000 pF
0.1 µF
S•G
50 Ω
S•G
1000 pF
8
7
6
5
4
3
2
1
50 Ω
9 10 11 12 13 14 15 16
Oscilloscope
Controller
(setting divide ratio)
Note: SSOP-16 pin
18
VCC
MB15E07L
■ APPLICATION EXAMPLE
Output
LPF
VP
VCO
10 kΩ
12 kΩ
Lock detect.
12 kΩ
φR
16
φP
15
10 kΩ
LD/fout
14
From
a controller
ZC
13
PS
12
LE
11
Data
Clock
10
9
7
8
MB15E07L
1
2
3
OSCIN OSCOUT
4
VP
5
VCC
6
DO
GND
Xfin
1000 pF
fin
1000 pF
X’ tal
C1
C2
0.1 µF 0.1 µF
C1, C2: Depend on the crystal parameters
VP: 6V max.
Note: SSOP-16 pin
19
MB15E07L
■ ORDERING INFORMATION
20
Part number
Package
MB15E07LPFV1
16-pin, plastic SSOP
(FPT-16P-M05)
MB15E07LPV
16-pads, plastic BCC
(LCC-16P-M02)
Remarks
MB15E07L
■ PACKAGE DIMENSIONS
* : These dimensions do not include resin protrusion.
16-pin, plastic SSOP
(FPT-16P-M05)
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
INDEX
*4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
6.40±0.20
(.252±.008)
5.40(.213)
NOM
"A"
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
(Continued)
21
MB15E07L
(Continued)
16-pins, plastic BCC
(LCC-16P-M02)
4.55±0.10
(.179±.004)
14
* : These dimensions do not include resin protrusion.
3.40(.134)TYP
0.80(.032)MAX
9
(Mouting height)
0.65(.026)TYP
9
14
0.40±0.10
(.016±.004)
2.45(.096)
TYP
3.40±0.10
(.1339±.0039)
45˚
"A"
1.15(.045)TYP
"B"
0.80(.032)
TYP
1
E-MARK
6
0.40(.016)
0.325±0.10
(.013±.004)
6
0.085±0.04
(.003±.002)
(STAND OFF)
Details of "A" part
0.05(.002)
22
1996 FUJITSU LIMITED C16013S-1C-1
1
Details of "B" part
0.75±0.10
(.030±.004)
0.40±0.10
(.016±.004)
C
1.725(.068)
TYP
0.60±0.10
(.024±.004)
0.60±0.10
(.024±.004)
Dimensions in mm (inches)
MB15E07L
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. – Fri.: 7 am – 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http:.//www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
http://www.fmap.com.sg/
F9710
 FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
Printed in Japan
23