FUJITSU F126NB

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12610-3Ea
8-bit Microcontrollers
CMOS
F2MC-8FX MB95120MB series
MB95128MB/F124MB/F124NB/F124JB/F126MB/F126NB/
MB95F126JB/F128MB/F128NB/F128JB/FV100D-103
■ DESCRIPTION
The MB95120MB series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURE
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Main clock
• Main PLL clock
• Sub clock
• Sub PLL clock
• Timer
• 8/16-bit compound timer × 2 channels
• Can be used to interval timer, PWC timer, PWM timer and input capture.
• 16-bit reload timer × 1 channel
• 8/16-bit PPG × 2 channels
• 16-bit PPG × 2 channels
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://edevice.fujitsu.com/micom/en-support/
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2007.8
MB95120MB Series
(Continued)
• Timebase timer × 1 channel
• Watch prescaler × 1 channel
• LIN-UART × 1 channel
• LIN function, clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
• I2C* × 1 channel
• Built-in wake-up function
• External interrupt × 12 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
• 8/10-bit A/D converter × 12 channels
• 8-bit or 10-bit resolution can be selected
• LCD controller (LCDC)
• 40 SEG × 4 COM (Max 160 pixels)
• With blinking function
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port
• The number of maximum ports : Max 87
• Port configuration
• General-purpose I/O ports (N-ch open drain) : 2 ports
• General-purpose I/O ports (CMOS)
: 85 ports
• Programmable input voltage levels of port
Automotive input level / CMOS input level / hysteresis input level
• Dual operation Flash memory
• Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time.
• Flash memory security function
Protects the content of Flash memory (Flash memory device only)
*:
2
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
MB95120MB Series
■ MEMORY LINEUP
Flash memory
RAM
16 Kbytes
512 bytes
32 Kbytes
1 Kbyte
60 Kbytes
2 Kbytes
MB95F124MB
MB95F124NB
MB95F124JB
MB95F126MB
MB95F126NB
MB95F126JB
MB95F128MB
MB95F128NB
MB95F128JB
3
MB95120MB Series
■ PRODUCT LINEUP
Part number
MB95128MB
Parameter
Type
MB95F124MB
MB95F126MB
MB95F128MB
MB95F124NB
MB95F126NB
MB95F128NB
MASK ROM
product
Flash memory product
ROM capacity*1
60 Kbytes (Max)
RAM capacity*1
2 Kbytes (Max)
Option*2
Reset output
Peripheral functions
Yes/No
Yes
Clock system
No
Dual clock
Low voltage
detection reset
Yes/No
Clock supervisor
Yes/No
CPU functions
MB95F124JB
MB95F126JB
MB95F128JB
No
Yes
No
Yes
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
Data bit length
: 1, 8, and 16 bits
Minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 MHz)
Interrupt processing time
: 0.6 μs (at machine clock frequency 16.25 MHz)
Ports (Max 87 ports)
General-purpose I/O port (N-ch open drain)
: 2 ports
General-purpose I/O port (CMOS)
: 85 ports
Programmable input voltage levels of port :
Automotive input level / CMOS input level / hysteresis input level
Timebase timer
(1 channel)
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Watchdog timer
Reset generated cycle
At main oscillation clock 10 MHz
At sub oscillation clock 32.768 kHz
Wild register
Capable of replacing 3 bytes of ROM data
: Min 105 ms
: Min 250 ms
IC
(1 channel)
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
UART/SIO
(1 channel)
Data transfer capable in UART/SIO
Full duplex double buffer
Variable data length (5/6/7/8-bit), built-in baud rate generator
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN-UART
(1 channel)
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
LIN functions available as the LIN master or LIN slave.
2
8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
(12 channels)
(Continued)
4
MB95120MB Series
(Continued)
Part number
MB95128MB
Peripheral functions
Parameter
MB95F124MB
MB95F126MB
MB95F128MB
MB95F124NB
MB95F126NB
MB95F128NB
MB95F124JB
MB95F126JB
MB95F128JB
LCD controller
(LCDC)
COM output
: 4 (Max)
SEG output
: 40 (Max)
LCD drive power supply (bias) pin
: 4 (Max)
40 SEG × 4 COM
: 160 pixels can be displayed.
Duty LCD mode
Operable in LCD standby mode
With blinking function
Built-in division resistance for LCD drive
16-bit reload timer
(1 channel)
Two clock modes and two counter operating modes can be selected.
Square waveform output
Count clock : 7 internal clocks and external clock can be selected.
Counter operating mode : reload mode or one-shot mode can be selected.
Each channel of the timer can be used as “8-bit timer × 2 channels” or “16-bit timer ×
1 channel”.
8/16-bit compound
Built-in timer function, PWC function, PWM function, capture function and square
timer (2 channels)
waveform output
Count clock : 7 internal clocks and external clock can be selected.
16-bit PPG
(2 channels)
PWM mode or one-shot mode can be selected.
Counter operating clock : Eight selectable clock sources
Support for external trigger start
8/16-bit PPG
(2 channels)
Each channel of the PPG can be used as “8-bit PPG × 2 channels” or “16-bit PPG ×
1 channel”.
Counter operating clock : Eight selectable clock sources
Watch counter
Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s)
Counter value can be set from 0 to 63 (Capable of counting for 1 minute when selecting
clock source 1 second and setting counter value to 60) .
Watch prescaler
(1 channel)
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
External interrupt
(12 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected.)
Can be used to recover from standby modes.
Flash memory
Supports automatic programming, Embedded AlgorithmTM *3
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of write/erase cycles (Minimum) : 10000 times
Data retention time : 20 years
Erase can be performed on each block
Block protection with external programming voltage
Dual operation Flash memory
Flash Security Feature for protecting the content of the Flash
Standby mode
Sleep, stop, watch, and timebase timer
*1 : For ROM capacitance and RAM capacitance, refer to “■ MEMORY LINEUP”.
*2 : For details of option, refer to “■ MASK OPTION”.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
Note : Part number of evaluation product in MB95120MB series is MB95FV100D-103. When using it, the MCU
board (MB2146-303A) is required.
5
MB95120MB Series
■ OSCILLATION STABILIZATION WAIT TIME
The initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. The maximum
value is shown as follows.
Oscillation stabilization wait time
Remarks
(2 −2) /FCH
Approx. 4.10 ms (at main oscillation clock 4 MHz)
14
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
FPT-100P-M20
FPT-100P-M06
BGA-224P-M08
: Available
: Unavailable
6
MB95128MB
MB95F124MB/F124NB/F124JB
MB95F126MB/F126NB/F126JB
MB95F128MB/F128NB/F128JB
MB95FV100D103
MB95120MB Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
• Notes on Using Evaluation Products
The Evaluation product has not only the functions of the MB95120MB series but also those of other products
to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for
peripheral resources not used by the MB95120MB series are therefore access-barred. Read/write access to
these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting
in unexpected malfunctions of hardware or software.
Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are
used, the address may be read or written unexpectedly).
Also, as the read values of prohibited addresses on the evaluation product are different to the values on the
Flash memory and MASK ROM products, do not use these values in the program.
The Evaluation product do not support the functions of some bits in single-byte registers. Read/write access to
these bits does not cause hardware malfunctions. Since the Evaluation, Flash memory product, and MASK ROM
product are designed to behave completely the same way in terms of hardware and software.
• Difference of Memory Spaces
If the amount of memory on the Evaluation product is different from that of the Flash memory product or MASK
ROM product, carefully check the difference in the amount of memory from the model to be actually used when
developing software.
For details of memory space, refer to “■ CPU CORE”.
• Current Consumption
• The current consumption of Flash memory product is typically greater than for MASK ROM product.
• For details of current consumption, refer to “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, refer to “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage are different between the Evaluation, Flash memory products, and MASK ROM product.
For details of operating voltage, refer to “■ ELECTRICAL CHARACTERISTICS”.
7
MB95120MB Series
■ PIN ASSIGNMENT
VCC
P90/V3
P91/V2
P92/V1
P93/V0
P94
P95
PA0/COM0
PA1/COM1
PA2/COM2
PA3/COM3
PB0/SEG00
PB1/SEG01
PB2/SEG02
PB3/SEG03
PB4/SEG04
PB5/SEG05
PB6/SEG06
PB7/SEG07
PC0/SEG08
PC1/SEG09
PC2/SEG10
PC3/SEG11
PC4/SEG12
VCC
(TOP VIEW)
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VSS
C
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P50/SCL0
P51/SDA0
P52/PPG1
AVR
AVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP-100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PC5/SEG13
PC6/SEG14
PC7/SEG15
PD0/SEG16
PD1/SEG17
PD2/SEG18
PD3/SEG19
PD4/SEG20
PD5/SEG21
PD6/SEG22
PD7/SEG23
PE0/SEG24
PE1/SEG25
PE2/SEG26
PE3/SEG27
PE4/SEG28/INT10
PE5/SEG29/INT11
PE6/SEG30/INT12
PE7/SEG31/INT13
P60/SEG32/PPG10
P61/SEG33/PPG11
MOD
X0
X1
VSS
AVSS
P30/AN00
P31/AN01
P32/AN02
P33/AN03
P34/AN04
P35/AN05
P36/AN06
P37/AN07
P40/AN08
P41/AN09
P42/AN10
P43/AN11
P53/TRG1
P70/TO0
P71/TI0
P67/SEG39/SIN
P66/SEG38/SOT
P65/SEG37/SCK
P64/SEG36/EC1
P63/SEG35/TO11
P62/SEG34/TO10
RST
X0A
X1A
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M20)
(Continued)
8
MB95120MB Series
(Continued)
P92/V1
P93/V0
P94
P95
PA0/COM0
PA1/COM1
PA2/COM2
PA3/COM3
PB0/SEG00
PB1/SEG01
PB2/SEG02
PB3/SEG03
PB4/SEG04
PB5/SEG05
PB6/SEG06
PB7/SEG07
PC0/SEG08
PC1/SEG09
PC2/SEG10
PC3/SEG11
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
QFP-100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PC4/SEG12
VCC
PC5/SEG13
PC6/SEG14
PC7/SEG15
PD0/SEG16
PD1/SEG17
PD2/SEG18
PD3/SEG19
PD4/SEG20
PD5/SEG21
PD6/SEG22
PD7/SEG23
PE0/SEG24
PE1/SEG25
PE2/SEG26
PE3/SEG27
PE4/SEG28/INT10
PE5/SEG29/INT11
PE6/SEG30/INT12
PE7/SEG31/INT13
P60/SEG32/PPG10
P61/SEG33/PPG11
MOD
X0
X1
VSS
X1A
X0A
RST
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P31/AN01
P32/AN02
P33/AN03
P34/AN04
P35/AN05
P36/AN06
P37/AN07
P40/AN08
P41/AN09
P42/AN10
P43/AN11
P53/TRG1
P70/TO0
P71/TI0
P67/SEG39/SIN
P66/SEG38/SOT
P65/SEG37/SCK
P64/SEG36/EC1
P63/SEG35/TO11
P62/SEG34/TO10
P91/V2
P90/V3
VCC
VSS
C
P00/INT00
P01/INT01
P02/INT02
P03/INT03
P04/INT04
P05/INT05
P06/INT06
P07/INT07
P10/UI0
P11/UO0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
P50/SCL0
P51/SDA0
P52/PPG1
AVR
AVCC
AVSS
P30/AN00
(FPT-100P-M06)
9
MB95120MB Series
■ PIN DESCRIPTION
Pin no.
Pin name
I/O
circuit
type*3
Function
LQFP *1
QFP *2
1
4
VSS
⎯
Power supply pin (GND)
2
5
C
⎯
Capacitor connection pin
3
6
P00/INT00
4
7
P01/INT01
5
8
P02/INT02
6
9
P03/INT03
7
10
P04/INT04
C
General-purpose I/O port
The pins are shared with external interrupt input. Large
current port.
8
11
P05/INT05
9
12
P06/INT06
10
13
P07/INT07
11
14
P10/UI0
G
General-purpose I/O port
The pin is shared with UART/SIO ch.0 data input.
12
15
P11/UO0
13
16
P12/UCK0
14
17
P13/TRG0/
ADTG
15
18
P14/PPG0
16
19
P20/PPG00
17
20
P21/PPG01
18
21
P22/TO00
19
22
P23/TO01
20
23
P24/EC0
General-purpose I/O port
The pin is shared with 8/16-bit compound timer ch.0 clock
input.
21
24
P50/SCL0
General-purpose I/O port
The pin is shared with I2C ch.0 clock I/O.
General-purpose I/O port
The pin is shared with UART/SIO ch.0 data output.
General-purpose I/O port
The pin is shared with UART/SIO ch.0 clock I/O.
H
General-purpose I/O port
The pin is shared with 16-bit PPG ch.0 trigger input (TRG0)
and A/D converter trigger input (ADTG).
General-purpose I/O port
The pin is shared with 16-bit PPG ch.0 output.
General-purpose I/O port
The pins are shared with 8/16-bit PPG ch.0 output.
H
I
General-purpose I/O port
The pins are shared with 8/16-bit compound timer ch.0
output.
General-purpose I/O port
The pin is shared with I2C ch.0 data I/O.
22
25
P51/SDA0
23
26
P52/PPG1
H
General-purpose I/O port
The pin is shared with 16-bit PPG ch.1 output.
24
27
AVR
⎯
A/D converter reference input pin
25
28
AVCC
⎯
A/D converter power supply pin
(Continued)
10
MB95120MB Series
Pin no.
Pin name
I/O
circuit
type*3
⎯
A/D converter power supply pin (GND)
J
General-purpose I/O port
The pins are shared with A/D converter analog input.
J
General-purpose I/O port
The pins are shared with A/D converter analog input.
H
General-purpose I/O port
The pin is shared with 16-bit PPG ch.1 trigger input.
LQFP *1
QFP *2
26
29
AVSS
27
30
P30/AN00
28
31
P31/AN01
29
32
P32/AN02
30
33
P33/AN03
31
34
P34/AN04
32
35
P35/AN05
33
36
P36/AN06
34
37
P37/AN07
35
38
P40/AN08
36
39
P41/AN09
37
40
P42/AN10
38
41
P43/AN11
39
42
P53/TRG1
40
43
P70/TO0
H
Function
General-purpose I/O port
The pin is shared with 16-bit reload timer ch.0 output.
General-purpose I/O port
The pin is shared with 16-bit reload timer ch.0 input.
41
44
P71/TI0
42
45
P67/SEG39/
SIN
43
46
P66/SEG38/
SOT
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG38) and LINUART data output (SOT) .
44
47
P65/SEG37/
SCK
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG37) and LINUART clock I/O (SCK) .
45
48
P64/SEG36/
EC1
46
49
P63/SEG35/
TO11
47
50
P62/SEG34/
TO10
48
51
RST
49
52
X0A
50
53
X1A
51
54
VSS
N
M
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG39) and LINUART data input (SIN) .
General-purpose I/O port
The pin is shared with LCDC SEG output (SEG36) and
8/16-bit compound timer ch.1 clock input (EC1) .
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG34,
SEG35) and 8/16-bit compound timer ch.1 output (TO10,
TO11) .
B'
Reset pin
A
Sub clock oscillation pin (32 kHz)
⎯
Power supply pin (GND)
(Continued)
11
MB95120MB Series
Pin no.
Pin name
LQFP *1
QFP *2
52
55
X1
53
56
X0
54
57
MOD
55
58
P61/SEG33/
PPG11
56
59
P60/SEG32/
PPG10
57
60
PE7/SEG31/
INT13
58
61
PE6/SEG30/
INT12
59
62
PE5/SEG29/
INT11
60
63
PE4/SEG28/
INT10
61
64
PE3/SEG27
62
65
PE2/SEG26
63
66
PE1/SEG25
64
67
PE0/SEG24
65
68
PD7/SEG23
66
69
PD6/SEG22
67
70
PD5/SEG21
68
71
PD4/SEG20
69
72
PD3/SEG19
70
73
PD2/SEG18
71
74
PD1/SEG17
72
75
PD0/SEG16
73
76
PC7/SEG15
74
77
PC6/SEG14
75
78
PC5/SEG13
76
79
VCC
I/O
circuit
type*3
Function
A
Main clock oscillation pin
B
An operating mode designation pin
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG32,
SEG33) and 8/16-bit PPG ch.1 output (PPG10, PPG11) .
Q
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG28 to
SEG31) and external interrupt input (INT10 to INT13) .
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG24 to
SEG27) .
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG16 to
SEG23) .
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG13 to
SEG15) .
⎯
Power supply pin
(Continued)
12
MB95120MB Series
(Continued)
Pin no.
Pin name
LQFP *1
QFP *2
77
80
PC4/SEG12
78
81
PC3/SEG11
79
82
PC2/SEG10
80
83
PC1/SEG09
81
84
PC0/SEG08
82
85
PB7/SEG07
83
86
PB6/SEG06
84
87
PB5/SEG05
85
88
PB4/SEG04
86
89
PB3/SEG03
87
90
PB2/SEG02
88
91
PB1/SEG01
89
92
PB0/SEG00
90
93
PA3/COM3
91
94
PA2/COM2
92
95
PA1/COM1
93
96
PA0/COM0
94
97
P95
95
98
P94
96
99
P93/V0
97
100
P92/V1
98
1
P91/V2
99
2
P90/V3
100
3
VCC
I/O
circuit
type*3
Function
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG08 to
SEG12) .
M
General-purpose I/O port
The pins are shared with LCDC SEG output (SEG00 to
SEG07) .
M
General-purpose I/O port
The pins are shared with LCDC COM output (COM0 to
COM3) .
M
General-purpose I/O port
R
General-purpose I/O port
The pins are shared with power supply pins for LCDC
drive.
⎯
Power supply pin
*1 : FPT-100P-M20
*2 : FPT-100P-M06
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
13
MB95120MB Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1 (X1A)
A
Clock input
N-ch
X0 (X0A)
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• Low-speed side
Feedback resistance : approx. 10 MΩ
Standby control
B
Mode input
Reset input
B’
N-ch
• Only for input
• Hysteresis input
• Reset output
• Hysteresis input
Reset output
P-ch
Digital output
Digital output
• CMOS output
• Hysteresis input
• Automotive input
N-ch
C
Hysteresis input
Automotive input
Standby control
External interrupt
enable
Pull-up control
R
P-ch
P-ch
G
N-ch
Digital output
•
•
•
•
•
CMOS output
CMOS input
Hysteresis input
With pull-up control
Automotive input
Digital output
CMOS input
Standby control
Hysteresis input
Automotive input
(Continued)
14
MB95120MB Series
Type
Circuit
Remarks
Pull-up control
R
P-ch
P-ch
H
Digital output
•
•
•
•
CMOS output
Hysteresis input
With pull-up control
Automotive input
•
•
•
•
N-ch open drain output
CMOS input
Hysteresis input
Automotive input
•
•
•
•
•
CMOS output
Hysteresis input
Analog input
With pull-up control
Automotive input
•
•
•
•
CMOS output
LCD output
Hysteresis input
Automotive input
Digital output
N-ch
Hysteresis input
Automotive input
Standby control
N-ch
I
CMOS input
Hysteresis input
Automotive input
Standby control
R
P-ch
Pull-up control
P-ch
N-ch
J
Digital output
Digital output
Digital output
Analog input
Hysteresis input
Automotive input
A/D control
Standby control
P-ch
N-ch
M
Digital output
Digital output
LCD output
LCD control
Standby control
Hysteresis input
Automotive input
(Continued)
15
MB95120MB Series
(Continued)
Type
Circuit
P-ch
N-ch
N
Remarks
Digital output
Digital output
•
•
•
•
•
CMOS output
LCD output
CMOS input
Hysteresis input
Automotive input
•
•
•
•
CMOS output
LCD output
Hysteresis input
Automotive input
•
•
•
•
CMOS output
LCD power supply
Hysteresis input
Automotive input
LCD output
CMOS input
Hysteresis input
Automotive input
LCD control
Standby control
P-ch
N-ch
Q
Digital output
Digital output
LCD output
Hysteresis input
Automotive input
LCD control
Standby control
External
interrupt control
P-ch
N-ch
Digital output
Digital output
LCD built-in division
resistance I/O
R
Hysteresis input
LCD control
Standby control
16
Automotive input
MB95120MB Series
■ HANDLING DEVICES
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceeding
the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the VCC power-supply voltage.
For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range
(50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient
variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
PIN CONNECTION
• Treatment of Unused Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it open.
• Treatment of Power Supply Pins on A/D Converter
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use.
Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 μF ceramic capacitor
as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near
this device.
17
MB95120MB Series
• Mode Pin (MOD)
Connect the MOD pin directly to VCC or VSS pins.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the MOD pins to VCC or VSS pins and to provide a low-impedance connection.
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC pin
must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
CS
• Analog Power Supply
Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00
to AN11 pins.
18
MB95120MB Series
■ PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL
PROGRAMMER
• Supported Parallel Programmers and Adapters
The following table lists supported parallel programmers and adapters.
Package
Applicable adapter model
FPT-100P-M20
TEF110-95F128HSPFV
FPT-100P-M06
TEF110-95F128HSPF
Parallel programmers
AF9708 (Ver 02.35G or more)
AF9709/B (Ver 02.35G or more)
AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following:
Flash Support Group, Inc. TEL: +81-53-428-8380
• Sector Configuration
The individual sectors of Flash memory correspond to addresses used for CPU access and programming by
the parallel programmer as follows:
• MB95F128MB/F128NB/F128JB (60 Kbytes)
Flash memory
CPU address
Programmer address*
1000H
71000H
1FFFH
2000H
71FFFH
72000H
2FFFH
3000H
72FFFH
73000H
3FFFH
4000H
73FFFH
74000H
7FFFH
8000H
77FFFH
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA2 (4 Kbytes)
Lower bank
SA1 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
Upper bank
SA5 (16 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 71000H to 7FFFFH.
3) Programmed by parallel programmer
19
MB95120MB Series
• MB95F126MB/F126NB/F126JB (32 Kbytes)
Flash memory
CPU address
Programmer address*
8000H
78000H
BFFFH
C000H
7BFFFH
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA5 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 78000H to 7FFFFH.
3) Programmed by parallel programmer
• MB95F124MB/F124NB/F124JB (16 Kbytes)
Flash memory
CPU address
Programmer address*
C000H
7C000H
CFFFH
D000H
7CFFFH
7D000H
DFFFH
E000H
7DFFFH
7E000H
EFFFH
F000H
7EFFFH
7F000H
FFFFH
7FFFFH
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer
programs data into Flash memory.
These programmer addresses are used for the parallel programmer to program or erase data in Flash
memory.
• Programming Method
1) Set the type code of the parallel programmer to 17222.
2) Load program data to programmer addresses 7C000H to 7FFFFH.
3) Programmed by parallel programmer
20
MB95120MB Series
■ BLOCK DIAGRAM
2
F MC-8FX CPU
RST
X0/X1
X0A/X1A
ROM (60 Kbytes)
Reset control
RAM (2 Kbytes)
Clock control
Interrupt control
Watch prescaler
Wild register
Watch counter
P00/INT00 to P07/INT07
External interrupt ch.0 to ch.7
8 channels
8/16-bit PPG ch.1
1 channel
P60/SEG32/PPG10
P61/SEG33/PPG11
P10/UI0
P12/UCK0
P13/TRG0/ADTG
P14/PPG0
P20/PPG00
P21/PPG01
P22/TO00
P23/TO01
P24/EC0
UART/SIO
1 channel
16-bit PPG ch.0
1 channel
8/16-bit PPG ch.0
1 channel
8/16-bit compound
timer ch.0
1 channel
8/16-bit
compound timer ch.1
1 channel
Internal bus
P11/UO0
LIN-UART
1 channel
16-bit reload timer
1 channel
P30/AN00 to P37/AN07
P40/AN08 to P43/AN11
AVCC
AVSS
8/10-bit
A/D converter
12 channels
LCDC
AVR
P50/SCL0
P51/SDA0
P52/PPG1
P53/TRG1
I2C
1 channel
16-bit PPG ch.1
1 channel
Port
External interrupt ch.8 to ch.11
4 channels
P62/SEG34/TO10
P63/SEG35/TO11
P64/SEG36/EC1
P65/SEG37/SCK
P66/SEG38/SOT
P67/SEG39/SIN
P70/TO0
P71/TI0
P90/V3 to P93/V0
P94/P95
PA0/COM0 to PA3/COM3
PB0/SEG00 to PB7/SEG07
PC0/SEG08 to PC7/SEG15
PD0/SEG16 to PD7/SEG23
PE0/SEG24 to PE3/SEG27
PE4/SEG28/INT10
PE5/SEG29/INT11
PE6/SEG30/INT12
PE7/SEG31/INT13
Port
Other pins
MOD, VCC,Vss,C
21
MB95120MB Series
■ CPU CORE
1. Memory space
Memory space of the MB95120MB series is 64 Kbytes and consists of I/O area, data area, and program area.
The memory space includes special - purpose areas such as the general - purpose registers and vector table.
Memory map of the MB95120MB series is shown below.
• Memory Map
MB95F124MB/F124NB/F124JB
MB95F126MB/F126NB/F126JB
MB95F128MB/F128NB/F128JB
MB95128MB
0000H
0000H
I/O
0080H
0100H
I/O
0080H
RAM 2 Kbytes
0100H
Register
0200H
0880H
RAM
Register
0200H
Access
prohibited
Address #1
Extended I/O
1000H
0000H
I/O
0080H
0100H
0F80H
Extended I/O
1000H
Address #2
Flash memory
60 Kbytes
Flash memory
FFFFH
FFFFH
Register
Access
prohibited
Extended I/O
MASK ROM
60 Kbytes
RAM 3.75 Kbytes
0200H
0F80H
0F80H
MB95FV100D-103
FFFFH
Flash memory
RAM
Address #1
Address #2
16 Kbytes
512 bytes
0280H
C000H
32 Kbytes
1 Kbyte
0480H
8000H
60 Kbytes
2 Kbytes
0880H
1000H
MB95F124MB
MB95F124NB
MB95F124JB
MB95F126MB
MB95F126NB
MB95F126JB
MB95F128MB
MB95F128NB
MB95F128JB
22
MB95120MB Series
2. Register
The MB95120MB series has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The dedicated registers are as follows:
Program counter (PC)
: A 16-bit register to indicate locations where instructions are stored.
Accumulator (A)
: A 16-bit register for temporary storage of arithmetic operations. In the case of
an 8-bit data processing instruction, the lower 1 byte is used.
Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator.
In the case of an 8-bit data processing instruction, the lower 1 byte is used.
Index register (IX)
: A 16-bit register for index modification
Extra pointer (EP)
: A 16-bit pointer to point to a memory address.
Stack pointer (SP)
: A 16-bit register to indicate a stack area.
Program status (PS)
: A 16-bit register for storing a register bank pointer, a direct bank pointer, and
a condition code register
Initial Value
16-bit
PC
: Program counter
FFFDH
AH
AL
: Accumulator
0000H
TH
TL
: Temporary accumulator
0000H
IX
: Index register
0000H
EP
: Extra pointer
0000H
SP
: Stack pointer
0000H
PS
: Program status
0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer
(DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.)
• Structure of the program status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
PS
R4
R3
R2
RP
R1
R0
DP2
DP1
DP
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DP0
H
I
IL1
IL0
N
Z
V
C
CCR
23
MB95120MB Series
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
RP upper
"0"
Generated address
"0"
"0"
"0"
"0"
OP code lower
"0"
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080H to 00FFH.
Direct bank pointer (DP2 to DP0)
Specified address area
Mapping area
XXXB (no effect to mapping)
0000H to 007FH
0000H to 007FH (without mapping)
000B (initial value)
0080H to 00FFH (without mapping)
001B
0100H to 017FH
010B
0180H to 01FFH
011B
0080H to 00FFH
100B
0200H to 027FH
0280H to 02FFH
101B
0300H to 037FH
110B
0380H to 03FFH
111B
0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is cleared to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
Interrupt level
Priority
High
0
0
0
0
1
1
1
0
2
1
1
3
N flag
Z flag
V flag
C flag
24
IL0
Low (no interruption)
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
MB95120MB Series
The following general-purpose registers are provided:
General-purpose registers: 8-bit data storage registers
The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8
registers. Up to a total of 32 banks can be used on the MB95120MB series. The bank currently in use is indicated
by the register bank pointer (RP).8-register. Up to a total of 32 banks can be used on the MB95120MB series.
The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates
the general-purpose register 0 (R0) to general-purpose register 7 (R7).
• Register Bank Configuration
8-bit
1F8H
This address = 0100H + 8 × (RP)
Address 100H
R0
R0
R0
R1
R2
R3
R4
R5
107H
R6
R1
R2
R3
R4
R5
R6
R1
R2
R3
R4
R5
R6
1FFH
R7
R7
R7
Bank 0
Memory area
Bank 31
32 banks
32 banks (RAM area)
The number of banks is
limited by the usable RAM
capacitance.
25
MB95120MB Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(Disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
1010X011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
⎯
(Disabled)
⎯
⎯
000EH
PDR2
Port 2 data register
R/W
00000000B
000FH
DDR2
Port 2 direction register
R/W
00000000B
0010H
PDR3
Port 3 data register
R/W
00000000B
0011H
DDR3
Port 3 direction register
R/W
00000000B
0012H
PDR4
Port 4 data register
R/W
00000000B
0013H
DDR4
Port 4 direction register
R/W
00000000B
0014H
PDR5
Port 5 data register
R/W
00000000B
0015H
DDR5
Port 5 direction register
R/W
00000000B
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
PDR7
Port 7 data register
R/W
00000000B
0019H
DDR7
Port 7 direction register
R/W
00000000B
001AH,
001BH
⎯
(Disabled)
⎯
⎯
001CH
PDR9
Port 9 data register
R/W
00000000B
001DH
DDR9
Port 9 direction register
R/W
00000000B
001EH
PDRA
Port A data register
R/W
00000000B
001FH
DDRA
Port A direction register
R/W
00000000B
0020H
PDRB
Port B data register
R/W
00000000B
0021H
DDRB
Port B direction register
R/W
00000000B
0022H
PDRC
Port C data register
R/W
00000000B
(Continued)
26
MB95120MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
0023H
DDRC
Port C direction register
R/W
00000000B
0024H
PDRD
Port D data register
R/W
00000000B
0025H
DDRD
Port D direction register
R/W
00000000B
0026H
PDRE
Port E data register
R/W
00000000B
0027H
DDRE
Port E direction register
R/W
00000000B
0028H
to
002CH
⎯
(Disabled)
⎯
⎯
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
PUL2
Port 2 pull-up register
R/W
00000000B
002FH
PUL3
Port 3 pull-up register
R/W
00000000B
0030H
PUL4
Port 4 pull-up register
R/W
00000000B
0031H
PUL5
Port 5 pull-up register
R/W
00000000B
0032H
PUL7
Port 7 pull-up register
R/W
00000000B
0033H
to
0035H
⎯
(Disabled)
⎯
⎯
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
003AH
PC01
8/16-bit PPG1 control register ch.0
R/W
00000000B
003BH
PC00
8/16-bit PPG0 control register ch.0
R/W
00000000B
003CH
PC11
8/16-bit PPG1 control register ch.1
R/W
00000000B
003DH
PC10
8/16-bit PPG0 control register ch.1
R/W
00000000B
003EH
TMCSRH0
16-bit reload timer control status register (upper byte) ch.0
R/W
00000000B
003FH
TMCSRL0
16-bit reload timer control status register (lower byte) ch.0
R/W
00000000B
0040H,
0041H
⎯
(Disabled)
⎯
⎯
0042H
PCNTH0
16-bit PPG status control register (upper byte) ch.0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register (lower byte) ch.0
R/W
00000000B
0044H
PCNTH1
16-bit PPG status control register (upper byte) ch.1
R/W
00000000B
0045H
PCNTL1
16-bit PPG status control register (lower byte) ch.1
R/W
00000000B
0046H,
0047H
⎯
(Disabled)
⎯
⎯
0048H
EIC00
External interrupt circuit control register ch.0/ch.1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
(Continued)
27
MB95120MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
EIC01
External interrupt circuit control register ch.8/ch.9
R/W
00000000B
004DH
EIC11
External interrupt circuit control register ch.10/ch.11
R/W
00000000B
004EH,
004FH
⎯
(Disabled)
⎯
⎯
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART reception/transmission data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch.0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch.0
R/W
00100000B
0058H
SSR0
UART/SIO serial status register ch.0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch.0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch.0
R
00000000B
005BH
to
005FH
⎯
(Disabled)
⎯
⎯
0060H
IBCR00
I2C bus control register 0 ch.0
R/W
00000000B
0061H
IBCR10
I2C bus control register 1 ch.0
R/W
00000000B
0062H
IBSR0
I2C bus status register ch.0
R
00000000B
I C data register ch.0
R/W
00000000B
0063H
2
IDDR0
2
0064H
IAAR0
I C address register ch.0
R/W
00000000B
0065H
ICCR0
I2C clock control register ch.0
R/W
00000000B
0066H
to
006BH
⎯
(Disabled)
⎯
⎯
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower byte)
R/W
00000000B
0070H
WCSR
Watch counter status register
R/W
00000000B
0071H
⎯
(Disabled)
⎯
⎯
0072H
FSR
Flash memory status register
R/W
000X0000B
(Continued)
28
MB95120MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
0073H
SWRE0
Flash memory sector writing control register 0
R/W
00000000B
0074H
SWRE1
Flash memory sector writing control register 1
R/W
00000000B
0075H
⎯
(Disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
Register bank pointer (RP) ,
Mirror of direct bank pointer (DP)
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(Disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(Disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control register
ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
(Continued)
29
MB95120MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control register
ch.1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG1 cycle setting buffer register ch.0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG0 cycle setting buffer register ch.0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG1 duty setting buffer register ch.0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG0 duty setting buffer register ch.0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG1 cycle setting buffer register ch.1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG0 cycle setting buffer register ch.1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG1 duty setting buffer register ch.1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG0 duty setting buffer register ch.1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG start register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output inversion register
R/W
00000000B
0FA6H
TMRH0/
TMRLRH0
16-bit reload timer timer/reload register (upper byte) ch.0
R/W
00000000B
0FA7H
TMRL0/
TMRLRL0
16-bit reload timer timer/reload register (lower byte) ch.0
R/W
00000000B
0FA8H,
0FA9H
⎯
(Disabled)
⎯
⎯
0FAAH
PDCRH0
16-bit PPG down counter register (upper byte) ch.0
R
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (lower byte) ch.0
R
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (upper byte) ch.0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (lower byte) ch.0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (upper byte) ch.0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (lower byte) ch.0
R/W
11111111B
0FB0H
PDCRH1
16-bit PPG down counter register (upper byte) ch.1
R
00000000B
0FB1H
PDCRL1
16-bit PPG down counter register (lower byte) ch.1
R
00000000B
0FB2H
PCSRH1
16-bit PPG cycle setting buffer register (upper byte) ch.1
R/W
11111111B
0FB3H
PCSRL1
16-bit PPG cycle setting buffer register (lower byte) ch.1
R/W
11111111B
0FB4H
PDUTH1
16-bit PPG duty setting buffer register (upper byte) ch.1
R/W
11111111B
0FB5H
PDUTL1
16-bit PPG duty setting buffer register (lower byte) ch.1
R/W
11111111B
0FB6H
to
0FBBH
⎯
(Disabled)
⎯
⎯
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator
prescaler select register ch.0
R/W
00000000B
(Continued)
30
MB95120MB Series
Address
Register
abbreviation
Register name
R/W
Initial value
0FBFH
BRSR0
UART/SIO dedicated baud rate generator
baud rate setting register ch.0
R/W
00000000B
0FC0H,
0FC1H
⎯
(Disabled)
⎯
⎯
0FC2H
AIDRH
A/D input disable register (upper byte)
R/W
00000000B
0FC3H
AIDRL
A/D input disable register (lower byte)
R/W
00000000B
0FC4H
LCDCC
LCDC control register
R/W
00010000B
0FC5H
LCDCE1
LCDC enable register 1
R/W
00110000B
0FC6H
LCDCE2
LCDC enable register 2
R/W
00000000B
0FC7H
LCDCE3
LCDC enable register 3
R/W
00000000B
0FC8H
LCDCE4
LCDC enable register 4
R/W
00000000B
0FC9H
LCDCE5
LCDC enable register 5
R/W
00000000B
0FCAH
LCDCE6
LCDC enable register 6
R/W
00000000B
0FCBH
LCDCB1
LCDC blinking setting register 1
R/W
00000000B
0FCCH
LCDCB2
LCDC blinking setting register 2
R/W
00000000B
0FCDH
to
0FE0H
LCDRAM
LCDC display RAM
R/W
00000000B
0FE1H,
0FE2H
⎯
(Disabled)
⎯
⎯
0FE3H
WCDR
Watch counter data register
R/W
00111111B
0FE4H,
0FE5H
⎯
(Disabled)
⎯
⎯
0FE6H
ILSR3
Input level select register 3
R/W
00000000B
0FE7H
ILSR2
Input level select register 2
R/W
00000000B
0FE8H,
0FE9H
⎯
(Disabled)
⎯
⎯
0FEAH
CSVCR
Clock supervisor control register
R/W
00011100B
0FEBH
to
0FEDH
⎯
(Disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin select circuit control register
R/W
01000000B
0FF0H
to
0FFFH
⎯
(Disabled)
⎯
⎯
(Continued)
31
MB95120MB Series
(Continued)
• R/W access symbols
R/W : Readable/Writable
R
: Read only
W
: Write only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
32
MB95120MB Series
■ INTERRUPT SOURCE TABLE
Interrupt source
Interrupt
request
number
Vector table address
Same level
Bit name of
priority order
interrupt level
(at simultaneous
setting register
occurrence)
Upper
Lower
IRQ0
FFFAH
FFFBH
L00 [1 : 0]
IRQ1
FFF8H
FFF9H
L01 [1 : 0]
IRQ2
FFF6H
FFF7H
L02 [1 : 0]
IRQ3
FFF4H
FFF5H
L03 [1 : 0]
UART/SIO ch.0
IRQ4
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit compound timer ch.0 (Lower)
IRQ5
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit compound timer ch.0 (Upper)
IRQ6
FFEEH
FFEFH
L06 [1 : 0]
LIN-UART (reception)
IRQ7
FFECH
FFEDH
L07 [1 : 0]
LIN-UART (transmission)
IRQ8
FFEAH
FFEBH
L08 [1 : 0]
8/16-bit PPG ch.1 (Lower)
IRQ9
FFE8H
FFE9H
L09 [1 : 0]
8/16-bit PPG ch.1 (Upper)
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
16-bit reload timer ch.0
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
8/16-bit PPG ch.0 (Upper)
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
8/16-bit PPG ch.0 (Lower)
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
8/16-bit compound timer ch.1 (Upper)
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
16-bit PPG ch.0
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
I2C ch.0
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
16-bit PPG ch.1
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler/watch counter
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit compound timer ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
External interrupt ch.0
External interrupt ch.4
External interrupt ch.1
External interrupt ch.5
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
High
External interrupt ch.8
External interrupt ch.9
External interrupt ch.10
External interrupt ch.11
Low
33
MB95120MB Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
Vcc
AVcc
Vss − 0.3
Vss + 6.0
AVR
Vss − 0.3
Vss + 6.0
V0 to V3
VSS − 0.3
VSS + 6.0
V
*3
Input voltage*1
VI
Vss − 0.3
Vss + 6.0
V
*4
Output voltage*1
VO
Vss − 0.3
Vss + 6.0
V
*4
ICLAMP
− 2.0
+ 2.0
mA
Applicable to pins*5
Σ|ICLAMP|
⎯
20
mA
Applicable to pins*5
1
Power supply voltage*
Power supply voltage for
LCD
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
IOL1
IOL2
⎯
IOLAV1
“L” level average
current
“L” level total average
output current
“H” level maximum
output current
⎯
mA
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
“H” level average
current
⎯
− 15
− 15
mA
−4
⎯
mA
−8
IOHAV2
“H” level total average
output current
mA
12
IOHAV1
“H” level total maximum
output current
15
*2
*2
4
IOLAV2
“L” level total maximum
output current
15
V
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
Other than P00 to P07
P00 to P07
Other than P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
P00 to P07
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total of pins)
(Continued)
34
MB95120MB Series
(Continued)
Parameter
Symbol
Rating
Min
Max
Unit
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
− 40
+ 105
°C
Tstg
− 55
+ 150
°C
Storage temperature
Remarks
*1 : The parameter is based on AVSS = VSS = 0.0 V.
*2 : Apply equal potential to AVcc and Vcc. AVR should not exceed AVcc + 0.3 V.
*3 : V0 to V3 should not exceed VCC + 0.3 V.
*4 : VI and Vo should not exceed VCC + 0.3 V. VI must not exceed the rating voltage. However, if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*5 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53
• Use within recommended operating conditions.
• Use at DC voltage (current).
• +B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting
resistance placed between the + B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current
to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this affects
other devices.
• Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+B signal input.
• Sample recommended circuits :
• Input/Output Equivalent circuits
Protective diode
+ B input (0 V to 16 V)
Vcc
Limiting
resistance
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB95120MB Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Condition
Value
Min
Max
2.42*1,*2
5.5*1
Unit
Remarks
In normal operating
Hold condition in
STOP mode
Other than
MB95FV100D-103
2.3
5.5
2.7
5.5
2.3
5.5
VSS
VCC
V
AVR
4.0
AVCC
V
Smoothing
capacitor
CS
0.1
1.0
μF
*3
Operating
temperature
TA
− 40
+ 105
°C
Other than MB95FV100D-103
+5
+ 35
°C
MB95FV100D-103
Power supply
voltage
Power supply
voltage for LCD
A/D converter
reference
input voltage
VCC,
AVCC
V0 to V3
⎯
V
In normal operating
Hold condition in
STOP mode
MB95FV100D-103
The range of liquid crystal power supply
(The optimal value depends on liquid
crystal display elements used.)
*1 : The values vary with the operating frequency, machine clock or analog guarantee range.
*2 : The value is 2.88 V when the low voltage detection reset is used.
*3 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC
pin must have a capacitor value higher than CS. For connection of smoothing capacitor CS, refer to the diagram
below.
• C pin connection diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
36
MB95120MB Series
3. DC Characteristics
Parameter
“H” level input
voltage
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
CondiSymbol
Pin name
Unit
Remarks
tion
Min
Typ
Max
Hysteresis input
P10 (selectable at UI0) ,
⎯
0.7 VCC
⎯ VCC + 0.3 V
(When selecting
VIH1
P67 (selectable at SIN)
CMOS input level)
P50, P51
VIH2
⎯ VSS + 5.5 V
⎯
0.7 VCC
(selectable at I2C)
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
Port inputs if AutoP90 to P95,
⎯
0.8 VCC
VIHA
⎯ VCC + 0.3 V motive input levels
PA0 to PA3,
are selected
PB0 to PB7,
PC0 to PC7,
PD0 to PD7,
PE0 to PE7
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P90 to P95,
⎯
0.8 VCC
VIHS1
⎯ VCC + 0.3 V Hysteresis input
PA0 to PA3,
PB0 to PB7,
PC0 to PC7,
PD0 to PD7,
PE0 to PE7
⎯
0.8 VCC
⎯ VSS + 5.5 V
VIHS2 P50, P51
CMOS input
⎯ VCC + 0.3 V
(Flash memory
⎯
0.7 VCC
product)
RST, MOD
VIHM
Hysteresis input
(MASK ROM
⎯ VCC + 0.3 V
⎯
0.8 VCC
product)
VIL
“L” level input
voltage
VILA
P10 (selectable at UI0) ,
P50, P51
(selectable at I2C)
P67 (selectable at SIN)
P00 to P07, P10 to P14,
P20 to P24, P30 to P37,
P40 to P43, P50 to P53,
P60 to P67, P70, P71,
P90 to P95,
PA0 to PA3,
PB0 to PB7,
PC0 to PC7,
PD0 to PD7,
PE0 to PE7
⎯
VSS − 0.3
⎯
0.3 VCC
V
Hysteresis input
(When selecting
CMOS input level)
⎯
VSS − 0.3
⎯
0.5 VCC
V
Port inputs if
Automotive input
levels are selected
(Continued)
37
MB95120MB Series
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
VILS
“L” level input
voltage
VILM
Open-drain
output
application
voltage
Pin name
P00 to P07
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P50 to P53,
P60 to P67,
P70, P71,
P90 to P95,
PA0 to PA3,
PB0 to PB7,
PC0 to PC7,
PD0 to PD7,
PE0 to PE7
Condition
Value
Unit
Typ
Max
⎯
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
⎯
VSS − 0.3
⎯
0.3 VCC
V
CMOS input
(Flash memory
product)
RST, MOD
⎯
VSS − 0.3
⎯
0.2 VCC
V
⎯
VD1
P50, P51
VSS − 0.3
⎯
VSS + 5.5
V
“H” level output
voltage
VOH1
Output pin other
IOH = − 4.0 mA Vcc − 0.5
than P00 to P07
⎯
⎯
V
VOH2
P00 to P07
IOH = − 8.0 mA Vcc − 0.5
⎯
⎯
V
“L” level output
voltage
VOL1
Output pin other
than P00 to
IOL = 4.0 mA
P07, RST*1
⎯
⎯
0.4
V
VOL2
P00 to P07
IOL = 12 mA
⎯
⎯
0.4
V
Port other than
P50, P51
0.0 V < VI <
VCC
−5
⎯
+5
μA
P50, P51
0.0 V < VI <
VSS + 5.5 V
⎯
⎯
5
μA
Input leakage
current (Hi-Z
output leakage
current)
ILI
Open-drain
output leakage
current
ILIOD
Remarks
Min
Hysteresis input
(MASK ROM
product)
When the pull-up
prohibition setting
(Continued)
38
MB95120MB Series
(VCC = AVCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin name
P10 to P14,
P20 to P24,
P30 to P37,
P40 to P43,
P52, P53,
P70, P71
Pull-up
resistor
RPULL
Pull-down
resistor
RMOD MOD
Input
capacitance
CIN
Condition
Value
Min
Unit
Remarks
VI = 0.0 V
25
50
100
kΩ
VI = VCC
50
100
200
kΩ
MASK ROM
product only
⎯
5
15
pF
Other than AVCC,
AVSS, AVR, VCC, f = 1 MHz
VSS
FCH = 20 MHz
FMP = 10 MHz
Main clock mode
(divided by 2)
ICC
Max
When the pullup
permission setting
⎯
Power supply
current*2
Typ
VCC
(External clock
operation)
12.5
Flash memory
product
mA (at Flash
memory writing
and erasing)
⎯
30.0
35.0
⎯
7.2
9.5
⎯
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
9.5
Flash memory
product
(at other than
mA
Flash memory
writing and
erasing)
15.2
mA
MASK ROM
product
20.0
Flash memory
product
(at other than
mA
Flash memory
writing and
erasing)
⎯
35.7
42.5
Flash memory
product
mA (at Flash
memory writing
and erasing)
⎯
11.6
15.2
mA
MASK ROM
product
(Continued)
39
MB95120MB Series
(VCC = AVCC = 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin name
Condition
Value
Unit Remarks
Min
Typ
Max
FCH = 20 MHz
FMP = 10 MHz
Main Sleep mode
(divided by 2)
⎯
4.5
7.5
mA
FCH = 32 MHz
FMP = 16 MHz
Main Sleep mode
(divided by 2)
⎯
7.2
12.0
mA
ICCL
FCL = 32 kHz
FMPL = 16 kHz
Sub clock mode
(divided by 2)
⎯
45
100
μA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Sub sleep mode
(divided by 2)
⎯
10
81
μA
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25 °C
⎯
4.6
27.0
μA
FCH = 4 MHz
FMP = 10 MHz
Main PLL mode
(multiplied by 2.5)
⎯
9.3
12.5
Flash
mA memory
product
⎯
7.0
9.5
MASK
mA ROM
product
FCH = 6.4 MHz
FMP = 16 MHz
Main PLL mode
(multiplied by 2.5)
⎯
14.9
20.0
Flash
mA memory
product
⎯
11.2
15.2
MASK
mA ROM
product
ICCS
VCC
(External clock
operation)
Power supply
current*2
ICCT
ICCMPLL
(Continued)
40
MB95120MB Series
(Continued)
(VCC = AVCC = 5.0 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin name
ICCSPLL
ICTS
Power supply
current*2
VCC
(External clock
operation)
ICCH
IA
AVCC
IAH
Condition
Value
Unit Remarks
Min
Typ
Max
FCL = 32 kHz
FMPL = 128 kHz
Sub PLL mode
(multiplied by 4) ,
TA = + 25 °C
⎯
160
400
μA
FCH = 10 MHz
Timebase timer mode
TA = + 25 °C
⎯
0.40
1.10
mA
Sub stop mode
TA = + 25 °C
⎯
3.5
20
μA
FCH = 16 MHz
At operating of A/D
conversion
⎯
2.4
4.7
mA
FCH = 16 MHz
At stopping of A/D
conversion
TA = + 25 °C
⎯
1
5
μA
Between V3 and VSS
⎯
300
⎯
kΩ
V1 to V3 = 3.6 V
⎯
⎯
5
kΩ
LCD internal
division
resistance
RLCD
⎯
COM0 to
COM3 output
impedance
RVCOM
COM0 to COM3
SEG00 to
SEG39 output
impedance
RVSEG
SEG00 to SEG39
⎯
⎯
⎯
7
kΩ
LCD leak
current
ILCDL
V0 to V3,
COM0 to COM3
SEG00 to SEG39
⎯
−1
⎯
+1
μA
*1 : Product without clock supervisor only.
*2 : • The power-supply current is determined by the external clock. When both low voltage detection option and
clock supervisor are selected, the power-supply current will be a value of adding current consumption of the
low voltage detection circuit (ILVD) and current consumption of built-in CR oscillator (ICSV) to the specified value.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
41
MB95120MB Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.42 V to 5.5 V, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
SymCondiPin name
bol
tion
FCH
X0, X1
Clock frequency
FCL
X0, X1
Clock cycle time
Input clock pulse width
Input clock rise time and
fall time
42
Unit
Remarks
16.25
MHz
When using main
oscillation circuit
⎯
32.50
MHz When using external clock
3.00
⎯
10.00
MHz Main PLL multiplied by 1
3.00
⎯
8.13
MHz Main PLL multiplied by 2
3.00
⎯
6.50
MHz Main PLL multiplied by 2.5
3.00
⎯
4.06
MHz Main PLL multiplied by 4
⎯
32.768
⎯
kHz
When using sub
oscillation circuit
⎯
32.768
⎯
kHz
When using sub PLL
VCC = 2.3 V to 3.6 V
61.5
⎯
1000
ns
When using main oscillation circuit
30.8
⎯
1000
ns
When using external clock
Min
Typ
Max
1.00
⎯
1.00
X0A, X1A
⎯
tHCYL
Value
tLCYL
X0A, X1A
⎯
30.5
⎯
μs
When using sub oscillation circuit
tWH1
tWL1
X0
61.5
⎯
⎯
ns
tWH2
tWL2
X0A
⎯
15.2
⎯
μs
When using external clock
Duty ratio is about 30% to
70%.
tCR
tCF
X0, X0A
⎯
⎯
5
ns
When using external clock
MB95120MB Series
• Input wave form for using external clock (main clock)
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Main Clock Input Port External Connection
When using a crystal or
ceramic oscillator
When using external clock
Microcontroller
Microcontroller
X0
X1
X0
X1
Open
FCH
FCH
C1
C2
• Input wave form for using external clock (sub clock)
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of Sub clock Input Port External Connection
When using a crystal or
ceramic oscillator
Microcontroller
X0A
X1A
When using external clock
Microcontroller
X0A
FCL
X1A
Open
FCL
C1
C2
43
MB95120MB Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Condition
Value
Min
61.5
Source clock cycle time*
(Clock before setting
division)
Max
2000
Unit
ns
When using main clock
Min : FCH = 8.125 MHz,
PLL multiplied by 2
Max : FCH = 1 MHz, divided by 2
μs
When using sub clock
Min : FCL = 32 kHz,
PLL multiplied by 4
Max : FCL = 32 kHz, divided by 2
1
Source clock frequency
Machine clock cycle time*2
(Minimum instruction
execution time)
Machine clock frequency
Remarks
tSCLK
7.6
61.0
0.50
16.25
MHz When using main clock
16.384
131.072
kHz When using sub clock
61.5
32000
ns
When using main clock
Min : FSP = 16.25 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
7.6
976.5
μs
When using sub clock
Min : FSPL = 131 kHz, no division
Max : FSPL = 16 kHz, divided by 16
FMP
0.031
16.250
MHz When using main clock
FMPL
1.024
131.072
kHz When using sub clock
FSP
⎯
FSPL
tMCLK
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
• Sub clock divided by 2
• PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
• Outline of clock generation block
FCH
(main oscillation)
Divided by 2
Main PLL
×1
×2
× 2.5
×4
SCLK
(source clock)
FCL
(sub oscillation)
Divided by 2
Sub PLL
×2
×3
×4
44
Clock mode select bit
(SYCC: SCS1, SCS0)
Division
circuit
×1
× 1/4
× 1/8
× 1/16
MCLK
(machine clock)
MB95120MB Series
• Operating voltage - Operating frequency (TA = − 40 °C to + 105 °C)
• MB95F124MB/F124NB/F124JB/F126MB/F126NB/F126JB/F128MB/F128NB/F128JB
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and watch
mode operation guarantee range
5.5
2.42
16.384 kHz
32 kHz
131.072 kHz
Operating voltage (V)
Operating voltage (V)
5.5
3.5
2.42
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
Source clock frequency (FSPL)
• Operating voltage - Operating frequency (TA = + 5 °C to + 35 °C)
• MB95FV100D-103
Main clock mode and main PLL mode
operation guarantee range
Sub PLL, sub clock mode and
watch mode operation guarantee range
5.5
2.7
16.384 kHz
32 kHz
131.072 kHz
PLL operation guarantee range
Source clock frequency (FSPL)
Operating voltage (V)
Operating voltage (V)
5.5
3.5
2.7
0.5MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
Main clock operation guarantee range
Source clock frequency (FSP)
45
MB95120MB Series
• Main PLL operation frequency
[MHz]
16.25
16
15
×4
12
Source clock frequency (Fsp)
× 2.5
10
×1
×2
7.5
6
5
3
0
3
4 4.062
5
6.4 6.5
Machine clock frequency (FMP)
46
8 8.125
10
[MHz]
MB95120MB Series
(3) External Reset
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
RST “L” level
pulse width
tRSTL
Pin
name
RST
Value
Condition
⎯
Min
Max
2 tMCLK*1
⎯
Oscillation time of
oscillator*2 + 100
⎯
100
⎯
Unit
Remarks
ns
At normal operating
μs
At stop mode, sub clock mode,
sub sleep mode, and watch mode
At timebase timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the
oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between
hundreds of μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
tRSTL
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal
operating
clock
100 μs
Oscillation time
Oscillation stabilization wait time
of oscillator
Execute instruction
Internal reset
47
MB95120MB Series
(4) Power-on Reset
(AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Power supply rising time
tR
Power supply cutoff time
tOFF
Pin name
VCC
tR
Condition
Value
Unit
Min
Max
⎯
⎯
50
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.3 V
Hold Condition in stop mode
VSS
48
MB95120MB Series
(5) Peripheral Input Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Peripheral input “H” pulse width
Peripheral input “L” pulse width
Symbol
tILIH
tIHIL
Pin name
Condition
INT00 to INT07,
INT10 to INT13,
EC0, EC1, TI0,
TRG0/ADTG,
TRG1
Value
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
⎯
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
INT10 to INT13, EC0, EC1,
TI0, TRG0/ADTG, TRG1
tIHIL
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
49
MB95120MB Series
(6) UART/SIO, Serial I/O Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Value
Condition
Max
4 tMCLK*
⎯
ns
− 190
+190
ns
2 tMCLK*
⎯
ns
UCK0, UI0
2 tMCLK*
⎯
ns
tSHSL
UCK0
4 tMCLK*
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK0
4 tMCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
UCK0, UO0
0
190
ns
Valid UI → UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
⎯
ns
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
⎯
ns
Internal clock
operation output pin :
CL = 80 pF + 1TTL.
External clock
operation output pin :
CL = 80 pF + 1TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
UCK0
2.4 V
0.8 V
0.8 V
tSLOV
UO0
UI0
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK0
0.2 VCC 0.2 VCC
tSLOV
UO0
UI0
50
Unit
Min
2.4 V
0.8 V
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
MB95120MB Series
(7) LIN-UART Timing
Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
SymPin name
bol
tSCYC
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
Value
Condition
Max
5 tMCLK*3
⎯
ns
−95
+95
ns
⎯
ns
0
⎯
ns
3 tMCLK*3 − tR
⎯
ns
* + 95
⎯
ns
SCK
Internal clock
SCK, SOT
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
SCK
SCK
SCK ↓ → SOT delay time
tSLOVE SCK, SOT
Valid SIN → SCK ↑
tIVSHE
SCK ↑ → valid SIN hold time
tSHIXE
External clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
* + 190
MCLK 3
t
t
MCLK 3
⎯
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
51
MB95120MB Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
SCK
0.8 VCC
0.2 VCC
tF
SOT
tSHSL
0.8 VCC
0.2 VCC
tR
tSLOVE
2.4 V
0.8 V
tIVSHE
SIN
tSHIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
52
0.8 VCC
MB95120MB Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Value
Condition
Internal clock
operation output pin :
SCK, SIN CL = 80 pF + 1 TTL.
SCK, SIN
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+95
ns
⎯
ns
0
⎯
ns
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
SCK
3 tMCLK*3 − tR
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
⎯
ns
SCK, SOT
⎯
SCK ↑ → SOT delay time
tSHOVE
Valid SIN → SCK ↓
tIVSLE
SCK ↓ → valid SIN hold time
tSLIXE
External clock
SCK, SIN operation output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
* + 190
MCLK 3
t
* + 95
MCLK 3
ns
190
⎯
ns
tMCLK*3 + 95
⎯
ns
2t
SCK fall time
tF
SCK
⎯
10
ns
SCK rise time
tR
SCK
⎯
10
ns
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
53
MB95120MB Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
SCK
0.8 VCC
tSLSH
0.8 VCC
0.2 VCC
tR
SOT
0.2 VCC
tF
tSHOVE
2.4 V
0.8 V
tIVSLE
SIN
tSLIXE
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
54
0.2 VCC
MB95120MB Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Parameter
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Value
Condition
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
t
Unit
Min
Max
5 tMCLK*3
⎯
ns
−95
+95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
SIN
0.8 V
tSHOVI
tSOVLI
0.8 VCC
0.2 VCC
tSLIXI
0.8 VCC
0.2 VCC
55
MB95120MB Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Parameter
Value
Condition
Unit
Min
Max
SCK
5 tMCLK*3
⎯
ns
SCK, SOT
−95
+95
ns
⎯
ns
0
⎯
ns
⎯
4 tMCLK*3
ns
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Internal clock
SCK, SIN operating output pin :
CL = 80 pF + 1 TTL.
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
SCK, SOT
t
* + 190
MCLK 3
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
serial clock.
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
tIVSHI
SIN
56
tSLOVI
2.4 V
0.8 V
tSHIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB95120MB Series
(8) I2C Timing
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40 °C to + 105 °C)
Value
Parameter
Symbol
SCL clock frequency
Pin
name
Condition
Standard-mode
Fast-mode
Min
Max
Min
Max
Unit
fSCL
SCL0
0
100
0
400
kHz
tHD;STA
SCL0
SDA0
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
tLOW
SCL0
4.7
⎯
1.3
⎯
μs
SCL clock “H” width
tHIGH
SCL0
4.0
⎯
0.6
⎯
μs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA
SCL0
SDA0
4.7
⎯
0.6
⎯
μs
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
SCL0
SDA0
0
3.45*2
0
0.9*3
μs
Data setup time SDA ↓ ↑ → SCL ↑
tSU;DAT
SCL0
SDA0
0.25*4
⎯
0.1*4
⎯
μs
Stop condition setup time SCL ↑ →
SDA ↑
tSU;STO
SCL0
SDA0
4.0
⎯
0.6
⎯
μs
tBUF
SCL0
SDA0
4.7
⎯
1.3
⎯
μs
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHD;DAT have only to be met if the device dose not stretch the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU;DAT ≥ 250 ns must then be met.
*4 : Refer to “ • Note of SDA and SCL set-up time”.
• Note of SDA and SCL set-up time
SDA0
Input data set-up time
SCL0
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
57
MB95120MB Series
tWAKEUP
SDA0
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL0
tHD;STA
58
tSU;DAT
tSU;STA
tSU;STO
MB95120MB Series
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Sym- Pin
Condition
bol name
Value*2
Min
Max
Unit
Remarks
SCL clock
“L” width
tLOW
SCL0
(2 + nm / 2) tMCLK − 20
⎯
ns
Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm / 2) tMCLK − 20
(nm / 2 ) tMCLK + 20
ns
Master mode
Start condition
SCL0
tHD;STA
hold time
SDA0
(−1 + nm / 2) tMCLK − 20
(−1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m,
n = 1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
SCL0
tSU;STO
setup time
SDA0
(1 + nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition
SCL0
tSU;STA
setup time
SDA0
(1 + nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Master mode
SCL0
SDA0
(2 nm + 4) tMCLK − 20
⎯
ns
SCL0
SDA0
3 tMCLK − 20
⎯
ns
Master mode
ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise,
the maximum
value is applied.
Bus free time
between stop
condition and
start condition
tBUF
Data hold time tHD;DAT
R = 1.7 kΩ,
C = 50 pF*1
Data setup
time
Setup time
between
clearing
interrupt and
SCL rising
tSU;DAT
SCL0
SDA0
tSU;INT SCL0
(−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20
(nm / 2) tMCLK − 20
(1 + nm / 2) tMCLK + 20
ns
Minimum value is
applied to interrupt
at 9th SCL↓.
Maximum value is
applied to interrupt
at 8th SCL↓.
SCL clock “L”
width
tLOW
SCL0
4 tMCLK − 20
⎯
ns
At reception
SCL clock “H”
width
tHIGH
SCL0
4 tMCLK − 20
⎯
ns
At reception
Start condition
SCL0
tHD;STA
detection
SDA0
2 tMCLK − 20
⎯
ns
Undetected when
1 tMCLK is used at
reception
(Continued)
59
MB95120MB Series
(Continued)
Parameter
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
Sym- Pin
Condition
bol name
Value*2
Min
Max
Unit
Remarks
Stop condition
detection
tSU;STO
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
Restart condition
detection condition
tSU;STA
SCL0
SDA0
2 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at
reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK − 20
⎯
ns
At reception
Data hold time
tHD;DAT
2 tMCLK − 20
⎯
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0 R = 1.7 kΩ,
1
SCL0 C = 50 pF*
tLOW − 3 tMCLK − 20
⎯
ns
At slave transmission
mode
Data hold time
tHD;DAT
SCL0
SDA0
0
⎯
ns
At reception
Data setup time
tSU;DAT
SCL0
SDA0
tMCLK − 20
⎯
ns
At reception
SDA↓→SCL↑
(at wakeup function)
tWAKE-
SCL0
SDA0
Oscillation
stabilization
wait time +
2 tMCLK − 20
⎯
ns
UP
SDA0
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : •
•
•
•
Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
m is CS4 bit and CS3 bit (bit 4 and bit 3) of I2C clock control register (ICCR) .
n is CS2 bit to CS0 bit (bit 2 to bit 0) of I2C clock control register (ICCR) .
Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of
ICCR0 register.
• Standard-mode :
m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode :
m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
Setting of m and n determines the machine clock that can be used below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
60
MB95120MB Series
(9) Low Voltage Detection
(AVss = Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Condition
Value
Min
Typ
Max
Unit
Remarks
Release voltage
VDL+
2.52
2.70
2.88
V
At power-supply rise
Detection voltage
VDL-
2.42
2.60
2.78
V
At power-supply fall
Hysteresis width
VHYS
70
100
⎯
mV
Power-supply start voltage
Voff
⎯
⎯
2.3
V
Power-supply end voltage
Von
4.9
⎯
⎯
V
0.3
⎯
⎯
μs
Slope of power supply that reset
release signal generates
⎯
3000
⎯
μs
Slope of power supply that reset
release signal generates within
rating (VDL+)
300
⎯
⎯
μs
Slope of power supply that reset
detection signal generates
⎯
300
⎯
μs
Slope of power supply that reset
detection signal generates within rating (VDL-)
Power-supply voltage
change time
(at power supply rise)
tr
⎯
Power-supply voltage
change time
(at power supply fall)
tf
Reset release delay time
td1
⎯
⎯
400
μs
Reset detection delay time
td2
⎯
⎯
30
μs
Current consumption
ILVD
⎯
38
50
μA
Current consumption of low
voltage detection circuit only
VCC
Von
Voff
time
tr
tf
VCC
VDL+
VHYS
VDL-
Internal reset signal
td2
td1
time
61
MB95120MB Series
(10) Clock Supervisor Clock
(Vcc = AVcc = 5 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Oscillation frequency
fOUT
Oscillation start time
twk
Condition
⎯
Current consumption
62
ICSV
Value
Unit
Min
Typ
Max
50
100
200
kHz
⎯
⎯
10
μs
⎯
20
36
μA
Remarks
Current consumption of builtin CR oscillator, at 100 kHz
oscillation
MB95120MB Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(AVcc = Vcc = 4.0 V to 5.5 V, AVss = Vss = 0.0 V, TA = − 40 °C to + 105 °C)
Parameter
Symbol
Condition
Resolution
Total error
Linearity error
⎯
Differential linear error
Value
Unit
Min
Typ
Max
⎯
⎯
10
bit
− 3.0
⎯
+ 3.0
LSB
− 2.5
⎯
+ 2.5
LSB
− 1.9
⎯
+ 1.9
LSB
Remarks
Zero transition voltage
VOT
AVss −
1.5 LSB
AVss +
0.5 LSB
AVss +
2.5 LSB
V
Full-scale transition
voltage
VFST
AVR −
3.5 LSB
AVR −
1.5 LSB
AVR +
0.5 LSB
V
0.9
⎯
16500
μs
4.5 V ≤ AVcc ≤
5.5 V
1.8
⎯
16500
μs
4.0 V ≤ AVcc <
4.5 V
μs
4.5 V ≤ AVcc ≤
5.5 V,
At external
impedance < 5.4 kΩ
4.0 V ≤ AVcc <
4.5 V,
At external
impedance < 2.4 kΩ
Compare time
⎯
⎯
Sampling time
0.6
⎯
∞
⎯
1.2
⎯
∞
μs
Analog input current
IAIN
−0.3
⎯
+0.3
μA
Analog input voltage
VAIN
AVss
⎯
AVR
V
⎯
AVss + 4.0
⎯
AVcc
V
AVR pin
IR
⎯
600
900
μA
AVR pin,
During A/D
operation
IRH
⎯
⎯
5
μA
AVR pin,
At stop mode
Reference voltage
Reference voltage
supply current
63
MB95120MB Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc < 4.5 V
R
2.0 kΩ (Max)
8.2 kΩ (Max)
C
16 pF (Max)
16 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
100
90
80
70
60
50
40
30
20
10
0
AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
0
2
4
6
8
10
12
Minimum sampling time [μs]
14
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
20
18
16
14
12
10
8
6
4
2
0
AVCC ≥ 4.5 V
AVCC ≥ 4.0 V
0
1
3
Minimum sampling time [μs]
• About errors
As |AVCC − AVSS| becomes smaller, values of relative errors grow larger.
64
2
4
MB95120MB Series
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ← → “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ← → “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit: LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
3FEH
1.5 LSB
3FDH
004H
003H
002H
VOT
Digital output
Digital output
3FEH
3FDH
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001H
001H
0.5 LSB
AVSS
AVR
Analog input
1 LSB =
AVR − AVSS
1024
(V)
AVSS
AVR
Analog input
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N − 1)H to NH.
(Continued)
65
MB95120MB Series
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004H
3FFH
Digital output
Digital output
Actual conversion
characteristic
003H
Ideal
characteristics
002H
Actual conversion
characteristic
Actual conversion
characteristic
3FEH
VFST
(measurement
value)
3FDH
001H
VOT (measurement value)
AVSS
AVR
AVSS
Analog input
AVR
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FFH
Ideal characteristics
(N+1)H
3FEH
Actual conversion
characteristic
VFST
(measurement
value)
VNT
004H
Actual conversion
characteristic
003H
002H
Digital output
{1 LSB × N + VOT}
3FDH
Digital output
Actual conversion
characteristic
3FCH
NH
(N-1)H
VNT
Actual conversion
characteristic
Ideal characteristics
(N-2)H
001H
V (N+1)T
VOT (measurement value)
AVSS
AVR
Analog input
Linear error in
= VNT − {1 LSB × N + VOT}
1 LSB
digital output N
AVSS
Analog input
Differential linear error =
in digital output N
N : A/D Converter digital output value
VNT : A voltage at which digital output transits from (N − 1)H to NH.
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
66
V (N + 1) T − VNT
1 LSB
AVR
−1
MB95120MB Series
6. Flash Memory Program/Erase Characteristics
Parameter
Condition
Value
Unit
Remarks
0.5*2
s
Excludes 00H programming
prior erasure.
0.5*1
7.5*2
s
Excludes 00H programming
prior erasure.
⎯
32
3600
μs
Excludes system-level
overhead.
10000
⎯
⎯
cycle
Power supply voltage at
program/erase
4.5
⎯
5.5
V
Flash memory data retention
time
20*3
⎯
⎯
year
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2*1
Sector erase time
(16 Kbytes sector)
⎯
Byte programming time
⎯
Program/erase cycle
Average TA = +85 °C
*1 : TA = + 25 °C, VCC = 5.0 V, 10000 cycles
*2 : TA = + 85 °C, VCC = 4.5 V, 10000 cycles
*3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
67
MB95120MB Series
■ EXAMPLE CHARACTERISTICS
• Power supply current temperature
ICC − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode, at external clock operating
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode, at external clock operating
20
20
FMP = 16 MHz
10
FMP = 10 MHz
15
ICC [mA]
ICC [mA]
FMP = 16 MHz
15
FMP = 10 MHz
10
FMP = 8 MHz
5
5
FMP = 4 MHz
FMP = 2 MHz
0
2
3
4
5
6
0
−50
7
0
VCC [V]
20
20
15
15
10
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
0
2
3
4
5
6
FMP = 16 MHz
5
0
−50
7
FMP = 10 MHz
0
VCC [V]
ICCMPLL − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz
(Multiply-by-2.5)
Main PLL mode, at external clock operating
+50
TA [°C]
+100
+150
ICCMPLL − TA
VCC = 5.5 V, FMP = 10, 16 MHz
(Multiply-by-2.5)
Main PLL mode, at external clock operating
20
20
15
FMP = 16 MHz
10
ICCMPLL [mA]
ICCMPLL [mA]
+150
10
FMP = 16 MHz
5
+100
ICCS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode, at external clock operating
ICCS [mA]
ICCS [mA]
ICCS − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode, at external clock operating
+50
TA [°C]
FMP = 10 MHz
FMP = 8 MHz
5
15
FMP = 16 MHz
10
FMP = 10 MHz
5
FMP = 4 MHz
FMP = 2 MHz
0
2
3
4
5
VCC [V]
6
7
0
−50
0
+50
TA [°C]
+100
+150
(Continued)
68
MB95120MB Series
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
100
100
75
75
ICCL [μA]
ICCL [μA]
ICCL − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
50
25
50
25
0
2
3
4
5
6
0
−50
7
0
+100
+150
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
100
100
75
75
50
25
50
25
0
2
3
4
5
6
0
−50
7
0
VCC [V]
ICCT − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
+50
TA [°C]
+100
+150
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
100
100
75
75
ICCT [μA]
ICCT [μA]
+50
TA [°C]
ICCLS − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
ICCLS [μA]
ICCLS [μA]
VCC [V]
50
25
50
25
0
2
3
4
5
VCC [V]
6
7
0
−50
0
+50
TA [°C]
+100
+150
(Continued)
69
MB95120MB Series
ICCSPLL − TA
VCC = 5.5 V, FMPL = 128 kHz (Multiply-by-4)
Sub PLL mode, at external clock operating
100
100
75
75
ICCSPLL [μA]
ICCSPLL [μA]
ICCSPLL − VCC
TA = + 25 °C, FMPL = 128 kHz (Multiply-by-4)
Sub PLL mode, at external clock operating
50
25
50
25
0
2
3
4
5
6
0
−50
7
0
VCC [V]
ICTS − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode, at external clock operating
+50
TA [°C]
+150
ICTS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode, at external clock operating
2.0
2.0
1.5
1.5
FMP = 16 MHz
ICTS [mA]
FMP = 16 MHz
ICTS [mA]
+100
1.0
FMP = 10 MHz
1.0
FMP = 10 MHz
FMP = 8 MHz
0.5
0.5
FMP = 4 MHz
FMP = 2 MHz
0.0
2
3
4
5
6
0.0
−50
7
0
VCC [V]
+100
+150
ICCH − TA
VCC = 5.5 V, FMPL = (stop)
Sub stop mode, at external clock stopping
20
20
15
15
ICCH [μA]
ICCH [μA]
ICCH − VCC
TA = + 25 °C, FMPL = (stop)
Sub stop mode, at external clock stopping
+50
TA [°C]
10
5
10
5
0
2
3
4
5
VCC [V]
6
7
0
−50
0
+50
TA [°C]
+100
+150
(Continued)
70
MB95120MB Series
IA − AVCC
TA = + 25 °C, FMP = 16 MHz (divided by 2)
Main clock mode, at external clock operating
IA − TA
VCC = 5.5 V, FMP = 16 MHz (divided by 2)
Main clock mode, at external clock operating
4
4
3
3
IA [mA]
IA [mA]
(Continued)
2
1
2
1
0
2
3
4
5
6
0
−50
7
0
+50
TA [°C]
+100
+150
IR − AVCC
TA = + 25 °C, FMP = 16 MHz (divided by 2)
Main clock mode, at external clock operating
IR − TA
VCC = 5.5 V, FMP = 16 MHz (divided by 2)
Main clock mode, at external clock operating
4
4
3
3
IR [mA]
IR [mA]
AVCC [V]
2
1
2
1
0
2
3
4
5
AVCC [V]
6
7
0
−50
0
+50
TA [°C]
+100
+150
71
MB95120MB Series
• Input voltage
VIH1 − VCC and VIL − VCC
TA = + 25 °C
VIHS1 − VCC and VILS − VCC
TA = + 25 °C
5
5
4
4
VIHS1 / VILS [V]
VIHS1
VIH1 / VIL [V]
VIH1
3
VIL
2
3
VILS
2
1
1
0
0
2
3
4
5
6
2
7
3
4
5
6
7
VCC [V]
VCC [V]
VIH2 − VCC and VIL − VCC
TA = + 25 °C
VIHS2 − VCC and VILS − VCC
TA = + 25 °C
5
5
4
4
VIHS2 / VILS [V]
VIH2 / VIL [V]
VIHS2
VIH2
3
VIL
2
1
3
VILS
2
1
0
0
2
3
4
5
6
7
2
3
4
VCC [V]
5
6
7
VCC [V]
VIHA − VCC and VILA − VCC
TA = + 25 °C
VIHM − VCC and VILM − VCC
TA = + 25 °C
5
5
VIHA
4
4
VIHM / VILM [V]
VIHA / VILA [V]
VILA
3
2
1
VIHM
2
VILM
1
0
0
2
3
4
5
VCC [V]
72
3
6
7
2
3
4
5
VCC [V]
6
7
MB95120MB Series
• Output voltage
3.5 V
3.3 V
(VCC-VOH2) − IOH
TA = + 25 °C
3V
2.7 V
2.5 V
(VCC-VOH1) − IOH
TA = + 25 °C
1.0
VCC = 4 V
VCC = 2.45 V
0.6
0.4
VCC = 2.45 V
0.8
VCC − VOH2 [V]
VCC = 4.5 V
VCC = 5 V
VCC = 5.5V
0.8
VCC − VOH1 [V]
VCC = 2.5 V
1.0
VCC = 2.7 V
VCC = 3 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4 V
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
0.6
0.4
0.2
0.2
0.0
0.0
0
−2
−4
−6
IOH [mA]
−8
−10
−2
0
−4
−6
IOH [mA]
3V
1.0
1.0
0.8
VCC = 3.3 V
VCC = 2.5 V
0.8
VCC = 2.45 V
0.6
VCC = 4 V
VCC = 4.5 V
VCC = 5 V
VCC = 5.5V
VCC = 2.45 V
0.4
VOL2 [V]
VCC = 3.5 V
VOL1 [V]
−10
VOL2 − IOL2
TA = + 25 °C
2.7 V
VOL1 − IOL1
TA = + 25 °C
−8
0.6
0.4
0.2
0.2
0.0
0.0
0.0
0
2
4
6
IOL1 [mA]
8
10
2.5
5.0
7.5
10.0
IOL2 [mA]
12.5
VCC = 2.5 V
VCC = 2.7 V
VCC = 3 V
VCC = 3.3 V
VCC = 3.5 V
VCC = 4 V
VCC = 4.5 V
VCC = 5 V
VCC = 5.5 V
15.0
• Pull-up
RPULL − VCC
TA = + 25 °C
250
RPULL [kΩ]
200
150
100
50
0
2
3
4
VCC [V]
5
6
73
MB95120MB Series
■ MASK OPTION
Part number
MB95128MB
MB95F124MB/F124NB/F124JB
MB95F126MB/126NB/F126JB
MB95F128MB/F128NB/F128JB
MB95FV100D-103
Specifying procedure
Specify when
ordering MASK
Setting disabled
Setting disabled
Dual-system clock
mode
Dual-system clock mode
Changing by the
switch on
MCU board
No.
1
Clock mode select
• Single-system clock mode
• Dual-system clock mode
2
Low voltage detection reset*
• With low voltage detection
reset
• Without low voltage detection
reset
Specify when
ordering MASK
Specified by part
number
Changing by the
switch on
MCU board
3
Clock supervisor*
• With clock supervisor
• Without clock supervisor
Specify when
ordering MASK
Specified by part
number
Changing by the
switch on
MCU board
Specified by part
number
MCU board switch set
as following ;
• With supervisor :
Without reset
output
• Without supervisor :
With reset output
Fixed to oscillation Fixed to oscillation
stabilization wait
stabilization wait time of
time of (214−2) /FCH (214−2) /FCH
Fixed to oscillation
stabilization wait time
of (214−2) /FCH
4
Reset output*
• With reset output
• Without reset output
5
Oscillation stabilization
wait time
Specify when
ordering MASK
* : Refer to table below about clock mode select, low voltage detection reset, clock supervisor select and reset output.
74
MB95120MB Series
Part number
Clock mode select
Low voltage detection reset Clock supervisor Reset output
No
No
Yes
Yes
No
Yes
Yes
Yes
No
MB95F124MB
No
No
Yes
MB95F124NB
Yes
No
Yes
Yes
Yes
No
No
No
Yes
MB95F126NB
Yes
No
Yes
MB95F126JB
Yes
Yes
No
MB95F128MB
No
No
Yes
MB95F128NB
Yes
No
Yes
MB95F128JB
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Yes
Yes
No
MB95128MB
MB95F124JB
MB95F126MB
Dual-system
Single-system
MB95FV100D-103
Dual-system
75
MB95120MB Series
■ ORDERING INFORMATION
Part number
MB95128MBPMC
MB95F124MBPMC
MB95F124NBPMC
MB95F124JBPMC
MB95F126MBPMC
MB95F126NBPMC
MB95F126JBPMC
MB95F128MBPMC
MB95F128NBPMC
MB95F128JBPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB95128MBPF
MB95F124MBPF
MB95F124NBPF
MB95F124JBPF
MB95F126MBPF
MB95F126NBPF
MB95F126JBPF
MB95F128MBPF
MB95F128NBPF
MB95F128JBPF
100-pin plastic QFP
(FPT-100P-M06)
MB2146-303A
(MB95FV100D-103PBT)
76
Package
(
MCU board
224-pin plastic PFBGA
(BGA-224P-M08)
)
MB95120MB Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
C
0.08(.003)
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
25
0.20±0.05
(.008±.002)
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
M
0.145±0.055
(.0057±.0022)
2005 FUJITSU LIMITED F100031S-c-2-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
77
MB95120MB Series
(Continued)
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
"A"
C
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
78
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB95120MB Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Added the MB95128MB (MASK ROM product)
26
■ I/O MAP
Changed as follows for R/W of Reset source register
R → R/W
35
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
For the operating temperature, the max rating is
changed;
+ 85 °C → + 105 °C
37 to 42, 44, Temperature conditions on table
47 to 51, 53,
55 to 57,
59 to 63
42
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics (1) Clock Timing
Changed as follows
TA = − 40 °C to + 85 °C → TA = − 40 °C to + 105 °C
Added “Main PLL multiplied by 4” in the Clock frequency
44
• Changed in the remarks of source clock cycle time
(when using main clock)
Min : FCH = 16.25 MHz, PLL multiplied by 1
→ Min : FCH = 8.125 MHz, PLL multiplied by 2
• Changed the footnote of *1;
PLL multiplication of main clock (select from 1, 2, 2.5
multiplication) →
PLL multiplication of main clock (select from 1, 2, 2.5,
4 multiplication)
• Added “ × 4” in the Main PLL of “• Outline of clock
generation block“
45
Changed as follows
• Operating voltage − Operating frequency (TA =
− 40 °C to + 85 °C) →
• Operating voltage − Operating frequency (TA =
− 40 °C to + 105 °C)
(2) Source Clock/Machine Clock
Changed the figure of • Main PLL operation frequency
46
57
68 to 73
2
(8) I C Timing
Added the *4
■ EXAMPLE CHARACTERISTICS
Added the ■ EXAMPLE CHARACTERISTICS
The vertical lines marked in the left side of the page show the changes.
79
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
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For further information please contact:
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Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
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Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
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Shanghai 200002, China
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
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as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
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Edited
Strategic Business Development Dept.