FUJITSU SEMICONDUCTOR
DATA SHEET
DS07–12xxx–1E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95430H Series
MB95F432H/F433H/F434H
MB95F432K/F433K/F434K
■ DESCRIPTION
MB95430H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction
set, the microcontrollers of this series contain a variety of peripheral resources.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10/12.5 MHz ±2%, maximum machine clock frequency: 12.5 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer × 1 channel
• 16-bit PPG × 1 channel
• 16-bit free-running timer × 1 channel
• 16-bit output compare × 2 channels
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• UART/SIO × 1 channel
• Full duplex double buffer
• Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.8
MB95430H Series
(Continued)
• I2C × 1 channel
• Built-in wake-up function
• Voltage comparator × 4 channels
• Operational amplifier (OPAMP) × 1 channel
• Software-select programmable gain
• Software-select standalone option
• Power down function included
• External interrupt × 8 channels
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter × 17 channels
• 8-bit and 10-bit resolution can be chosen.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F432H/F433H/F434H (maximum no. of I/O ports: 28)
General-purpose I/O ports (N-ch open drain)
:1
General-purpose I/O ports (CMOS I/O)
: 27
• MB95F432K/F433K/F434K (maximum no. of I/O ports: 29)
General-purpose I/O ports (N-ch open drain)
:2
General-purpose I/O ports (CMOS I/O)
: 27
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Programmable port input voltage level
• CMOS input level / hysteresis input level
• Dual operation Flash memory
• The erase/write operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
• Protects the content of the Flash memory
2
DS07–12xxx–1E
MB95430H Series
■ PRODUCT LINE-UP
Part number
MB95F432H
MB95F433H
MB95F434H
MB95F432K
MB95F433K
MB95F434K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Program ROM
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
240 bytes
496 bytes
240 bytes
240 bytes
496 bytes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected by software
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
CPU functions
Data bit length
: 1, 8 and 16 bits
Minimum instruction execution time : 61.5 ns (with machine clock = 16.25 MHz)
Interrupt processing time
: 0.6 µs (with machine clock = 16.25 MHz)
I/O ports (Max): 29
I/O ports (Max): 28
GeneralCMOS I/O: 27
CMOS I/O: 27
purpose I/O
N-ch open drain: 1
N-ch open drain: 2
Time-base
Interrupt cycle: 0.256 ms to 8.3 s (when external clock = 4 MHz)
timer
Hardware/
Reset generation cycle
software
- Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
17 channels (Ch. 16 is the channel for OPAMP output.)
8/10-bit A/D
converter
8-bit resolution and 10-bit resolution can be chosen.
1 channel
8/16-bit
The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
composite
It has built-in timer function, PWC function, PWM function and input capture function.
timer
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
8 channels
External
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
It can be used to wake up the device from different standby modes.
1-wire serial control
On-chip debug
It supports serial writing. (asynchronous mode)
1 channel
Data transfer with UART/SIO is enabled.
It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
UART/SIO
It uses the NRZ type transfer format.
LSB-first data transfer and MSB-first data transfer are available to use.
Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
(Continued)
DS07–12xxx–1E
3
MB95430H Series
(Continued)
Part number
MB95F432H
MB95F433H
MB95F434H
MB95F432K
MB95F433K
MB95F434K
Parameter
I2C
16-bit PPG
Output
compare
Voltage
comparator
1 channel
Master/slave transmission and receiving
It has a bus error function, an arbitration function, a transmission direction detection function
and a wake-up function.
It also has functions of generating and detecting repeated START conditions.
PWM mode and single-shot mode are available to use.
Ch. 0 can work with the multi-functional timer or individually.
1 channel of 16-bit free-running timer with a compare buffer
2 channels of 16-bit output compare
4 channels
OPAMP
This is an operational amplifier used in an induction heater. It contains 7 software (registers)
select close loop gain selections for ground current sensing according to different sense
resistor values. The OPAMP can also work as a standalone OPAMP.
It selects closed loop gain for ground current sensing according to different sense resistor
values of a standalone OPAMP.
Watch
prescaler
Eight different time intervals can be selected.
It supports automatic programming, Embedded Algorithm, and write/erase/erase-suspend/
erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
Number of write/erase cycles: 100000
Data retention time: 20 years
Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-32P-M30
Package
DIP-32P-M06
4
DS07–12xxx–1E
MB95430H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F432H
MB95F433H
MB95F434H
MB95F432K
MB95F433K
MB95F434K
FPT-32P-M30
O
O
O
O
O
O
DIP-32P-M06
O
O
O
O
O
O
Package
O: Available
DS07–12xxx–1E
5
MB95430H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool.
6
DS07–12xxx–1E
MB95430H Series
32
31
30
29
28
27
26
25
Vss
PF1/X1
PF0/X0
PF2/RST
P67/CMP3_N/AN15
P66/CMP3_P/AN14
P65/CMP3_O/UO/SDA
P64/CMP2_N/AN13
■ PIN ASSIGNMENT
P62/OPAMP_O
P12/EC0/UI/SCL/DBG
7
8
PF2/RST
PF0/X0
PF1/X1
Vss
PG2/PPG0/X1A/OUT1
PG1/TRG/ADTG/X0A/BZ/OUT0
Vcc
C
P60/OPAMP_P
P61/OPAMP_N
P62/OPAMP_O
P12/EC0/UI/SCL/DBG
P00/INT00/AN00
P01/INT01/AN01/BZ
P02/INT02/AN02/UCK
P03/INT03/AN03/UO/SDA
DS07–12xxx–1E
FPT-32P-M30
16
5
6
P07/INT07/AN07/EC0
P60/OPAMP_P
P61/OPAMP_N
(TOP VIEW)
LQFP32
13
14
15
3
4
P04/INT04/AN04/UI/SCL
P05/INT05/AN05/TO0
P06/INT06/AN06/TO1
Vcc
C
9
10
11
12
1
2
P00/INT00/AN00
P01/INT01/AN01/BZ
P02/INT02/AN02/UCK
P03/INT03/AN03/UO/SDA
PG2/PPG0/X1A/OUT1
PG1/TRG/ADTG/X0A/BZ/OUT0
1
2
32
31
3
4
30
29
5
6
28
27
(TOP VIEW)
SH-DIP32
24
23
22
21
P63/CMP2_P/AN12
P76/CMP2_O/UCK
P75/CMP1_N/AN11
P74/CMP1_P/AN10
20
19
18
17
P73/CMP1_O/OUT1/PPG
P72/CMP0_N/AN09
P71/CMP0_P/AN08
P70/CMP0_O/OUT0/TRG
P67/CMP3_N/AN15
P66/CMP3_P/AN14
P65/CMP3_O/UO/SDA
P64/CMP2_N/AN13
P63/CMP2_P/AN12
P76/CMP2_O/UCK
26
P75/CMP1_N/AN11
8
25
P74/CMP1_P/AN10
9
10
11
12
13
14
15
16
24
P73/CMP1_O/OUT1/PPG
P72/CMP0_N/AN09
P71/CMP0_P/AN08
P70/CMP0_O/OUT0/TRG
P07/INT07/AN07/EC0
P06/INT06/AN06/TO1
P05/INT05/AN05/TO0
7
DIP-32P-M06
23
22
21
20
19
18
17
P04/INT04/AN04/UI/SCL
7
MB95430H Series
■ PIN DESCRIPTION
Pin no.
LQFP32*1 SH-DIP32*2
Pin name
I/O
circuit
type*3
PG2
1
5
PPG
X1A
General-purpose I/O port
C
OUT1
2
6
Function
16-bit PPG output pin
Subclock I/O oscillation pin
Output compare ch. 1 output pin
PG1
General-purpose I/O port
TRG
16-bit PPG trigger input pin
ADTG
X0A
C
BZ
A/D converter trigger input pin
Subclock I/O oscillation pin
Buzzer output pin
OUT0
Output compare ch. 0 output pin
3
7
VCC
—
Power supply pin
4
8
C
—
Capacitor connection pin
5
9
6
10
7
11
8
9
12
13
P60
OPAMP_P
P61
OPAMP_N
P62
OPAMP_O
K
K
J
11
15
General-purpose I/O port
Operational amplifier input pin
General-purpose I/O port
Operational amplifier output pin
General-purpose I/O port
EC0
8/16-bit composite timer external clock input pin
UI
H
UART/SIO data input pin
SCL
I2C clock I/O pin
DBG
DBG input pin
P00
General-purpose I/O port
INT00
E
INT01
AN01
External interrupt input pin
A/D converter analog input pin
P01
14
Operational amplifier input pin
P12
AN00
10
General-purpose I/O port
General-purpose I/O port
E
External interrupt input pin
A/D converter analog input pin
BZ
Buzzer output pin
P02
General-purpose I/O port
INT02
AN02
UCK
E
External interrupt input pin
A/D converter analog input pin
UART/SIO clock I/O pin
(Continued)
8
DS07–12xxx–1E
MB95430H Series
Pin no.
LQFP32*1 SH-DIP32*2
12
13
16
17
Pin name
I/O
circuit
type*3
P03
General-purpose I/O port
INT03
External interrupt input pin
AN03
F
15
16
17
18
18
19
20
21
22
UART/SIO data output pin
SDA
I2C data I/O pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
F
SCL
I2C clock I/O pin
P05
General-purpose I/O port
INT05
AN05
E
P06
General-purpose I/O port
INT06
AN06
E
External interrupt input pin
A/D converter analog input pin
TO1
Timer output pin
P07
General-purpose I/O port
INT07
AN07
E
External interrupt input pin
A/D converter analog input pin
EC0
8/16-bit composite timer external clock input pin
P70
General-purpose I/O port
CMP0_O
OUT0
D
Comparator ch. 0 output pin
Output compare ch. 0 output pin
TRG
16-bit PPG trigger input pin
P71
General-purpose I/O port
CMP0_P
I
CMP0_N
CMP1_O
OUT1
PPG
Comparator ch. 0 positive input pin
A/D converter analog input pin
General-purpose I/O port
I
Comparator ch. 0 negative input pin
A/D converter analog input pin
P73
24
A/D converter analog input pin
Timer output pin
AN09
20
External interrupt input pin
TO0
P72
23
A/D converter analog input pin
UART/SIO data input pin
AN08
19
A/D converter analog input pin
UO
UI
14
Function
General-purpose I/O port
D
Comparator ch. 1 output pin
Output compare ch. 1 output pin
16-bit PPG output pin
(Continued)
DS07–12xxx–1E
9
MB95430H Series
(Continued)
Pin no.
LQFP32*1 SH-DIP32*2
Pin name
I/O
circuit
type*3
P74
21
25
CMP1_P
General-purpose I/O port
I
AN10
26
CMP1_N
General-purpose I/O port
I
AN11
24
27
28
CMP2_O
General-purpose I/O port
D
UART/SIO clock I/O pin
P63
General-purpose I/O port
CMP2_P
I
CMP2_N
General-purpose I/O port
I
AN13
27
30
31
CMP3_O
UO
General-purpose I/O port
L
P66
General-purpose I/O port
CMP3_P
I
CMP3_N
General-purpose I/O port
I
30
2
31
3
32
4
RST
PF0
X0
PF1
X1
VSS
Comparator ch. 3 negative input pin
A/D converter analog input pin
PF2
1
Comparator ch. 3 positive input pin
A/D converter analog input pin
AN15
29
UART/SIO data output pin
I2C data I/O pin
P67
32
Comparator ch. 3 output pin
SDA
AN14
28
Comparator ch. 2 negative input pin
A/D converter analog input pin
P65
26
Comparator ch. 2 positive input pin
A/D converter analog input pin
P64
29
Comparator ch. 2 output pin
UCK
AN12
25
Comparator ch. 1 negative input pin
A/D converter analog input pin
P76
23
Comparator ch. 1 positive input pin
A/D converter analog input pin
P75
22
Function
General-purpose I/O port
A
B
B
—
Reset pin
Dedicated reset pin in MB95F432H/F433H/F434H
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
*1: Package code: FPT-32P-M30
*2: Package code: DIP-32P-M06
*3: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
10
DS07–12xxx–1E
MB95430H Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
N-ch
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
• N-ch open drain output
• Hysteresis input
• Reset output
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx.10 MΩ
• CMOS output
• Hysteresis input
• Pull-up control available
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
DS07–12xxx–1E
11
MB95430H Series
Type
Circuit
D
Remarks
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Pull-up control available
Analog input
•
•
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
Analog input
N-ch open drain output
(as I2C output)
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
P-ch
I2C output control
Digital output
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
CMOS input
G
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
H
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
• CMOS input
CMOS input
Digital output
N-ch
(Continued)
12
DS07–12xxx–1E
MB95430H Series
(Continued)
Type
Circuit
I
P-ch
P-ch
Remarks
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Analog input for A/D
Analog input for VC
Analog input control
Standby control
Hysteresis input
J
P-ch
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Analog output
Analog output control
Standby control
Hysteresis input
K
P-ch
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Analog input
Analog input control
Standby control
Hysteresis input
L
P-ch
P-ch
I2C output control
Digital output
Digital output
N-ch
Standby control
•
•
•
•
CMOS output
Hysteresis input
CMOS input
N-ch open drain output
(as I2C output)
Hysteresis input
CMOS input
DS07–12xxx–1E
13
MB95430H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the
RST/PF2 pin can be enabled by the RSTOE bit in the SYSC1 register, and the reset input function and the
general purpose I/O function can be selected by the RSTEN bit in the SYSC1 register.
14
DS07–12xxx–1E
MB95430H Series
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set
to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and
the VSS pin when designing the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
DS07–12xxx–1E
15
MB95430H Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(20 Kbyte)
PF1/X1*2
PF0/X0*2
Oscillator
circuit
(PG2/X1A*2)
RAM (496 bytes)
CR
oscillator
(PG1/X0A*2)
Comparator ch. 0
Clock control
(P12*1/DBG)
On-chip debug
trigger
Wild register
8
8
stop
External interrupt
Comparator ch. 1
(P05/TO0)
(P73/OUT1, PG2/OUT1)
P75/CMP1_N
P61/OPAMP_N
Buzzer
16-bit free-run timer
(P70/OUT0, PG1/OUT0)
P74/CMP1_P
OPAMP
2
Internal bus
(P01/BZ, PG1/BZ)
2
PG1/TRG, (P70/TRG)
P60/OPAMP_P
8/16-bit composite timer
(P06/TO1)
PG2/PPG, (P73/PPG)
P73/CMP1_O
Interrupt controller
P12*1/EC0, (P07/EC0)
P71/CMP0_P
P70/CMP0_O
16-bit PPG
(P00/INT00 to P07/INT07)
P72/CMP0_N
P62/OPAMP_O
(PG1/ATDG)
P00/AN00
P01/AN01
16-bit output compare
P02/AN02
P03/AN03
P67/CMP3_N
P66/CMP3_P
P04/AN04
Comparator ch. 3
P05/AN05
P06/AN06
P65/CMP3_O
8/10-bit A/D converter
P64/CMP2_N
P63/CMP2_P
P07/AN07
(P71/AN08)
Comparator ch. 2
(P72/AN09)
(P73/AN10)
P76/CMP2_O
(P74/AN11)
(P02/UCK, P76/UCK)
(P03/UO, P65/UO)
(P75/AN12)
UART/SIO
(P63/AN13)
(P04/UI, P12*1/UI)
(P64/AN14)
(P65/AN15)
I2 C
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
Vss
*2: Software option
C
(P04/SCL*3, P12*1/SCL)
(P03/SDA*3, P65/SDA*3)
Port
*3: This pin will work as an N-ch open drain pin during I2C operation.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
16
DS07–12xxx–1E
MB95430H Series
■ CPU CORE
• Memory Space
The memory space of the MB95430H Series is 64 Kbyte in size, and consists of an I/O area, a data area,
and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95430H Series are shown below.
• Memory Maps
MB95F432H/F432K
MB95F433H/F433K
0000H
0000H
I/O
0080H
0090H
0100H
Access prohibited
RAM 240 bytes
I/O
0080H
0090H
0100H
Register
0180H
MB95F434H/F434K
0000H
Access prohibited
RAM 240 bytes
I/O
0080H
0090H
0100H
Register
0180H
Access prohibited
RAM 496 bytes
Register
0200H
0280H
Access prohibited
Access prohibited
Access prohibited
0F80H
0F80H
Extended I/O
1000H
1000H
Access prohibited
B000H
C000H
Flash 4 Kbyte
Access prohibited
F000H
FFFFH
DS07–12xxx–1E
0F80H
Extended I/O
Flash 4 Kbyte
Extended I/O
1000H
Access prohibited
B000H
C000H
Flash 4 Kbyte
Access prohibited
B000H
Access prohibited
Flash 20 Kbyte
E000H
Flash 8 Kbyte
FFFFH
FFFFH
17
MB95430H Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
R/W
11111111B
0006H
—
—
—
0007H
SYCC
System clock control register
R/W
0000X011B
00000XXXB
(Disabled)
Oscillation stabilization wait time setting register
(Disabled)
0008H
STBC
Standby control register
R/W
0009H
RSRR
Reset source register
R/W XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
PDR7
Port 7 data register
R/W
00000000B
0019H
DDR7
Port 7 direction register
R/W
00000000B
0020H
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
BUZZ
Buzzer control register
R/W
00000000B
0039H
—
—
—
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Continued)
18
DS07–12xxx–1E
MB95430H Series
Address
Register
abbreviation
003AH
CMR0
Voltage comparator control register ch. 0
R/W
000X0001B
003BH
CMR1
Voltage comparator control register ch. 1
R/W
000X0001B
003CH
CMR2
Voltage comparator control register ch. 2
R/W
000X0001B
003DH
CMR3
Voltage comparator control register ch. 3
R/W
000X0001B
003EH
OPCR
OPAMP control register
R/W
00000011B
003FH
to
0041H
—
—
—
0042H
PCNTH0
16-bit PPG status control register upper ch. 0
R/W
00000000B
0043H
PCNTL0
16-bit PPG status control register lower ch. 0
R/W
00000000B
0044H
PTGS0
16-bit PPG trigger source control register ch. 0
R/W
00000000B
0045H
—
—
—
0046H
OCUOC
R/W
00000000B
0047H
—
—
—
0048H
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
SYSC2
R/W
00000000B
004FH
—
—
—
0050H
IBCR00
0051H
IBCR10
Register name
(Disabled)
(Disabled)
16-bit output compare stop trigger control register
(Disabled)
(Disabled)
System control register 2
(Disabled)
I2C bus control register 0
R/W Initial value
R/W
00000000B
2
R/W
00000000B
2
I C bus control register 1
0052H
IBSR0
I C bus status register
R/W
00000000B
0053H
IDDR0
I2C data register
R/W
00000000B
0054H
IAAR0
I2C address register
R/W
00000000B
2
0055H
ICCR0
I C clock control register
R/W
00000000B
0056H
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
00100000B
0058H
SSR0
UART/SIO serial status and data register ch. 0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch. 0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch. 0
R
00000000B
005BH
—
—
—
005CH
TCDTH
16-bit free-running timer data register (upper)
R/W
00000000B
005DH
TCDTL
16-bit free-running timer data register (lower)
R/W
00000000B
005EH
CPCLRH
16-bit free-running timer compare clear register (upper)
R
11111111B
005FH
CPCLRL
16-bit free-running timer compare clear register (lower)
R
11111111B
(Disabled)
(Continued)
DS07–12xxx–1E
19
MB95430H Series
Address
Register
abbreviation
0060H
TCCSH
16-bit free-running timer control status register (upper)
R/W
01000000B
0061H
TCCSL
16-bit free-running timer control status register (lower)
R/W
00000000B
0062H
ETCCSH
16-bit free-running timer extended control status register
(upper)
R/W
00000000B
0063H
ETCCSL
16-bit free-running timer extended control status register
(lower)
R/W
00000000B
0064H
OCCP0H
16-bit output compare channel 0 register (upper)
R
00000000B
0065H
OCCP0L
16-bit output compare channel 0 register (lower)
R
00000000B
0066H
OCCP1H
16-bit output compare channel 1 register (upper)
R
00000000B
0067H
OCCP1L
16-bit output compare channel 1 register (lower)
R
00000000B
0068H
OCSH
16-bit output compare control status register (upper)
R/W
00000000B
0069H
OCSL
16-bit output compare control status register (lower)
R/W
00000000B
006AH
OCMCR
16-bit output compare mode control register
R/W
00000000B
006BH
EOCS
16-bit output compare extended control status register
R/W
00000000B
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower)
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
R
0000XXXXB
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
to
0F7FH
—
—
—
Register name
(Disabled)
Flash memory status register 3
(Disabled)
(Disabled)
(Disabled)
R/W Initial value
(Continued)
20
DS07–12xxx–1E
MB95430H Series
Address
Register
abbreviation
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
WRARH3
Wild register address setting register (upper) ch. 3
R/W
00000000B
0F8AH
WRARL3
Wild register address setting register (lower) ch. 3
R/W
00000000B
0F8BH
WRDR3
Wild register data setting register ch. 3
R/W
00000000B
0F8CH
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
R/W
00000000B
0F97H
to
0FA9H
—
—
—
0FAAH
PDCRH0
16-bit PPG down counter register (upper) ch. 0
R/W
00000000B
0FABH
PDCRL0
16-bit PPG down counter register (lower) ch. 0
R/W
00000000B
0FACH
PCSRH0
16-bit PPG cycle setting buffer register (upper) ch. 0
R/W
11111111B
0FADH
PCSRL0
16-bit PPG cycle setting buffer register (lower) ch. 0
R/W
11111111B
0FAEH
PDUTH0
16-bit PPG duty setting buffer register (upper) ch. 0
R/W
11111111B
0FAFH
PDUTL0
16-bit PPG duty setting buffer register (lower) ch. 0
R/W
11111111B
0FB0H
to
0FBDH
—
—
—
0FBEH
PSSR0
UART/SIO prescaler select register ch. 0
R/W
00000000B
0FBFH
BRSR0
UART/SIO baud rate setting register ch. 0
R/W
00000000B
0FC0H,
0FC1H
—
—
—
0FC2H
AIDRH
A/D input disable register (upper)
R/W
00000000B
0FC3H
AIDRL
A/D input disable register (lower)
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Disabled)
R/W Initial value
(Continued)
DS07–12xxx–1E
21
MB95430H Series
(Continued)
Address
Register
abbreviation
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 0XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 00XXXXXXB
0FE6H,
0FE7H
—
0FE8H
SYSC1
0FE9H
Register name
(Disabled)
R/W Initial value
—
—
System configuration register 1
R/W
11000011B
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
—
—
—
0FEEH
ILSR
Input level select register
(Disabled)
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
—
—
—
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
22
DS07–12xxx–1E
MB95430H Series
■ INTERRUPT SOURCE TABLE
Vector table address
Priority order of
interrupt
Bit name of
sources of the
interrupt level
same level
setting register
(occurring
simultaneously)
Interrupt
request
number
Upper
Lower
IRQ00
FFFAH
FFFBH
L00 [1:0]
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
UART/SIO
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
Output compare ch. 0 match
IRQ07
FFECH
FFEDH
L07 [1:0]
Output compare ch. 1 match
IRQ08
FFEAH
FFEBH
L08 [1:0]
IRQ09
FFE8H
FFE9H
L09 [1:0]
Voltage comparator ch. 0
IRQ10
FFE6H
FFE7H
L10 [1:0]
Voltage comparator ch. 1
IRQ11
FFE4H
FFE5H
L11 [1:0]
Voltage comparator ch. 2
IRQ12
FFE2H
FFE3H
L12 [1:0]
Voltage comparator ch. 3
IRQ13
FFE0H
FFE1H
L13 [1:0]
16-bit free-running timer (compare
match/zero-detect/overflow)
IRQ14
FFDEH
FFDFH
L14 [1:0]
16-bit PPG
IRQ15
FFDCH
FFDDH
L15 [1:0]
IRQ16
FFDAH
FFDBH
L16 [1:0]
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 0
External interrupt ch. 4
External interrupt ch. 1
External interrupt ch. 5
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
2
IC
—
Flash memory
DS07–12xxx–1E
High
Low
23
MB95430H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
VSS − 0.3
VSS + 6
V
VI
VSS − 0.3
VSS + 6
V
*2
VO
VSS − 0.3
VSS + 6
V
*2
ICLAMP
−2
+2
mA
Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*3
IOL1
IOL2
—
—
15
15
“H” level maximum
output current
mA
4
“L” level average current
“L” level total average
output current
mA
IOLAV2
—
12
ΣIOL
—
100
mA
ΣIOLAV
—
50
mA
IOH1
—
−15
IOH2
—
−15
IOHAV1
—
mA
−4
“H” level average
current
mA
IOHAV2
—
−8
ΣIOH
—
−100
mA
ΣIOHAV
—
−50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
“H” level total maximum
output current
“H” level total average
output current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than P05 and P06
P05 and P06
Other than P05 and P06
Average output current =
operating current × operating ratio
(1 pin)
P05 and P06
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
Other than P05 and P06
P05 and P06
Other than P05 and P06
Average output current =
operating current × operating ratio
(1 pin)
P05 and P06
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
(Continued)
24
DS07–12xxx–1E
MB95430H Series
(Continued)
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
*3: Applicable to the following pins: P00 to P07, P60 to P67, P70 to P76, PF0 and PF1
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
• Input/Output equivalent circuit
Protective diode
VCC
HV(High Voltage) input (0 V to 16 V)
P-ch
Limiting
resistor
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07–12xxx–1E
25
MB95430H Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
VCC
Smoothing
capacitor
CS
Operating
temperature
TA
Value
Min
Max
2.4*1*2
5.5*1
2.3
5.5
2.9
5.5
2.3
5.5
0.022
1
−40
+85
+5
+35
Unit
Remarks
In normal operation
V
Other than on-chip debug
Hold condition in stop mode mode
In normal operation
Hold condition in stop mode
On-chip debug mode
µF *3
°C
Other than on-chip debug mode
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: This value becomes 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/EC0/UI/SCL/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
26
DS07–12xxx–1E
MB95430H Series
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter Symbol
"H" level
input voltage
“L” level
input voltage
Pin name
Condition
VIHI
P03, P04, P12,
P65
Unit
Remarks
VCC + 0.3
V
When CMOS input
level (hysteresis
input) is selected
—
VCC + 0.3
V
Hysteresis input
0.7 VCC
—
VCC + 0.3
V
Hysteresis input
*1
VSS − 0.3
—
0.3 VCC
V
When CMOS input
level (hysteresis
input) is selected
VILS
P00 to P07,
P12,
P60 to P67, P70
to P76,
PF0, PF1, PG1,
PG2
*1
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS − 0.3
—
0.3 VCC
V
Hysteresis input
P03, P04 and P65
are open-drain
output pins when
assigned as the
SDA/SCL pin of I2C.
Min
Typ*3
Max
*1
0.7 VCC
—
VIHS
P00 to P07,
P12,
P60 to P67, P70
to P76,
PF0, PF1, PG1,
PG2
*1
0.8 VCC
VIHM
PF2
—
VIL
P03, P04, P12,
P65
Open-drain
output
application
voltage
“H” level
output
voltage
“L” level
output
voltage
Input
capacitance
P03, P04, P12,
P65, PF2
VSS − 0.3
—
VSS + 5.5
V
VOH1
Output pins
other than P05,
IOH = −4 mA
P06, P12 and
PF2
VCC − 0.5
—
—
V
VOH2
P05, P06
IOH = −8 mA
VCC − 0.5
—
—
V
VOL1
Output pins
other than P05 IOL = 4 mA
and P06
—
—
0.4
V
VOL2
P05, P06
IOL = 12 mA
—
—
0.4
V
ILI
All input pins
0.0 V < VI < VCC
−5
—
+5
When pull-up
µA resistance is
disabled
RPULL
P00 to P07,
PG1, PG2
VI = 0 V
25
50
100
When pull-up
kΩ resistance is
enabled
—
5
15
pF
VD
Input leak
current (Hi-Z
output leak
current)
Pull-up
resistance
Value
CIN
—
Other than VCC
f = 1 MHz
and VSS
(Continued)
DS07–12xxx–1E
27
MB95430H Series
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
Value
Min
Typ*3 Max
Unit
Remarks
Flash memory
mA product (except
writing and erasing)
—
12.1
22
—
39.3
46.8
Flash memory
mA product (at writing
and erasing)
—
13.8
30.3
mA At A/D conversion
—
12.5
23.4
When the voltage
mA comparator is
operating
—
13.4
22.3
mA
—
5.1
13.2
mA
—
57
168
µA
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
—
7.6
92
µA
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
—
4.2
33
µA
VCC = 5.5 V
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock mode
—
9.6
18.2
mA
VCC = 5.5 V
Sub-CR clock mode
(divided by 2)
TA = +25°C
—
107.4 550
µA
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
ICCS
Power supply
current*2
Condition
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main
sleep mode
VCC
(divided
by 2)
(External clock
operation)
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25°C
ICCL
ICCMCR
VCC
ICCSCR
When the OPAMP
is operating
(Continued)
28
DS07–12xxx–1E
MB95430H Series
(Continued)
Parameter
Symbol
ICCTS
VCC = 5.5 V
FCH = 32 MHz
Time-base timer
VCC
mode
(External clock TA = +25°C
operation)
VCC = 5.5 V
Substop mode
TA = +25°C
—
0.9
3.3
mA
—
3.5
24.8
µA
ILVD
Current
consumption for
low-voltage
detection circuit only
—
26.9
54
µA
ICRH
Current
consumption for the
main CR oscillator
—
0.2
0.6
mA
Current
consumption for the
sub-CR oscillator
oscillating at
100 kHz
—
64.7
72
µA
ICCH
Power supply
current*2
Pin name
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Condition
Unit
Remarks
Min Typ*3 Max
VCC
ICRL
*1: The input levels of P04 can be switched between “CMOS input level” and “hysteresis input level”. The input
level selection register (ILSR) is used to switch between the two input levels.
*2: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL.
*3: VCC = 5.0 V, TA = 25°C
DS07–12xxx–1E
29
MB95430H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name Condition
X0, X1
FCH
X0
X1: open
X0, X1
Clock
frequency
FCRH
FCL
—
X0A, X1A
FCRL
Clock cycle
time
Input clock
pulse width
Input clock
rise time and
fall time
CR
oscillation
start time
tHCYL
—
1
—
1
—
12
1
—
32.5
MHz When the main external clock is
MHz used
TBD
12.5
TBD
MHz
TBD
10
TBD
MHz
TBD
8
TBD
MHz
TBD
1
TBD
MHz
—
32.768
—
kHz
When the sub-oscillation circuit
is used
—
32.768
—
kHz
When the sub-external clock is
used
16.25 MHz
—
50
100
200
X0, X1
—
61.5
—
1000
ns
83.4
—
1000
ns
*
30.8
—
1000
ns
—
—
30.5
—
µs
33.4
—
—
ns
*
12.4
—
—
ns
—
—
15.2
—
µs
—
—
5
ns
*
—
—
5
ns
X0
X1: open
X0A, X1A
tWH1
tWL1
X0
X1: open
X0, X1
X0A
X0
X1: open
X0, X1
Remarks
Typ
—
tLCYL
tCR
tCF
*
Max
Unit
Min
—
X0, X1
tWH2
tWL2
—
Value
When the main oscillation circuit
is used
When the main CR clock is used
kHz When the sub-CR clock is used
When the main oscillation circuit
is used
When the external clock is used
When the subclock is used
When the external clock is used,
the duty ratio should range
between 40% and 60%.
When the external clock is used
tCRHWK
—
—
—
—
80
µs
When the main CR clock is used
tCRLWK
—
—
—
—
10
µs
When the sub-CR clock is used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
30
DS07–12xxx–1E
MB95430H Series
tHCYL
tWH1
tWL1
tCR
X0, X1
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When the external clock is used When the external clock
(X1 is open)
is used
X0
X1
X1
X0
X1
Open
FCH
FCH
FCH
tLCYL
tWH2
tCR
X0A
tWL2
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When the external clock
is used
X0A
X1A
Open
FCL
DS07–12xxx–1E
31
MB95430H Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Source clock
cycle time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
FMPL
Unit
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
80
—
1000
ns
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
—
61
—
µs
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
MHz When the main oscillation clock is used
1
—
12.5
MHz When the main CR clock is used
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
80
—
16000
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
MHz When the main oscillation clock is used
0.0625
—
12.5
MHz When the main CR clock is used
1.024
—
16.384
3.125
—
50
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
kHz When the sub-oscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1 and DIV0). This source clock is divided to become a machine clock according to the divide
ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). In addition, a source clock can
be selected from the following.
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
32
DS07–12xxx–1E
MB95430H Series
• Schematic diagram of the clock generation block
Divided
by 2
FCH
(main oscillation)
FCRH
(Main CR clock)
FCL
(sub-oscillation)
FCRL
(Sub-CR clock)
SCLK
(source clock)
Divided
by 2
Divided
by 2
Clock mode select bits
(SYCC2: RCS1, RCS0)
Division
circuit
× 1
× 1/4
× 1/8
×1/16
MCLK
(machine clock)
Machine clock divide ratio select bits
(SYCC:DIV1, DIV0)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
MB95430H (without the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
MB95430H (with the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
2.9
3.0
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
DS07–12xxx–1E
33
MB95430H Series
(3) External Reset
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
RST “L” level
pulse width
Symbol
tRSTL
Value
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2 + 100
—
µs
In stop mode, subclock mode,
subsleep mode, watch mode, and
power-on
100
—
µs
In time-base timer mode
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
34
100 μs
Oscillation stabilization wait time
Execute instruction
DS07–12xxx–1E
MB95430H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
DS07–12xxx–1E
35
MB95430H Series
(5) Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
Value
Pin name
INT00 to INT07, EC0, ADTG,
TRG
Unit
Min
Max
2 tMCLK*
—
ns
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, ADTG,
TRG
36
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
DS07–12xxx–1E
MB95430H Series
(6) UART/SIO, Serial I/O Timing
Parameter
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Pin name
Condition
Unit
Min
Max
Symbol
Serial clock cycle time
tSCYC
UCK
UCK ↓ → UO time
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UCK, UI
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Serial clock “L” pulse width
4 tMCLK*
—
ns
−190
+190
ns
2 tMCLK*
—
ns
UCK, UI
2 tMCLK*
—
ns
tSHSL
UCK
4 tMCLK*
—
ns
tSLSH
UCK
4 tMCLK*
—
ns
—
190
ns
Internal clock
operation
External clock
operation
UCK ↓ → UO time
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UCK, UI
2 tMCLK*
—
ns
UCK ↑ → valid UI hold time
tSHIX
UCK, UI
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK
0.8 V
0.8 V
tSLOV
2.4 V
UC
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
UI
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
UCK
0.2 VCC
0.2 VCC
tSLOV
2.4 V
UC
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
UI
0.2 VCC 0.2 VCC
DS07–12xxx–1E
37
MB95430H Series
(7) Low-voltage Detection
(VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Value
Symbol
Min
Typ
Max
Unit
Remarks
Release voltage
VDL+
2.52
2.7
2.88
V
At power supply rise
Detection voltage
VDL-
2.42
2.6
2.78
V
At power supply fall
Hysteresis width
VHYS
70
100
—
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
tr
3000
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall)
tf
300
—
—
µs
Slope of power supply that the reset
detection signal generates within the
rating (VDL-)
Reset release delay time
td1
—
—
300
µs
Reset detection delay time
td2
—
—
20
µs
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
38
td1
DS07–12xxx–1E
MB95430H Series
(8) I2C Timing
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Standardmode
Fast-mode Unit
Min
Max
Min
Max
0
100
0
400
kHz
SCL, SDA
4.0
—
0.6
—
µs
Symbol Pin name Condition
SCL clock frequency
fSCL
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHD;STA
SCL
SCL clock “L” width
tLOW
SCL
4.7
—
1.3
—
µs
SCL clock “H” width
tHIGH
SCL
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
0
3.45*2
0
0.9*3
µs
(Repeated) START condition hold time
SCL ↑ → SDA ↓
tSU;STA
Data hold time
SCL ↓ → SDA ↓↑
tHD;DAT
SCL, SDA
Data setup time
SDA ↓↑ → SCL ↑
tSU;DAT
SCL, SDA
0.25
—
0.1
—
µs
STOP condition setup time
SCL ↑ → SDA ↑
tSU;STO
SCL, SDA
4
—
0.6
—
µs
tBUF
SCL, SDA
4.7
—
1.3
—
µs
Bus free time between STOP condition
and START condition
SCL, SDA
R = 1.7 kΩ,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT ≥ 250ns is fulfilled.
tWAKEUP
SDA
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL
tHD;STA
tSU;DAT
fSCL
tSU;STA
tSU;STO
(Continued)
DS07–12xxx–1E
39
MB95430H Series
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Sym- Pin
Condition
bol name
Value*2
Min
Max
Unit
Remarks
SCL clock “L”
width
tLOW SCL
(2 + nm/2)tMCLK − 20
—
ns
Master mode
SCL clock “H”
width
tHIGH SCL
(nm/2)tMCLK − 20
(nm/2)tMCLK + 20
ns
Master mode
START
SCL,
condition hold tHD;STA
SDA
time
(−1 + nm/2)tMCLK − 20
(−1 + nm)tMCLK + 20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value
is applied.
STOP
condition
setup time
tSU;STO
SCL,
SDA
(1 + nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
Master mode
START
condition
setup time
tSU;STA
SCL,
SDA
(1 + nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
Master mode
tBUF
SCL,
SDA
(2 nm + 4)tMCLK − 20
—
ns
tHD;DAT
SCL,
SDA
3 tMCLK − 20
—
ns
Master mode
ns
Master mode
When assuming
that “L” of SCL is
not extended,
the minimum
value is applied
to first bit of
continuous data.
Otherwise, the
maximum value
is applied.
ns
Minimum value
is applied to
interrupt at 9th
SCL↓. Maximum
value is applied
to the interrupt at
the 8th SCL↓.
Bus free time
between
STOP
condition and
START
condition
Data hold
time
Data setup
time
tSU;DAT
SCL,
SDA
Setup time
between
clearing inter- tSU;INT SCL
rupt and SCL
rising
R = 1.7 kΩ,
C = 50 pF*1
(−2 + nm/2)tMCLK − 20
(nm/2)tMCLK − 20
(−1 + nm/2)tMCLK + 20
(1 + nm/2)tMCLK + 20
(Continued)
40
DS07–12xxx–1E
MB95430H Series
(Continued)
Parameter
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Sym- Pin
Condition
Unit
Remarks
bol name
Min
Max
SCL clock “L” width
tLOW
SCL
4 tMCLK − 20
—
ns
At reception
SCL clock “H” width
tHIGH
SCL
4 tMCLK − 20
—
ns
At reception
START condition
detection
tHD;STA
SCL,
SDA
2 tMCLK − 20
—
ns
Undetected when 1
tMCLK is used at
reception
STOP condition
detection
tSU;STO
SCL,
SDA
2 tMCLK − 20
—
ns
Undetected when 1
tMCLK is used at
reception
RESTART condition
SCL,
tSU;STA
detection condition
SDA
2 tMCLK − 20
—
ns
Undetected when 1
tMCLK is used at
reception
2 tMCLK − 20
—
ns
At reception
Bus free time
tBUF
SCL,
SDA
Data hold time
tHD;DAT
SCL,
SDA
2 tMCLK − 20
—
ns
At slave
transmission mode
Data setup time
tSU;DAT
SCL,
SDA
tLOW − 3 tMCLK − 20
—
ns
At slave
transmission mode
Data hold time
tHD;DAT
SCL,
SDA
0
—
ns
At reception
Data setup time
tSU;DAT
SCL,
SDA
tMCLK − 20
—
ns
At reception
Oscillation
stabilization wait
time
+2 tMCLK − 20
—
ns
SCL,
SDA↓ → SCL↑
tWAKEUP
SDA
(at wakeup function)
R = 1.7 kΩ,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
See “(2) Source Clock/Machine Clock” for tMCLK.
m represents the CS4 bit and CS3 bit (bit 4 and bit 3) in the I2C clock control register (ICCR0).
n represents the CS2 bit to CS0 bit (bit 2 to bit 0) in the I2C clock control register (ICCR0).
The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
*2: •
•
•
•
DS07–12xxx–1E
41
MB95430H Series
(9) Voltage Compare Timing
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Pin name
Value
Min
Typ
Max
Unit
Remarks
Voltage range
CMPn_P,
CMPn_N
(n = 0,1,2,3)
0
—
VCC − 1.3
V
Offset voltage
CMPn_P,
CMPn_N
(n = 0,1,2,3)
−10
—
+10
mV
Delay time
CMPn_O
(n = 0,1,2,3)
—
650
1210
ns
5 mV overdrive
—
140
420
ns
50 mV overdrive
—
—
1210
ns
Power down recovery
PD: 1 → 0
0
—
—
ns
Power down effective
PD: 0 → 1
Output: “H” level
—
—
1210
ns
Output stabilization time
at power up
Power down delay
Power up stabilization time
42
CMPn_O
(n = 0,1,2,3)
CMPn_O
(n = 0,1,2,3)
DS07–12xxx–1E
MB95430H Series
(9) Operational Amplifier Timing
• Open Loop Configuration
(VCC = 4.0 V to 5.5 V, TA = −40°C to +85°C)
Parameter
Pin name
Value
Min
Typ
Max
Unit
Remarks
Input voltage range
OPAMP_P,
OPAMP_N
0.1
—
1.5
V
Output voltage range
OPAMP_O
0.1
—
VCC − 0.1
V
Output resistor load
OPAMP_O
220k
—
—
ohm
Output capacitor load
OPAMP_O
—
—
20
pF
Offset voltage
OPAMP_O
—
—
10
mV
Open loop bandwidth
OPAMP_O
3
—
—
MHz
Open loop gain
OPAMP_O
75
85
—
dB
AD loading
Common mode rejection ratio OPAMP_O
60
—
—
dB
AD loading
Power supply rejection ratio
OPAMP_O
65
—
—
dB
Power down recovery time
OPAMP_O
—
—
200
µs
Slew rate
OPAMP_O
0.3
—
—
V/µs
Large signal response
OPAMP_O
—
—
6
µs
Small signal response
OPAMP_O
—
—
500
ns
Output stabilization time
OPAMP_O
—
—
60
µs
DS07–12xxx–1E
Minimum driving
resistor value
AD loading
(maximum ESR = 10k)
After changes in
values of RES0-RES2
43
MB95430H Series
• Closed Loop Configuration
(VCC = 4.0 V to 5.5 V, TA = −40°C to +85°C)
Parameter
Pin name
Value
Unit
Remarks
Min
Typ
Max
Minimum input voltage range OPAMP_P,
(10x, 20x, 60x)
OPAMP_N
—
0.07
0.09
V
Minimum input voltage range OPAMP_P,
(30x, 40x, 50x)
OPAMP_N
—
0.07
0.10
V
Maximum input voltage range OPAMP_P,
(10x, 20x, 30x, 40x, 50x, 60x) OPAMP_N
—
—
VCC/Gain
V
Output voltage range
OPAMP_O
0.1
—
VCC − 0.1
V
Output capacitor load
OPAMP_O
—
—
20
pF
Closed loop bandwidth
OPAMP_O
1
—
—
MHz AD loading
Closed loop gain
OPAMP_O
10
—
60
V/V Selectable
Closed loop gain error*
(10x, 20x, 30x, 40x, 50x)
OPAMP_O
—
—
±10%
—
Closed loop gain error*
(60x)
OPAMP_O
—
—
±15%
—
Power down recovery time
OPAMP_O
—
—
200
µs
Slew rate
OPAMP_O
0.3
—
—
V/µs
Large signal response
OPAMP_O
—
—
6
µs
Small signal response
OPAMP_O
—
—
500
ns
Output stabilization time
OPAMP_O
—
—
60
µs
AD loading
(maximum ESR = 10k)
After changes in
values of RES0-RES2
*: Gain error = 1 − (actual gain / design gain)
44
DS07–12xxx–1E
MB95430H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Resolution
Total error
Linearity error
—
Differential linear
error
Value
Unit
Min
Typ
Max
—
—
10
bit
−3
—
+3
LSB
−2.5
—
+2.5
LSB
−1.9
—
+1.9
LSB
Remarks
Zero transition
voltage
VOT
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
VCC − 4.5 LSB
VCC − 2 LSB
VCC + 0.5 LSB
V
0.9
—
16500
µs
4.5 V ≤ VCC ≤ 5.5 V
1.8
—
16500
µs
4.0 V ≤ VCC < 4.5 V
0.6
—
∞
µs
4.5 V ≤ VCC ≤ 5.5 V,
with external
impedance < 5.4 kΩ
1.2
—
∞
µs
4.0 V ≤ VCC < 4.5 V,
with external
impedance < 2.4 kΩ
Compare time
Sampling time
—
—
Analog input current
IAIN
−0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
DS07–12xxx–1E
45
MB95430H Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
1.95 kΩ (Max)
17 pF (Max)
4.0 V ≤ VCC < 4.5 V
8.98 kΩ (Max)
17 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
External impedance [kΩ]
External impedance [kΩ]
100
90
80
70
60
(VCC ≥ 4.5 V)
50
(VCC ≥ 4.0 V)
40
30
20
10
18
16
14
12
(VCC ≥ 4.5 V)
10
(VCC ≥ 4.0 V)
8
6
4
2
0
0
0
2
4
6
8
10
12
Minimum sampling time [μs]
14
0
1
2
3
4
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
46
DS07–12xxx–1E
MB95430H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
2 LSB
3FDH
Digital output
Digital output
3FDH
004H
003H
Actual conversion
characteristic
3FEH
3FEH
VOT
{1 LSB × (N-1) + 0.5 LSB}
004H
VNT
003H
1 LSB
002H
002H
001H
Actual conversion
characteristic
Ideal characteristic
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC - VSS
(V)
1024
N
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
DS07–12xxx–1E
47
MB95430H Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
002H
Digital output
Digital output
003H
Actual conversion
characteristic
Ideal
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
VSS
Analog input
VCC
VSS
Linearity error
3FFH
3FEH
Ideal characteristic
(N+1)H
Actual conversion
characteristic
{1 LSB × N + VOT}
VFST
(measurement
value)
VNT
004H
Digital output
Digital output
3FDH
002H
VCC
Differential linearity error
Actual conversion
characteristic
V(N+1)T
NH
VNT
(N-1)H
Actual conversion
characteristic
003H
Analog input
Ideal
characteristic
Actual conversion
characteristic
(N-2)H
001H
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB × N + VOT}
Linearity error
=
of digital output N
1 LSB
N
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
48
DS07–12xxx–1E
MB95430H Series
6. Flash Memory Write/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.2*1
0.5*2
s
The time of writing 00H prior to
erasure is excluded.
Sector erase time
(16 Kbyte sector)
—
0.5*1
7.5*2
s
The time of writing 00H prior to
erasure is excluded.
Byte writing time
—
21
6100*2
µs
System-level overhead is excluded.
Erase/write cycle
100000
—
—
cycle
Power supply voltage at erase/
write
3.0
—
5.5
V
Flash memory data retention
time
20*3
—
—
year Average TA = +85°C
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 3.0 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85°C).
DS07–12xxx–1E
49
MB95430H Series
■ MASK OPTIONS
No.
Part Number
MB95F432H
MB95F433H
MB95F434H
Selectable/Fixed
MB95F432K
MB95F433K
MB95F434K
Fixed
1
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
2
Reset
50
With dedicated reset input
Without dedicated reset input
DS07–12xxx–1E
MB95430H Series
■ ORDERING INFORMATION
Part Number
Package
MB95F432HPMC-G-SNE2
MB95F432KPMC-G-SNE2
MB95F433HPMC-G-SNE2
MB95F433KPMC-G-SNE2
MB95F434HPMC-G-SNE2
MB95F434KPMC-G-SNE2
32-pin plastic LQFP
(FPT-32P-M30)
MB95F432HP-G-SH-SNE2
MB95F432KP-G-SH-SNE2
MB95F433HP-G-SH-SNE2
MB95F433KP-G-SH-SNE2
MB95F434HP-G-SH-SNE2
MB95F434KP-G-SH-SNE2
32-pin plastic SH-DIP
(DIP-32P-M06)
DS07–12xxx–1E
51
MB95430H Series
■ PACKAGE DIMENSION
32-pin plastic LQFP
Lead pitch
0.80 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm MAX
(FPT-32P-M30)
32-pin plastic LQFP
(FPT-32P-M30)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.05
* 7.00±0.10(.276±.004)SQ
0.13 –0.00
+.002
24
.005 –.000
17
16
25
0.10(.004)
Details of "A" part
1.60 MAX
(Mounting height)
(.063) MAX
INDEX
0.25(.010)
9
32
0~7°
1
0.80(.031)
+.003
.014 –.001
C
"A"
8
+0.08
0.35 –0.03
0.20(.008)
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
M
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
52
DS07–12xxx–1E
MB95430H Series
(Continued)
32-pin plastic SDIP
Lead pitch
1.778 mm
Low space
10.16 mm
Sealing method
Plastic mold
(DIP-32P-M06)
32-pin plastic SDIP
(DIP-32P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
+0.20
*28.00 –0.30
1.102
+.008
–.012
INDEX
*8.89±0.25
(.350±.010)
1.02
.040
+0.30
–0.20
+.012
–.008
+0.70
4.70 –0.20
0.51(.020)
MIN.
+.028
.185 –.008
3.30
+0.20
–0.30
+.008
.130 –.012
+0.03
0.27 –0.07
+.001
.011 –.003
1.27(.050)
MAX.
C
1.778(.070)
10.16(.400)
+0.08
0.48 –0.12
+.003
0.25(.010)
M
.019 –.005
2003-2010 FUJITSU SEMICONDUCTOR LIMITED D32018S-c-1-3
0~15°
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07–12xxx–1E
53
MB95430H Series
MEMO
54
DS07–12xxx–1E
MB95430H Series
MEMO
DS07–12xxx–1E
55
MB95430H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department