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Using the WM8753 for Bluetooth Record
(PCM to I2S Conversion)
INTRODUCTION
2
The need to convert PCM to I S data format is desirable in many multi-media phones with Bluetooth
(BT) capability where the signal across the BT link is to be recorded.
Figure 1 Typical Call Record Block Diagram
This conversion is required as the majority of BT IC’s at present only output PCM formatted data
while many DSP’s will be setup to use I2S formatted data (Left Justified or Right Justified data may
also be used).
The BT IC outputs PCM formatted data as it is ideal for voice signals. It is mono only and ideal for
reduced sampling rates and bit rate due to only one channel being considered.
1/fs
1 VXCLK
VXFS
VXCLK
VXDIN/
VXDOUT
1
2
3
n-2 n-1
MSB
n
LSB
Figure 2 PCM Data Format Mode A
Figure 3 PCM Data Format Mode B
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
February 2005, Rev 1.5
Copyright 2005 Wolfson Microelectronics plc
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The DSP will typically use one of the standard audio data formats as it will be used to output stereo
audio to headphones or on-phone speakers.
Figure 4 I2S Justified Data Format
The rising edge of VXFS alone signifies the start of a new frame in PCM format. The falling edge of
VXFS is ignored. As can be seen in Figure 4, LRC low signifies left channel data while LRC high
signifies right channel data.
There is no direct way to input PCM format data into an interface expecting I2S format data, a
conversion must take place.
Due to the flexibility offered by the WM8753 this conversion can be done. There are some limitations
however due to the WM8753 not being specifically designed to offer this conversion.
The aim of this application note is to provide a clear understanding of the WM8753 interfaces and
their interaction. From this, it should become clear as to the possible solutions offered by the
WM8753 and the considerations that must be made before design.
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WM8753 AUDIO INTERFACE OPTIONS
The WM8753 has two very flexible audio interfaces. One interface has a connection to a mono voice
DAC and a stereo ADC. The other interface has a connection to a stereo HiFi DAC. The flexibility
offered by the WM8753 allows interconnection between the two interfaces as shown in Figure 5.
Figure 5 Audio Interface Routing Options
As can be seen, the Voice Interface (VXFS, VXCLK, VXDOUT, VXDIN) may be routed to the VX
DAC and ADC only. The HiFi Interface (LRC, BCLK, ADCDAT, DACDAT) can be routed to the HiFi
DAC, VX DAC and ADC. The different routing options are selected by setting the IFMODE register
bits.
Both interfaces can be configured for any data format which is one of the advantages of the WM8753
making data conversion possible. The Voice Interface uses the PFORMAT and PWL register bits to
set the data format and word length while the HiFi Interface uses the FORMAT and WL register bits.
Refer to tables Table 1, Table 2 and Table 3.
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IFMODE[1:0]
DAC DATA
DAC FRAME SYNC
DAC BIT CLK
DAC WORDLENGTH
DAC FORMAT
00
01
10
11
DACDAT
DACDAT
DACDAT
DACDAT
LRC
LRC
LRC
LRC
BCLK
BCLK
BCLK
BCLK
WL[1:0]
WL[1:0]
WL[1:0]
WL[1:0]
FORMAT[1:0]
FORMAT[1:0]
FORMAT[1:0]
FORMAT[1:0]
Table 1 Hi-FI DAC Audio Interface Configuration
IFMODE[1:0]
ADC DATA
ADC FRAME SYNC
ADC BIT CLK
ADC WORDLENGTH
ADC FORMAT
00
01
10
11
VXDOUT
ADCDAT
ADCDAT
ADCDAT
VXFS
LRC
LRC
VXFS
VXCLK
BCLK
BCLK
BCLK
PWL[1:0]
PWL[1:0]
PWL[1:0]
PWL[1:0]
PFORMAT[1:0]
PFORMAT[1:0]
PFORMAT[1:0]
PFORMAT[1:0]
VXDAC
WORDLENGTH
VXDAC FORMAT
PWL[1:0]
PWL[1:0]
-
PFORMAT[1:0]
PFORMAT[1:0]
-
Table 2 ADC Audio Interface Configuration
IFMODE[1:0]
00
01
10
11
VXDAC DATA VXDAC FRAME SYNC VXDAC BIT CLK
VXDIN
DACDAT
-
VXFS
LRC
-
VXCLK
BCLK
-
Table 3 Voice DAC Audio Interface Configuration
See the latest WM8753 datasheet for more details.
To be able to convert PCM to I2S data format the following is needed:
INTERFACE 1 (PCM INPUT)
INTERFACE 2 (I2S OUTPUT)
PCM Frame Clock
I2S Frame Clock
PCM Data Clock
I2S Data Clock
PCM Digital Data Input
I S Digital Data Output
2
Table 4 Interface Signal Requirements
Figure 5 shows that IFMODE[1:0]=00 offers the best routing option to achieve a successful data
conversion based on the signal requirements shown in Table 4.
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IFMODE[1:0]=00 OPTIONS
2
BCLK
LRC
DATA
DACDAT
ADCDAT
BCLK
LRC
VXDIN
VXDOUT
I2S
DATA
a BCLK
Dat
LRC
Data BCLK
PCM
VXFS
VXCLK
LRC
DATA
PCM data input to Voice Interface – I S data output from HiFi Interface
Figure 6 IFMODE[1:0] = 00 Unsynchronized Output Example
The diagram shown in Figure 6 makes it immediately obvious that this combination of direct interface
usage will not work. The main reason for this is stated in the note under the diagram; “ADCDAT is
synchronized with the Voice (VX) interface”. The ADC data output is not synchronized to the HiFi
interface meaning that the data will not be justified correctly for the I2S data output.
Whether the WM8753 is in Master mode (i.e. clocks are output) or Slave mode (i.e. clocks are input),
the ADCDAT (I2S data output) is synchronised to the PCM timing rather than the required I2S timing.
Figure 7 is a scope capture of the setup timing described. The Voice and HiFi interfaces are in
Master mode. The internal routing path is shown in Figure 11. As can be seen, the PCM data format
(Mode A) is correct. The I2S frame clock (LRC) is correct but, the data is not sitting correctly within
the frame.
Figure 7 Out of Sync I2S Output Data Format
The solution to this synchronization issue requires the use of an external switch circuit. An example
setup is shown in Figure 8.
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BCLK
DATA
LRC
DACDAT
ADCDAT
BCLK
ta BCLK
Da
S
I2
LRC
LRC
DATA
VXDIN
VXCLK
VXDOUT
DATA
a
Dat BCLK
PCM
VXFS
LRC
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Figure 8 Possible Solution 1
The diagram in Figure 8 allows the VXDAC and ADC to be used purely for phone call purposes while
the HiFi DAC may be used for audio playback of an MP3 file for example. This solution also allows
the PCM to I2S conversion to take place.
One limitation of this solution is that a single frame sync is used meaning that both the PCM and I2S
data must be running at the same sample rate. This also means that the frame sync edges must be
the same for both PCM and I2S data. As stated previously, in PCM mode of the WM8753, it is the
rising edge only that signifies the start of a new frame, the falling edge is ignored. This is also true for
the many BT chips. Due to this, it is possible to apply an I2S frame sync signal to both the BT chip
and the DSP via the sw/mux. In this case the ADCDAT is synchronized with the correct LRC and
2
BITCLK. The BT chip will output data on the rising edge of VXFS (right channel data in I S format).
If monitored on a scope, both interfaces will appear to have I2S timing and data format.
In this mode, the WM8753 must be the Master.
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PCM data input to HiFi Interface – I2S data output from Voice Interface
Voice Codec + Hi-Fi DAC
(IFMODE[1:0] = 00)
PFORMAT[1:0]
PWL[1:0]
VXCLKINV
BCLK
LRC
Data
Dat
DACDAT
BCLK
SW/
MUX
ADCDAT
LRC
PCM
I2S
VXDIN
VXDOUT
VXFS
VXCLK
DATA
BCLK
LRC
HiFi DAC
a
DATA
ADC
BCLK
LRC
DATA
VX DAC
FORMAT[1:0]
WL[1:0]
BCLKINV
SW/
MUX
GPIO
DSP
BT CHIP
Figure 9 IFMODE[1:0] = 00 Possible Solution 2
Figure 9 shows a possible solution where the HiFi DAC is used for the PCM data input from the BT
chip. This allows the PCM data to use a dedicated interface and the I2S data to have its own
interface. This has the obvious advantage of allowing each interface to have individual frame sync
signals that can be used at different sample rates and high-low pulse widths as required. An example
of the interface clocking is shown in Figure 10. It should be noted that the ADC data on VXDOUT is
positioned in the right channel (VXFS high) due to the signal routing path passing through the right
ADC only.
The additional sw/mux blocks are required to allow audio playback to be routed through the stereo
HiFi DAC from the DSP.
In this mode, the WM8753 can be the Master or Slave.
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Figure 10 Synchronized I2S Output Data Format
SOLUTION COSIDERATIONS
There are a number of considerations that must be made for either of the suggested solutions within
this document. These are summarised in Table 5 for reference.
Solution 1
SUMMARY
CONSIDERATION
Only one frame sync is available for the
2
PCM to I S conversion.
1. Are multiple sample rates required?
If so it is not possible to use this
solution.
2. Does the BT Chip only require a
rising edge on frame sync or does
the
falling
edge
have
any
significance? If the falling edge is a
requirement then it is not possible
to use this solution unless the DSP
can deal with a PCM type frame
sync in which case this can be the
common format.
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Are all additional signal paths catered
for?
There may be many other routing paths
required in addition to the PCM to I2S
conversion. The system designer
should ensure that all routing is
possible around the conversion path.
A common data clock is used for
synchronization purposes.
Can both the BT Chip and the DSP deal
with the same data clock rate? This
should not be an issue but needs to be
confirmed for the relevant IC’s used.
An external switch or multiplexer is
required.
The component chosen for this signal
selection must be able to deal with
switching as fast as the data clock will
run.
The WM8753 must be the Master
device.
Can both DSP and BT Chip work as
slaves? If not it is not possible to use
this solution.
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Solution 2
To allow stereo playback through the
HiFi DAC, external switches or
multiplexers are required.
The components chosen for this signal
selection must be able to deal with
switching as fast as the data clock will
run.
Are all additional signal paths catered
for?
There may be many other routing paths
required in addition to the PCM to I2S
conversion. The system designer
should ensure that all routing is
possible around the conversion path.
Table 5 Solution Comparison
WM8753 SOFTWARE CONSIDERATIONS
The PCM mono mode described in the WM8753 datasheet (Audio Data Formats section) is not a
setup option for the HiFi DAC. The HiFi DAC must be set up to work in DSP mode by setting the
FORMAT and WL bits found in register R4 (0x04h). Setting the FORMAT[1:0] = 11 sets DSP mode
active, the word length may be set between 16 and 32 bits long using the WL[1:0] bits. The word
length is system specific.
The ADC should be set to output data in I2S, Left Justified, Right Justified or DSP mode using the
PFORMAT[1:0] and PWL[1:0] bits found in register R3 (0x03h).
Please refer to the latest revision of the WM8753 datasheet for more details on the data format and
other settings required to set the required path active.
For the list of register settings required to set the routing paths as shown in Figure 11 and Figure 12,
refer to Table 6 and Table 7.
CONCLUSION
PCM to I2S data format conversion is a requirement for many new multi-media phone applications.
The WM8753, although not specifically designed for such functionality, does offer the ability to
achieve the conversion.
Solution 1 has the advantage of allowing easier internal routing for additional paths with minimal
external cost. It does have the limitation that a single frame sync is available relying heavily on a
common sample rate being used between the BT Chip and the DSP. It also requires the BT Chip or
the DSP to be flexible with the frame syncs that they can accept allowing a common signal to be
applied to both. They both must work as slaves with the WM8753 as master to ensure
synchronisation.
Solution 2 offers the advantage of two completely independent interfaces that can be run with
different data formats at different sample rates. The WM8753 can be master or slave. This solution
relies a lot less on the capability of the DSP and BT Chip. The downside is that the cost of external
components is higher than solution 1 and the external routing design is slightly more complex.
The solutions offered within this document each have their advantages over the other. The decision
over which one is better is system specific and needs to be decided by the system designer based
on routing requirements and capability of the DSP and BT Chip used.
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APPENDIX
Figure 11 WM8753 Internal Routing Path for Solution 1
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REGISTER
VALUE
REGISTER BITS
R3 (03h)
0x14a
ADCDOP=1 [ADC data output to ADCDAT and VXDOUT]
PMS=1 [Voice Interface is Master]
R4 (04h)
0x04a
MS=1 [HiFi Interface is Master]
R5 (05h)
0x023
ADCTRI=0 [ADCDAT output is set to standard operation]
R7 (07h)
0x097
PBMODE=010 [VXCLK is equal to MCLK/4]
BMODE=010 [BCLK is equal to MCLK/4]
R20 (14h)
0x0d0
VMIDSEL=01 [Power up with 50kΩ]
VREF=1 [Power up]
R21 (15h)
0x004
ADCR=1 [Power up]
R23 (17h)
0x00c
RECMIX=1 [Power up]
MONOMIX=1 [Power up]
R33 (21h)
0x00a
VDAC=1 [Power up]
MSEL=1 [Mono mixer output switched into REC mixer input]
MRECVOL=010 [REC mixer volume set to 0dB]
R39 (27h)
0x05b
VXD2MO=1 [Voice DAC output switched into Mono mixer]
VXD2MOVOL=011 [VXD2MO volume set to 0dB]
R46 (2eh)
0x008
RADCSEL=10 [REC mixer output selected as RADC input]
Notes:
1.
2.
The register bit descriptions only list changes from default.
All other registers and register bits are left in their default state.
Table 6 Register Settings Required for the Solution 1 Internal Routing Path
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Figure 12 WM8753 Internal Routing Path for Solution 2
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REGISTER
VALUE
R1 (01h)
0x000
R3 (03h)
0x14a
REGISTER BITS
DACMU=0 [DAC mute off]
ADCDOP=1 [ADC data output to ADCDAT and VXDOUT]
PMS=1 [Voice Interface is Master]
R4 (04h)
0x04b
MS=1 [HiFi Interface is Master]
FORMAT=11 [DSP mode selected]
R5 (05h)
0x013
VXDTRI=0 [VXDOUT output is set to standard operation]
R7 (07h)
0x097
PBMODE=010 [VXCLK is equal to MCLK/4]
BMODE=010 [BCLK is equal to MCLK/4]
R20 (14h)
0x0c8
VMIDSEL=01 [Power up with 50kΩ]
VREF=1 [Power up]
DACL=1 [Power up]
R21 (15h)
0x004
ADCR=1 [Power up]
R23 (17h)
0x00c
RECMIX=1 [Power up]
MONOMIX=1 [Power up]
R33 (21h)
0x008
MSEL=1 [Mono mixer output switched into REC mixer input]
MRECVOL=000 [REC mixer volume set to +6dB]
R38 (26h)
0x150
LD2MO=1 [Left DAC switched into Mono mixer]
R46 (2eh)
0x008
RADCSEL=10 [REC mixer output selected as RADC input]
Notes:
1.
2.
The register bit descriptions only list changes from default.
All other registers and register bits are left in their default state.
Table 7 Register Settings Required for the Solution 2 Internal Routing Path
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APPLICATION SUPPORT
If you require more information or require technical support please contact Wolfson Microelectronics
Applications group through the following channels:
Email:
Telephone Apps:
Fax:
Mail:
[email protected]
(+44) 131 272 7070
(+44) 131 272 7001
Applications at the address on the last page.
or contact your local Wolfson representative.
Additional information may be made available from time to time on our web site at
http://www.wolfsonmicro.com
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