Standard Products UT28F256LVQLE Radiation-Hardened 32K x 8 PROM Data Sheet March 2007 www.aeroflex.com/radhard FEATURES QML Q & V compliant part - AC and DC testing at factory Programmable, read-only, asynchronous, radiationhardened, 32K x 8 memory - Supported by industry standard programmer No post-program conditioning required 65ns maximum address access time (-55 oC to +125 oC) Packaging options: - 28-lead 50-mil center flatpack (0.490 x 0.74) Three-state data bus VDD: 3.0Vto 3.6V Low operating and standby current - Operating: 50.0mA maximum @15.4MHz • Derating: 1.7mA/MHz - Standby: 1.0mA maximum (post-rad) Standard Microcircuit Drawing 5962-01517 Radiation-hardened process and design; total dose irradiation testing to MIL-STD-883, Method 1019 - PRODUCT DESCRIPTION The UT28F256LVQLE amorphous silicon redundant ViaLinkTM PROM is a high performance, asynchronous, radiation-hardened, 32K x 8 programmable memory device. The UT28F256LVQLE PROM features fully asychronous operation requiring no external clocks or timing strobes. An advanced radiation-hardened twin-well CMOS process technology is used to implement the UT28F256LVQLE. The combination of radiation-hardness, fast access time, and low power consumption make the UT28F256LQLE ideal for high speed systems designed for operation in radiation environments. Total dose: 100Krad to 1Megarad(Si) Onset LET: 40 MeV-cm2/mg SEL Immune >110 MeV-cm2/mg A(14:0) MEMORY ARRAY DECODER SENSE AMPLIFIER CE PE CONTROL LOGIC DQ(7:0) OE PROGRAMMING Figure 1. PROM Block Diagram 1 PIN NAMES DEVICE OPERATION The UT28F256LVQLE has three control inputs: Chip Enable (CE), Program Enable (PE), and Output Enable (OE); fifteen address inputs, A(14:0); and eight bidirectional data lines, DQ(7:0). CE is the device enable input that controls chip selection, active, and standby modes. Asserting CE causes IDD to rise to its active value and decodes the fifteen address inputs to select one of 32,768 words in the memory. PE controls program and read operations. During a read cycle, OE must be asserted to enable the outputs. A(14:0) Address CE Chip Enable OE Output Enable PE Program Enable DQ(7:0) Data Input/Data Output Table 1. Device Operation Truth Table 1 PIN CONFIGURATION OE PE CE I/O MODE MODE PE X 1 1 Three-state Standby A13 0 1 0 Data Out Read 1 0 0 Data In Program 1 1 0 Three-state Read 2 A14 1 28 VDD A12 2 27 A7 3 26 A6 A5 4 25 A8 5 24 A4 6 23 A9 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 DQ2 12 17 13 16 DQ5 DQ4 VSS 14 15 DQ3 Notes: 1. “X” is defined as a “don’t care” condition. 2. Device active; outputs disabled. ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS) SYMBOL PARAMETER LIMITS UNITS VDD DC supply voltage -0.3 to 6.0 V VI/O Voltage on any pin -0.5 to (VDD + 0.5) V TSTG Storage temperature -65 to +150 °C 1.5 W +175 °C Thermal resistance, junction-to-case 2 3.3 °C/W DC input current ±10 mA PD Maximum power dissipation TJ Maximum junction temperature ΘJC II Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Test per MIL-STD-883, Method 1012, infinite heat sink. 2 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITS VDD Positive supply voltage 3.0 to 3.6 V TC Case temperature range -55 to +125 °C VIN DC input voltage 0 to VDD V DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (VDD = 3.0V to 3.6V; -55°C < TC < +125°C) SYMBOL PARAMETER VIH High-level input voltage VIL Low-level input voltage VOL1 Low-level output voltage VOL2 CONDITION MINIMUM MAXIMUM 0.7VDD UNIT V 0.25VDD V IOL = 100μA, VDD = 3.0V VSS + 0.05 V Low-level output voltage IOL = 1.0mA, VDD = 3.0V VSS + 0.10 V VOH1 High-level output voltage IOH = -100μA, VDD = 3.0V VDD-0.15 V VOH2 High-level output voltage IOH = -1.0mA, VDD = 3.0V VDD-0.3 V CIN 1 Input capacitance, all inputs except PE ƒ = 1MHz, VDD = 3.3V VIN = 0V 15 Input Capacitance PE 20 Bidirectional I/O capacitance ƒ = 1MHz, VDD = 3.3V VOUT = 0V IIN Input leakage current VIN = 0V to VDD, all pins except PE VIN = VDD, PE only IOZ Three-state output leakage current VO = 0V to VDD VDD = 3.6V OE = 3.6V IOS 2,3 Short-circuit output current VDD = 3.6V, VO = VDD VDD = 3.6V, VO = 0V IDD1(OP)4 Supply current operating @15.4MHz (65ns product) CMOS input levels (IOUT = 0), VIL = 0.2V VDD, PE = 3.6V, VIH = 3.0V IDD2(SB) post-rad Supply current standby CMOS input levels VIL = VSS +0.25V CE = VDD - 0.25 VIH = VDD - 0.25V CIO 1 pF 15 pF -3 +3 35 μA μA -8 +8 μA 100 mA mA 50.0 mA 1.0 mA -100 Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rad(Si). 1. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. 1.7mA/MHz. 3 The chip enable-controlled access is initiated by CE going active while OE remains asserted, PE remains deasserted, and the addresses remain stable for the entire cycle. After the specified tELQV is satisfied, the eight-bit word addressed by A(14:0) appears at the data outputs DQ(7:0). READ CYCLE A combination of PE greater than VIH(min), and CE less than VIL(max) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output. Output enable-controlled access is initiated by OE going active while CE is asserted, PE is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tELQV have not been satisfied. An address access read is initiated by a change in address inputs while the chip is enabled with OE asserted and PE deasserted. Valid data appears on data output, DQ(7:0), after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time. AC CHARACTERISTICS READ CYCLE (Post-Radiation)* (VDD = 3.0V to 3.6V; -55°C < TC < +125°C) SYMBOL PARAMETER 28F256LV-65 MIN MAX tAVAV1 Read cycle time 65 tAVQV Read access time tAXQX2 Output hold time 0 ns tGLQX2 OE-controlled output enable time 0 ns tGLQV OE-controlled access time 35 ns tGHQZ OE-controlled output three-state time 35 ns tELQX2 CE-controlled output enable time tELQV CE-controlled access time 65 ns tEHQZ CE-controlled output three-state time 35 ns ns 65 0 Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 1E6 rads(Si). 1. Functional test. 2. Three-state is defined as a 200mV change from steady-state output voltage. 4 UNIT ns ns tAVAV A(14:0) CE tAVQV tELQX tEHQZ tELQV OE DQ(7:0) tGHQZ tAXQX tGLQV tGLQX tAVQV Figure 2. PROM Read Cycle transient radiation hardness and latchup immunity, Aeroflex Colorado Springs builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, Aeroflex Colorado Springs pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. RADIATION HARDNESS The UT28F256LVQLE PROM incorporates special design and layout features which allow operation in high-level radiation environments. Aeroflex Colorado Springs has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For RADIATION HARDNESS DESIGN SPECIFICATIONS 1 Total Dose 1E6 rad(Si) Latchup LET Threshold >110 MeV-cm2/mg Memory Cell LET Threshold >100 MeV-cm2/mg Logic SEU Onset LET >40 MeV-cm2/mg SEU Cross Section 2.5E-6 cm2/device Error rate - geosynchronous orbit, Adams 90% worst case environment 2.5E-12 errors/device day Note: 1. The PROM will not latchup during radiation exposure under recommended operating conditions. 5 200 ohms VREF=1.40V 90% 90% VDD 50pF 0V 10% 10% < 5ns < 5ns Input Pulses Notes: 1. 50pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point . Figure 3. AC Test Loads and Input Waveforms 6 k 0.015 0.008 PIN NO. 1 ID. 6 k 0.015 0.008 26 PLACES 0.050 BSC e -A- -B- D 0.740 MAX S1 (4) PLACES 0.000 MIN. E1 0.550 MAX b 0.022 7 0.015 28 PLACES 0.010 M H 0.036 M H A-B S D S 5 A-B S D S 5 TOP VIEW E 0.520 0.460 A 0.115 0.045 -D7 c 0.009 0.004 0.040 -H- -CQ 0.045 0.026 E2 0.180 MIN L 0.370 0.250 E3 0.030 MIN END VIEW Notes: 1. All exposed metalized areas to be plated per MIL-PRF-38535. 2. The lid is connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Dimension letters refer to MIL-STD-1835. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option. 7. With solder, increase maximum by 0.003. 8. Total weight is approximately 2.4 grams. Figure 5. 28-Lead 50-mil Center Flatpack (0.490 x 0.74) 7 ORDERING INFORMATION UT28F256LVQLE PROM: SMD 5962 * 01517 * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (X) = 28-lead Flatpack Class Designator: (Q) = Class Q (V) = Class V Device Type (04) = 65ns Access Time, CMOS compatible inputs and CMOS compatible outputs (05) = 65ns Access Time, CMOS compatible inputs and CMOS compatible outputs Extended Industrial Temp (-40cC to +125oC) Drawing Number: 01517 Total Dose: (F) = 3E5 rads(Si) (G) = 5E5 rads(Si) (H) = 1E6 rads(Si) (R) = 1E5 rads(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 4. Device type 03 available with total dose of 1E5 rads(Si) or 3E5 rads(Si). 8 UT28F256LVQLE PROM UT **** *** - * * * * * * Total Dose: ( ) = None Lead Finish: (A) = Solder (C) = Gold (X) = Optional Screening: (C) = Mil Temp (P) = Prototype (W) = Extended Industrial Temp (-40cC to +125oC) Package Type: (U) = 28-lead Flatpack Access Time: (65) = 65ns access time Device Type Modifier: (C) = CMOS compatible inputs and CMOS compatible outputs Device Type: (28F256LVQLE) = 3.3V, 32Kx8 One Time Programmable PROM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Military Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices have prototype assembly and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed and may not be specified. 5. Extended Industrial Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 6. Lead finish is gold only. 9 COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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